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(2006-08-06) rescue-bootcd

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This commit is contained in:
Valeriano A.R.
2006-08-06 00:00:00 +02:00
parent 2f796b816a
commit decb062d20
21091 changed files with 7076462 additions and 0 deletions
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10
extra/linux-2.6.10/include/asm-mips/8253pit.h Normal file
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/*
* 8253/8254 Programmable Interval Timer
*/
#ifndef _8253PIT_H
#define _8253PIT_H
#define PIT_TICK_RATE 1193182UL
#endif

47
extra/linux-2.6.10/include/asm-mips/a.out.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 - 1999, 2003 by Ralf Baechle
*/
#ifndef _ASM_A_OUT_H
#define _ASM_A_OUT_H
#ifdef __KERNEL__
#include <linux/config.h>
#endif
struct exec
{
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
unsigned a_text; /* length of text, in bytes */
unsigned a_data; /* length of data, in bytes */
unsigned a_bss; /* length of uninitialized data area for
file, in bytes */
unsigned a_syms; /* length of symbol table data in file,
in bytes */
unsigned a_entry; /* start address */
unsigned a_trsize; /* length of relocation info for text, in
bytes */
unsigned a_drsize; /* length of relocation info for data, in bytes */
};
#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
#ifdef __KERNEL__
#ifdef CONFIG_MIPS32
#define STACK_TOP TASK_SIZE
#endif
#ifdef CONFIG_MIPS64
#define STACK_TOP (current->thread.mflags & MF_32BIT_ADDR ? TASK_SIZE32 : TASK_SIZE)
#endif
#endif
#endif /* _ASM_A_OUT_H */

186
extra/linux-2.6.10/include/asm-mips/addrspace.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 99 Ralf Baechle
* Copyright (C) 2000, 2002 Maciej W. Rozycki
* Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
*/
#ifndef _ASM_ADDRSPACE_H
#define _ASM_ADDRSPACE_H
#include <linux/config.h>
#include <spaces.h>
/*
* Configure language
*/
#ifdef __ASSEMBLY__
#define _ATYPE_
#define _ATYPE32_
#define _ATYPE64_
#else
#define _ATYPE_ __PTRDIFF_TYPE__
#define _ATYPE32_ int
#define _ATYPE64_ long long
#endif
/*
* 32-bit MIPS address spaces
*/
#ifdef __ASSEMBLY__
#define _ACAST32_
#define _ACAST64_
#else
#define _ACAST32_ (_ATYPE_)(_ATYPE32_) /* widen if necessary */
#define _ACAST64_ (_ATYPE64_) /* do _not_ narrow */
#endif
/*
* Returns the kernel segment base of a given address
*/
#define KSEGX(a) ((_ACAST32_ (a)) & 0xe0000000)
/*
* Returns the physical address of a CKSEGx / XKPHYS address
*/
#define CPHYSADDR(a) ((_ACAST32_ (a)) & 0x1fffffff)
#define XPHYSADDR(a) ((_ACAST64_ (a)) & 0x000000ffffffffff)
#ifdef CONFIG_MIPS64
/*
* Memory segments (64bit kernel mode addresses)
* The compatibility segments use the full 64-bit sign extended value. Note
* the R8000 doesn't have them so don't reference these in generic MIPS code.
*/
#define XKUSEG 0x0000000000000000
#define XKSSEG 0x4000000000000000
#define XKPHYS 0x8000000000000000
#define XKSEG 0xc000000000000000
#define CKSEG0 0xffffffff80000000
#define CKSEG1 0xffffffffa0000000
#define CKSSEG 0xffffffffc0000000
#define CKSEG3 0xffffffffe0000000
#define CKSEG0ADDR(a) (CPHYSADDR(a) | CKSEG0)
#define CKSEG1ADDR(a) (CPHYSADDR(a) | CKSEG1)
#define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3)
#else
#define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
#define CKSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
#define CKSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
#define CKSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
/*
* Map an address to a certain kernel segment
*/
#define KSEG0ADDR(a) (CPHYSADDR(a) | KSEG0)
#define KSEG1ADDR(a) (CPHYSADDR(a) | KSEG1)
#define KSEG2ADDR(a) (CPHYSADDR(a) | KSEG2)
#define KSEG3ADDR(a) (CPHYSADDR(a) | KSEG3)
/*
* Memory segments (32bit kernel mode addresses)
* These are the traditional names used in the 32-bit universe.
*/
#define KUSEG 0x00000000
#define KSEG0 0x80000000
#define KSEG1 0xa0000000
#define KSEG2 0xc0000000
#define KSEG3 0xe0000000
#define CKUSEG 0x00000000
#define CKSEG0 0x80000000
#define CKSEG1 0xa0000000
#define CKSEG2 0xc0000000
#define CKSEG3 0xe0000000
#endif
/*
* Cache modes for XKPHYS address conversion macros
*/
#define K_CALG_COH_EXCL1_NOL2 0
#define K_CALG_COH_SHRL1_NOL2 1
#define K_CALG_UNCACHED 2
#define K_CALG_NONCOHERENT 3
#define K_CALG_COH_EXCL 4
#define K_CALG_COH_SHAREABLE 5
#define K_CALG_NOTUSED 6
#define K_CALG_UNCACHED_ACCEL 7
/*
* 64-bit address conversions
*/
#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
#define XKPHYS_TO_PHYS(p) ((p) & TO_PHYS_MASK)
#define PHYS_TO_XKPHYS(cm,a) (0x8000000000000000 | ((cm)<<59) | (a))
#if defined (CONFIG_CPU_R4300) \
|| defined (CONFIG_CPU_R4X00) \
|| defined (CONFIG_CPU_R5000) \
|| defined (CONFIG_CPU_NEVADA) \
|| defined (CONFIG_CPU_MIPS64)
#define KUSIZE 0x0000010000000000 /* 2^^40 */
#define KUSIZE_64 0x0000010000000000 /* 2^^40 */
#define K0SIZE 0x0000001000000000 /* 2^^36 */
#define K1SIZE 0x0000001000000000 /* 2^^36 */
#define K2SIZE 0x000000ff80000000
#define KSEGSIZE 0x000000ff80000000 /* max syssegsz */
#define TO_PHYS_MASK 0x0000000fffffffff /* 2^^36 - 1 */
#endif
#if defined (CONFIG_CPU_R8000)
/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
#define KUSIZE 0x0000010000000000 /* 2^^40 */
#define KUSIZE_64 0x0000010000000000 /* 2^^40 */
#define K0SIZE 0x0000010000000000 /* 2^^40 */
#define K1SIZE 0x0000010000000000 /* 2^^40 */
#define K2SIZE 0x0001000000000000
#define KSEGSIZE 0x0000010000000000 /* max syssegsz */
#define TO_PHYS_MASK 0x000000ffffffffff /* 2^^40 - 1 */
#endif
#if defined (CONFIG_CPU_R10000)
#define KUSIZE 0x0000010000000000 /* 2^^40 */
#define KUSIZE_64 0x0000010000000000 /* 2^^40 */
#define K0SIZE 0x0000010000000000 /* 2^^40 */
#define K1SIZE 0x0000010000000000 /* 2^^40 */
#define K2SIZE 0x00000fff80000000
#define KSEGSIZE 0x00000fff80000000 /* max syssegsz */
#define TO_PHYS_MASK 0x000000ffffffffff /* 2^^40 - 1 */
#endif
/*
* Further names for SGI source compatibility. These are stolen from
* IRIX's <sys/mips_addrspace.h>.
*/
#define KUBASE 0
#define KUSIZE_32 0x0000000080000000 /* KUSIZE
for a 32 bit proc */
#define K0BASE_EXL_WR 0xa800000000000000 /* exclusive on write */
#define K0BASE_NONCOH 0x9800000000000000 /* noncoherent */
#define K0BASE_EXL 0xa000000000000000 /* exclusive */
#ifndef CONFIG_CPU_R8000
/*
* The R8000 doesn't have the 32-bit compat spaces so we don't define them
* in order to catch bugs in the source code.
*/
#define COMPAT_K1BASE32 0xffffffffa0000000
#define PHYS_TO_COMPATK1(x) ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
#endif
#define KDM_TO_PHYS(x) (_ACAST64_ (x) & TO_PHYS_MASK)
#define PHYS_TO_K0(x) (_ACAST64_ (x) | CAC_BASE)
#endif /* _ASM_ADDRSPACE_H */

174
extra/linux-2.6.10/include/asm-mips/arc/hinv.h Normal file
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/*
* ARCS hardware/memory inventory/configuration and system ID definitions.
*/
#ifndef _ASM_ARC_HINV_H
#define _ASM_ARC_HINV_H
#include <asm/arc/types.h>
/* configuration query defines */
typedef enum configclass {
SystemClass,
ProcessorClass,
CacheClass,
#ifndef _NT_PROM
MemoryClass,
AdapterClass,
ControllerClass,
PeripheralClass
#else /* _NT_PROM */
AdapterClass,
ControllerClass,
PeripheralClass,
MemoryClass
#endif /* _NT_PROM */
} CONFIGCLASS;
typedef enum configtype {
ARC,
CPU,
FPU,
PrimaryICache,
PrimaryDCache,
SecondaryICache,
SecondaryDCache,
SecondaryCache,
#ifndef _NT_PROM
Memory,
#endif
EISAAdapter,
TCAdapter,
SCSIAdapter,
DTIAdapter,
MultiFunctionAdapter,
DiskController,
TapeController,
CDROMController,
WORMController,
SerialController,
NetworkController,
DisplayController,
ParallelController,
PointerController,
KeyboardController,
AudioController,
OtherController,
DiskPeripheral,
FloppyDiskPeripheral,
TapePeripheral,
ModemPeripheral,
MonitorPeripheral,
PrinterPeripheral,
PointerPeripheral,
KeyboardPeripheral,
TerminalPeripheral,
LinePeripheral,
NetworkPeripheral,
#ifdef _NT_PROM
Memory,
#endif
OtherPeripheral,
/* new stuff for IP30 */
/* added without moving anything */
/* except ANONYMOUS. */
XTalkAdapter,
PCIAdapter,
GIOAdapter,
TPUAdapter,
Anonymous
} CONFIGTYPE;
typedef enum {
Failed = 1,
ReadOnly = 2,
Removable = 4,
ConsoleIn = 8,
ConsoleOut = 16,
Input = 32,
Output = 64
} IDENTIFIERFLAG;
#ifndef NULL /* for GetChild(NULL); */
#define NULL 0
#endif
union key_u {
struct {
#ifdef _MIPSEB
unsigned char c_bsize; /* block size in lines */
unsigned char c_lsize; /* line size in bytes/tag */
unsigned short c_size; /* cache size in 4K pages */
#else /* _MIPSEL */
unsigned short c_size; /* cache size in 4K pages */
unsigned char c_lsize; /* line size in bytes/tag */
unsigned char c_bsize; /* block size in lines */
#endif /* _MIPSEL */
} cache;
ULONG FullKey;
};
#if _MIPS_SIM == _ABI64
#define SGI_ARCS_VERS 64 /* sgi 64-bit version */
#define SGI_ARCS_REV 0 /* rev .00 */
#else
#define SGI_ARCS_VERS 1 /* first version */
#define SGI_ARCS_REV 10 /* rev .10, 3/04/92 */
#endif
typedef struct component {
CONFIGCLASS Class;
CONFIGTYPE Type;
IDENTIFIERFLAG Flags;
USHORT Version;
USHORT Revision;
ULONG Key;
ULONG AffinityMask;
ULONG ConfigurationDataSize;
ULONG IdentifierLength;
char *Identifier;
} COMPONENT;
/* internal structure that holds pathname parsing data */
struct cfgdata {
char *name; /* full name */
int minlen; /* minimum length to match */
CONFIGTYPE type; /* type of token */
};
/* System ID */
typedef struct systemid {
CHAR VendorId[8];
CHAR ProductId[8];
} SYSTEMID;
/* memory query functions */
typedef enum memorytype {
ExceptionBlock,
SPBPage, /* ARCS == SystemParameterBlock */
#ifndef _NT_PROM
FreeContiguous,
FreeMemory,
BadMemory,
LoadedProgram,
FirmwareTemporary,
FirmwarePermanent
#else /* _NT_PROM */
FreeMemory,
BadMemory,
LoadedProgram,
FirmwareTemporary,
FirmwarePermanent,
FreeContiguous
#endif /* _NT_PROM */
} MEMORYTYPE;
typedef struct memorydescriptor {
MEMORYTYPE Type;
LONG BasePage;
LONG PageCount;
} MEMORYDESCRIPTOR;
#endif /* _ASM_ARC_HINV_H */

87
extra/linux-2.6.10/include/asm-mips/arc/types.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright 1999 Ralf Baechle (ralf@gnu.org)
* Copyright 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_ARC_TYPES_H
#define _ASM_ARC_TYPES_H
#include <linux/config.h>
#ifdef CONFIG_ARC32
typedef char CHAR;
typedef short SHORT;
typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
typedef long LONG __attribute__ ((__mode__ (__SI__)));
typedef unsigned char UCHAR;
typedef unsigned short USHORT;
typedef unsigned long ULONG __attribute__ ((__mode__ (__SI__)));
typedef void VOID;
/* The pointer types. Note that we're using a 64-bit compiler but all
pointer in the ARC structures are only 32-bit, so we need some disgusting
workarounds. Keep your vomit bag handy. */
typedef LONG _PCHAR;
typedef LONG _PSHORT;
typedef LONG _PLARGE_INTEGER;
typedef LONG _PLONG;
typedef LONG _PUCHAR;
typedef LONG _PUSHORT;
typedef LONG _PULONG;
typedef LONG _PVOID;
#endif /* CONFIG_ARC32 */
#ifdef CONFIG_ARC64
typedef char CHAR;
typedef short SHORT;
typedef long LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
typedef long LONG __attribute__ ((__mode__ (__DI__)));
typedef unsigned char UCHAR;
typedef unsigned short USHORT;
typedef unsigned long ULONG __attribute__ ((__mode__ (__DI__)));
typedef void VOID;
/* The pointer types. We're 64-bit and the firmware is also 64-bit, so
live is sane ... */
typedef CHAR *_PCHAR;
typedef SHORT *_PSHORT;
typedef LARGE_INTEGER *_PLARGE_INTEGER;
typedef LONG *_PLONG;
typedef UCHAR *_PUCHAR;
typedef USHORT *_PUSHORT;
typedef ULONG *_PULONG;
typedef VOID *_PVOID;
#endif /* CONFIG_ARC64 */
typedef CHAR *PCHAR;
typedef SHORT *PSHORT;
typedef LARGE_INTEGER *PLARGE_INTEGER;
typedef LONG *PLONG;
typedef UCHAR *PUCHAR;
typedef USHORT *PUSHORT;
typedef ULONG *PULONG;
typedef VOID *PVOID;
/*
* Return type of ArcGetDisplayStatus()
*/
typedef struct {
USHORT CursorXPosition;
USHORT CursorYPosition;
USHORT CursorMaxXPosition;
USHORT CursorMaxYPosition;
USHORT ForegroundColor;
USHORT BackgroundColor;
UCHAR HighIntensity;
UCHAR Underscored;
UCHAR ReverseVideo;
} DISPLAY_STATUS;
#endif /* _ASM_ARC_TYPES_H */

396
extra/linux-2.6.10/include/asm-mips/asm.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
* Copyright (C) 1999 by Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
* Copyright (C) 2002 Maciej W. Rozycki
*
* Some useful macros for MIPS assembler code
*
* Some of the routines below contain useless nops that will be optimized
* away by gas in -O mode. These nops are however required to fill delay
* slots in noreorder mode.
*/
#ifndef __ASM_ASM_H
#define __ASM_ASM_H
#include <linux/config.h>
#include <asm/sgidefs.h>
#ifndef CAT
#ifdef __STDC__
#define __CAT(str1,str2) str1##str2
#else
#define __CAT(str1,str2) str1/**/str2
#endif
#define CAT(str1,str2) __CAT(str1,str2)
#endif
/*
* PIC specific declarations
* Not used for the kernel but here seems to be the right place.
*/
#ifdef __PIC__
#define CPRESTORE(register) \
.cprestore register
#define CPADD(register) \
.cpadd register
#define CPLOAD(register) \
.cpload register
#else
#define CPRESTORE(register)
#define CPADD(register)
#define CPLOAD(register)
#endif
/*
* LEAF - declare leaf routine
*/
#define LEAF(symbol) \
.globl symbol; \
.align 2; \
.type symbol,@function; \
.ent symbol,0; \
symbol: .frame sp,0,ra
/*
* NESTED - declare nested routine entry point
*/
#define NESTED(symbol, framesize, rpc) \
.globl symbol; \
.align 2; \
.type symbol,@function; \
.ent symbol,0; \
symbol: .frame sp, framesize, rpc
/*
* END - mark end of function
*/
#define END(function) \
.end function; \
.size function,.-function
/*
* EXPORT - export definition of symbol
*/
#define EXPORT(symbol) \
.globl symbol; \
symbol:
/*
* FEXPORT - export definition of a function symbol
*/
#define FEXPORT(symbol) \
.globl symbol; \
.type symbol,@function; \
symbol:
/*
* ABS - export absolute symbol
*/
#define ABS(symbol,value) \
.globl symbol; \
symbol = value
#define PANIC(msg) \
.set push; \
.set reorder; \
PTR_LA a0,8f; \
jal panic; \
9: b 9b; \
.set pop; \
TEXT(msg)
/*
* Print formatted string
*/
#define PRINT(string) \
.set push; \
.set reorder; \
PTR_LA a0,8f; \
jal printk; \
.set pop; \
TEXT(string)
#define TEXT(msg) \
.pushsection .data; \
8: .asciiz msg; \
.popsection;
/*
* Build text tables
*/
#define TTABLE(string) \
.pushsection .text; \
.word 1f; \
.popsection \
.pushsection .data; \
1: .asciiz string; \
.popsection
/*
* MIPS IV pref instruction.
* Use with .set noreorder only!
*
* MIPS IV implementations are free to treat this as a nop. The R5000
* is one of them. So we should have an option not to use this instruction.
*/
#ifdef CONFIG_CPU_HAS_PREFETCH
#define PREF(hint,addr) \
.set push; \
.set mips4; \
pref hint,addr; \
.set pop
#define PREFX(hint,addr) \
.set push; \
.set mips4; \
prefx hint,addr; \
.set pop
#else /* !CONFIG_CPU_HAS_PREFETCH */
#define PREF(hint,addr)
#define PREFX(hint,addr)
#endif /* !CONFIG_CPU_HAS_PREFETCH */
/*
* MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
*/
#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
#define MOVN(rd,rs,rt) \
.set push; \
.set reorder; \
beqz rt,9f; \
move rd,rs; \
.set pop; \
9:
#define MOVZ(rd,rs,rt) \
.set push; \
.set reorder; \
bnez rt,9f; \
move rd,rs; \
.set pop; \
9:
#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
#define MOVN(rd,rs,rt) \
.set push; \
.set noreorder; \
bnezl rt,9f; \
move rd,rs; \
.set pop; \
9:
#define MOVZ(rd,rs,rt) \
.set push; \
.set noreorder; \
beqzl rt,9f; \
move rd,rs; \
.set pop; \
9:
#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
(_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
#define MOVN(rd,rs,rt) \
movn rd,rs,rt
#define MOVZ(rd,rs,rt) \
movz rd,rs,rt
#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
/*
* Stack alignment
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define ALSZ 7
#define ALMASK ~7
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define ALSZ 15
#define ALMASK ~15
#endif
/*
* Macros to handle different pointer/register sizes for 32/64-bit code
*/
/*
* Size of a register
*/
#ifdef __mips64
#define SZREG 8
#else
#define SZREG 4
#endif
/*
* Use the following macros in assemblercode to load/store registers,
* pointers etc.
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define REG_S sw
#define REG_L lw
#define REG_SUBU subu
#define REG_ADDU addu
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define REG_S sd
#define REG_L ld
#define REG_SUBU dsubu
#define REG_ADDU daddu
#endif
/*
* How to add/sub/load/store/shift C int variables.
*/
#if (_MIPS_SZINT == 32)
#define INT_ADD add
#define INT_ADDU addu
#define INT_ADDI addi
#define INT_ADDIU addiu
#define INT_SUB sub
#define INT_SUBU subu
#define INT_L lw
#define INT_S sw
#define INT_SLL sll
#define INT_SLLV sllv
#define INT_SRL srl
#define INT_SRLV srlv
#define INT_SRA sra
#define INT_SRAV srav
#endif
#if (_MIPS_SZINT == 64)
#define INT_ADD dadd
#define INT_ADDU daddu
#define INT_ADDI daddi
#define INT_ADDIU daddiu
#define INT_SUB dsub
#define INT_SUBU dsubu
#define INT_L ld
#define INT_S sd
#define INT_SLL dsll
#define INT_SLLV dsllv
#define INT_SRL dsrl
#define INT_SRLV dsrlv
#define INT_SRA dsra
#define INT_SRAV dsrav
#endif
/*
* How to add/sub/load/store/shift C long variables.
*/
#if (_MIPS_SZLONG == 32)
#define LONG_ADD add
#define LONG_ADDU addu
#define LONG_ADDI addi
#define LONG_ADDIU addiu
#define LONG_SUB sub
#define LONG_SUBU subu
#define LONG_L lw
#define LONG_S sw
#define LONG_SLL sll
#define LONG_SLLV sllv
#define LONG_SRL srl
#define LONG_SRLV srlv
#define LONG_SRA sra
#define LONG_SRAV srav
#define LONG .word
#define LONGSIZE 4
#define LONGMASK 3
#define LONGLOG 2
#endif
#if (_MIPS_SZLONG == 64)
#define LONG_ADD dadd
#define LONG_ADDU daddu
#define LONG_ADDI daddi
#define LONG_ADDIU daddiu
#define LONG_SUB dsub
#define LONG_SUBU dsubu
#define LONG_L ld
#define LONG_S sd
#define LONG_SLL dsll
#define LONG_SLLV dsllv
#define LONG_SRL dsrl
#define LONG_SRLV dsrlv
#define LONG_SRA dsra
#define LONG_SRAV dsrav
#define LONG .dword
#define LONGSIZE 8
#define LONGMASK 7
#define LONGLOG 3
#endif
/*
* How to add/sub/load/store/shift pointers.
*/
#if (_MIPS_SZPTR == 32)
#define PTR_ADD add
#define PTR_ADDU addu
#define PTR_ADDI addi
#define PTR_ADDIU addiu
#define PTR_SUB sub
#define PTR_SUBU subu
#define PTR_L lw
#define PTR_S sw
#define PTR_LA la
#define PTR_SLL sll
#define PTR_SLLV sllv
#define PTR_SRL srl
#define PTR_SRLV srlv
#define PTR_SRA sra
#define PTR_SRAV srav
#define PTR_SCALESHIFT 2
#define PTR .word
#define PTRSIZE 4
#define PTRLOG 2
#endif
#if (_MIPS_SZPTR == 64)
#define PTR_ADD dadd
#define PTR_ADDU daddu
#define PTR_ADDI daddi
#define PTR_ADDIU daddiu
#define PTR_SUB dsub
#define PTR_SUBU dsubu
#define PTR_L ld
#define PTR_S sd
#define PTR_LA dla
#define PTR_SLL dsll
#define PTR_SLLV dsllv
#define PTR_SRL dsrl
#define PTR_SRLV dsrlv
#define PTR_SRA dsra
#define PTR_SRAV dsrav
#define PTR_SCALESHIFT 3
#define PTR .dword
#define PTRSIZE 8
#define PTRLOG 3
#endif
/*
* Some cp0 registers were extended to 64bit for MIPS III.
*/
#if (_MIPS_SIM == _MIPS_SIM_ABI32)
#define MFC0 mfc0
#define MTC0 mtc0
#endif
#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
#define MFC0 dmfc0
#define MTC0 dmtc0
#endif
#define SSNOP sll zero,zero,1
#endif /* __ASM_ASM_H */

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/*
* asmmacro.h: Assembler macros to make things easier to read.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1998, 1999, 2003 Ralf Baechle
*/
#ifndef _ASM_ASMMACRO_32_H
#define _ASM_ASMMACRO_32_H
#include <asm/offset.h>
#include <asm/regdef.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
.macro fpu_save_double thread status tmp1=t0 tmp2
cfc1 \tmp1, fcr31
sdc1 $f0, THREAD_FPR0(\thread)
sdc1 $f2, THREAD_FPR2(\thread)
sdc1 $f4, THREAD_FPR4(\thread)
sdc1 $f6, THREAD_FPR6(\thread)
sdc1 $f8, THREAD_FPR8(\thread)
sdc1 $f10, THREAD_FPR10(\thread)
sdc1 $f12, THREAD_FPR12(\thread)
sdc1 $f14, THREAD_FPR14(\thread)
sdc1 $f16, THREAD_FPR16(\thread)
sdc1 $f18, THREAD_FPR18(\thread)
sdc1 $f20, THREAD_FPR20(\thread)
sdc1 $f22, THREAD_FPR22(\thread)
sdc1 $f24, THREAD_FPR24(\thread)
sdc1 $f26, THREAD_FPR26(\thread)
sdc1 $f28, THREAD_FPR28(\thread)
sdc1 $f30, THREAD_FPR30(\thread)
sw \tmp1, THREAD_FCR31(\thread)
.endm
.macro fpu_save_single thread tmp=t0
cfc1 \tmp, fcr31
swc1 $f0, THREAD_FPR0(\thread)
swc1 $f1, THREAD_FPR1(\thread)
swc1 $f2, THREAD_FPR2(\thread)
swc1 $f3, THREAD_FPR3(\thread)
swc1 $f4, THREAD_FPR4(\thread)
swc1 $f5, THREAD_FPR5(\thread)
swc1 $f6, THREAD_FPR6(\thread)
swc1 $f7, THREAD_FPR7(\thread)
swc1 $f8, THREAD_FPR8(\thread)
swc1 $f9, THREAD_FPR9(\thread)
swc1 $f10, THREAD_FPR10(\thread)
swc1 $f11, THREAD_FPR11(\thread)
swc1 $f12, THREAD_FPR12(\thread)
swc1 $f13, THREAD_FPR13(\thread)
swc1 $f14, THREAD_FPR14(\thread)
swc1 $f15, THREAD_FPR15(\thread)
swc1 $f16, THREAD_FPR16(\thread)
swc1 $f17, THREAD_FPR17(\thread)
swc1 $f18, THREAD_FPR18(\thread)
swc1 $f19, THREAD_FPR19(\thread)
swc1 $f20, THREAD_FPR20(\thread)
swc1 $f21, THREAD_FPR21(\thread)
swc1 $f22, THREAD_FPR22(\thread)
swc1 $f23, THREAD_FPR23(\thread)
swc1 $f24, THREAD_FPR24(\thread)
swc1 $f25, THREAD_FPR25(\thread)
swc1 $f26, THREAD_FPR26(\thread)
swc1 $f27, THREAD_FPR27(\thread)
swc1 $f28, THREAD_FPR28(\thread)
swc1 $f29, THREAD_FPR29(\thread)
swc1 $f30, THREAD_FPR30(\thread)
swc1 $f31, THREAD_FPR31(\thread)
sw \tmp, THREAD_FCR31(\thread)
.endm
.macro fpu_restore_double thread tmp=t0
lw \tmp, THREAD_FCR31(\thread)
ldc1 $f0, THREAD_FPR0(\thread)
ldc1 $f2, THREAD_FPR2(\thread)
ldc1 $f4, THREAD_FPR4(\thread)
ldc1 $f6, THREAD_FPR6(\thread)
ldc1 $f8, THREAD_FPR8(\thread)
ldc1 $f10, THREAD_FPR10(\thread)
ldc1 $f12, THREAD_FPR12(\thread)
ldc1 $f14, THREAD_FPR14(\thread)
ldc1 $f16, THREAD_FPR16(\thread)
ldc1 $f18, THREAD_FPR18(\thread)
ldc1 $f20, THREAD_FPR20(\thread)
ldc1 $f22, THREAD_FPR22(\thread)
ldc1 $f24, THREAD_FPR24(\thread)
ldc1 $f26, THREAD_FPR26(\thread)
ldc1 $f28, THREAD_FPR28(\thread)
ldc1 $f30, THREAD_FPR30(\thread)
ctc1 \tmp, fcr31
.endm
.macro fpu_restore_single thread tmp=t0
lw \tmp, THREAD_FCR31(\thread)
lwc1 $f0, THREAD_FPR0(\thread)
lwc1 $f1, THREAD_FPR1(\thread)
lwc1 $f2, THREAD_FPR2(\thread)
lwc1 $f3, THREAD_FPR3(\thread)
lwc1 $f4, THREAD_FPR4(\thread)
lwc1 $f5, THREAD_FPR5(\thread)
lwc1 $f6, THREAD_FPR6(\thread)
lwc1 $f7, THREAD_FPR7(\thread)
lwc1 $f8, THREAD_FPR8(\thread)
lwc1 $f9, THREAD_FPR9(\thread)
lwc1 $f10, THREAD_FPR10(\thread)
lwc1 $f11, THREAD_FPR11(\thread)
lwc1 $f12, THREAD_FPR12(\thread)
lwc1 $f13, THREAD_FPR13(\thread)
lwc1 $f14, THREAD_FPR14(\thread)
lwc1 $f15, THREAD_FPR15(\thread)
lwc1 $f16, THREAD_FPR16(\thread)
lwc1 $f17, THREAD_FPR17(\thread)
lwc1 $f18, THREAD_FPR18(\thread)
lwc1 $f19, THREAD_FPR19(\thread)
lwc1 $f20, THREAD_FPR20(\thread)
lwc1 $f21, THREAD_FPR21(\thread)
lwc1 $f22, THREAD_FPR22(\thread)
lwc1 $f23, THREAD_FPR23(\thread)
lwc1 $f24, THREAD_FPR24(\thread)
lwc1 $f25, THREAD_FPR25(\thread)
lwc1 $f26, THREAD_FPR26(\thread)
lwc1 $f27, THREAD_FPR27(\thread)
lwc1 $f28, THREAD_FPR28(\thread)
lwc1 $f29, THREAD_FPR29(\thread)
lwc1 $f30, THREAD_FPR30(\thread)
lwc1 $f31, THREAD_FPR31(\thread)
ctc1 \tmp, fcr31
.endm
.macro cpu_save_nonscratch thread
LONG_S s0, THREAD_REG16(\thread)
LONG_S s1, THREAD_REG17(\thread)
LONG_S s2, THREAD_REG18(\thread)
LONG_S s3, THREAD_REG19(\thread)
LONG_S s4, THREAD_REG20(\thread)
LONG_S s5, THREAD_REG21(\thread)
LONG_S s6, THREAD_REG22(\thread)
LONG_S s7, THREAD_REG23(\thread)
LONG_S sp, THREAD_REG29(\thread)
LONG_S fp, THREAD_REG30(\thread)
.endm
.macro cpu_restore_nonscratch thread
LONG_L s0, THREAD_REG16(\thread)
LONG_L s1, THREAD_REG17(\thread)
LONG_L s2, THREAD_REG18(\thread)
LONG_L s3, THREAD_REG19(\thread)
LONG_L s4, THREAD_REG20(\thread)
LONG_L s5, THREAD_REG21(\thread)
LONG_L s6, THREAD_REG22(\thread)
LONG_L s7, THREAD_REG23(\thread)
LONG_L sp, THREAD_REG29(\thread)
LONG_L fp, THREAD_REG30(\thread)
LONG_L ra, THREAD_REG31(\thread)
.endm
#endif /* _ASM_ASMMACRO_32_H */

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/*
* asmmacro.h: Assembler macros to make things easier to read.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
* Copyright (C) 1998, 1999 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_ASMMACRO_64_H
#define _ASM_ASMMACRO_64_H
#include <asm/offset.h>
#include <asm/regdef.h>
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
.macro fpu_save_16even thread tmp=t0
cfc1 \tmp, fcr31
sdc1 $f0, THREAD_FPR0(\thread)
sdc1 $f2, THREAD_FPR2(\thread)
sdc1 $f4, THREAD_FPR4(\thread)
sdc1 $f6, THREAD_FPR6(\thread)
sdc1 $f8, THREAD_FPR8(\thread)
sdc1 $f10, THREAD_FPR10(\thread)
sdc1 $f12, THREAD_FPR12(\thread)
sdc1 $f14, THREAD_FPR14(\thread)
sdc1 $f16, THREAD_FPR16(\thread)
sdc1 $f18, THREAD_FPR18(\thread)
sdc1 $f20, THREAD_FPR20(\thread)
sdc1 $f22, THREAD_FPR22(\thread)
sdc1 $f24, THREAD_FPR24(\thread)
sdc1 $f26, THREAD_FPR26(\thread)
sdc1 $f28, THREAD_FPR28(\thread)
sdc1 $f30, THREAD_FPR30(\thread)
sw \tmp, THREAD_FCR31(\thread)
.endm
.macro fpu_save_16odd thread
sdc1 $f1, THREAD_FPR1(\thread)
sdc1 $f3, THREAD_FPR3(\thread)
sdc1 $f5, THREAD_FPR5(\thread)
sdc1 $f7, THREAD_FPR7(\thread)
sdc1 $f9, THREAD_FPR9(\thread)
sdc1 $f11, THREAD_FPR11(\thread)
sdc1 $f13, THREAD_FPR13(\thread)
sdc1 $f15, THREAD_FPR15(\thread)
sdc1 $f17, THREAD_FPR17(\thread)
sdc1 $f19, THREAD_FPR19(\thread)
sdc1 $f21, THREAD_FPR21(\thread)
sdc1 $f23, THREAD_FPR23(\thread)
sdc1 $f25, THREAD_FPR25(\thread)
sdc1 $f27, THREAD_FPR27(\thread)
sdc1 $f29, THREAD_FPR29(\thread)
sdc1 $f31, THREAD_FPR31(\thread)
.endm
.macro fpu_save_double thread status tmp1 tmp2
sll \tmp2, \tmp1, 5
bgez \tmp2, 2f
fpu_save_16odd \thread
2:
fpu_save_16even \thread \tmp1 # clobbers t1
.endm
.macro fpu_restore_16even thread tmp=t0
lw \tmp, THREAD_FCR31(\thread)
ldc1 $f0, THREAD_FPR0(\thread)
ldc1 $f2, THREAD_FPR2(\thread)
ldc1 $f4, THREAD_FPR4(\thread)
ldc1 $f6, THREAD_FPR6(\thread)
ldc1 $f8, THREAD_FPR8(\thread)
ldc1 $f10, THREAD_FPR10(\thread)
ldc1 $f12, THREAD_FPR12(\thread)
ldc1 $f14, THREAD_FPR14(\thread)
ldc1 $f16, THREAD_FPR16(\thread)
ldc1 $f18, THREAD_FPR18(\thread)
ldc1 $f20, THREAD_FPR20(\thread)
ldc1 $f22, THREAD_FPR22(\thread)
ldc1 $f24, THREAD_FPR24(\thread)
ldc1 $f26, THREAD_FPR26(\thread)
ldc1 $f28, THREAD_FPR28(\thread)
ldc1 $f30, THREAD_FPR30(\thread)
ctc1 \tmp, fcr31
.endm
.macro fpu_restore_16odd thread
ldc1 $f1, THREAD_FPR1(\thread)
ldc1 $f3, THREAD_FPR3(\thread)
ldc1 $f5, THREAD_FPR5(\thread)
ldc1 $f7, THREAD_FPR7(\thread)
ldc1 $f9, THREAD_FPR9(\thread)
ldc1 $f11, THREAD_FPR11(\thread)
ldc1 $f13, THREAD_FPR13(\thread)
ldc1 $f15, THREAD_FPR15(\thread)
ldc1 $f17, THREAD_FPR17(\thread)
ldc1 $f19, THREAD_FPR19(\thread)
ldc1 $f21, THREAD_FPR21(\thread)
ldc1 $f23, THREAD_FPR23(\thread)
ldc1 $f25, THREAD_FPR25(\thread)
ldc1 $f27, THREAD_FPR27(\thread)
ldc1 $f29, THREAD_FPR29(\thread)
ldc1 $f31, THREAD_FPR31(\thread)
.endm
.macro fpu_restore_double thread tmp
mfc0 t0, CP0_STATUS
sll t1, t0, 5
bgez t1, 1f # 16 register mode?
fpu_restore_16odd a0
1: fpu_restore_16even a0, t0 # clobbers t0
.endm
.macro cpu_save_nonscratch thread
LONG_S s0, THREAD_REG16(\thread)
LONG_S s1, THREAD_REG17(\thread)
LONG_S s2, THREAD_REG18(\thread)
LONG_S s3, THREAD_REG19(\thread)
LONG_S s4, THREAD_REG20(\thread)
LONG_S s5, THREAD_REG21(\thread)
LONG_S s6, THREAD_REG22(\thread)
LONG_S s7, THREAD_REG23(\thread)
LONG_S sp, THREAD_REG29(\thread)
LONG_S fp, THREAD_REG30(\thread)
.endm
.macro cpu_restore_nonscratch thread
LONG_L s0, THREAD_REG16(\thread)
LONG_L s1, THREAD_REG17(\thread)
LONG_L s2, THREAD_REG18(\thread)
LONG_L s3, THREAD_REG19(\thread)
LONG_L s4, THREAD_REG20(\thread)
LONG_L s5, THREAD_REG21(\thread)
LONG_L s6, THREAD_REG22(\thread)
LONG_L s7, THREAD_REG23(\thread)
LONG_L sp, THREAD_REG29(\thread)
LONG_L fp, THREAD_REG30(\thread)
LONG_L ra, THREAD_REG31(\thread)
.endm
#endif /* _ASM_ASMMACRO_64_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 Ralf Baechle
*/
#ifndef _ASM_ASMMACRO_H
#define _ASM_ASMMACRO_H
#include <linux/config.h>
#include <asm/hazards.h>
#ifdef CONFIG_MIPS32
#include <asm/asmmacro-32.h>
#endif
#ifdef CONFIG_MIPS64
#include <asm/asmmacro-64.h>
#endif
.macro local_irq_enable reg=t0
mfc0 \reg, CP0_STATUS
ori \reg, \reg, 1
mtc0 \reg, CP0_STATUS
irq_enable_hazard
.endm
.macro local_irq_disable reg=t0
mfc0 \reg, CP0_STATUS
ori \reg, \reg, 1
xori \reg, \reg, 1
mtc0 \reg, CP0_STATUS
irq_disable_hazard
.endm
#ifdef CONFIG_CPU_SB1
.macro fpu_enable_hazard
.set push
.set noreorder
.set mips2
SSNOP
bnezl $0, .+4
SSNOP
.set pop
.endm
#else
.macro fpu_enable_hazard
.endm
#endif
#endif /* _ASM_ASMMACRO_H */

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/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*
* But use these as seldom as possible since they are much more slower
* than regular operations.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 97, 99, 2000, 03, 04 by Ralf Baechle
*/
/*
* As workaround for the ATOMIC_DEC_AND_LOCK / atomic_dec_and_lock mess in
* <linux/spinlock.h> we have to include <linux/spinlock.h> outside the
* main big wrapper ...
*/
#include <linux/config.h>
#include <linux/spinlock.h>
#ifndef _ASM_ATOMIC_H
#define _ASM_ATOMIC_H
#include <asm/cpu-features.h>
#include <asm/war.h>
extern spinlock_t atomic_lock;
typedef struct { volatile int counter; } atomic_t;
#define ATOMIC_INIT(i) { (i) }
/*
* atomic_read - read atomic variable
* @v: pointer of type atomic_t
*
* Atomically reads the value of @v.
*/
#define atomic_read(v) ((v)->counter)
/*
* atomic_set - set atomic variable
* @v: pointer of type atomic_t
* @i: required value
*
* Atomically sets the value of @v to @i.
*/
#define atomic_set(v,i) ((v)->counter = (i))
/*
* atomic_add - add integer to atomic variable
* @i: integer value to add
* @v: pointer of type atomic_t
*
* Atomically adds @i to @v.
*/
static __inline__ void atomic_add(int i, atomic_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
"1: ll %0, %1 # atomic_add \n"
" addu %0, %2 \n"
" sc %0, %1 \n"
" beqzl %0, 1b \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
unsigned long temp;
__asm__ __volatile__(
"1: ll %0, %1 # atomic_add \n"
" addu %0, %2 \n"
" sc %0, %1 \n"
" beqz %0, 1b \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else {
unsigned long flags;
spin_lock_irqsave(&atomic_lock, flags);
v->counter += i;
spin_unlock_irqrestore(&atomic_lock, flags);
}
}
/*
* atomic_sub - subtract the atomic variable
* @i: integer value to subtract
* @v: pointer of type atomic_t
*
* Atomically subtracts @i from @v.
*/
static __inline__ void atomic_sub(int i, atomic_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
"1: ll %0, %1 # atomic_sub \n"
" subu %0, %2 \n"
" sc %0, %1 \n"
" beqzl %0, 1b \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
unsigned long temp;
__asm__ __volatile__(
"1: ll %0, %1 # atomic_sub \n"
" subu %0, %2 \n"
" sc %0, %1 \n"
" beqz %0, 1b \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else {
unsigned long flags;
spin_lock_irqsave(&atomic_lock, flags);
v->counter -= i;
spin_unlock_irqrestore(&atomic_lock, flags);
}
}
/*
* Same as above, but return the result value
*/
static __inline__ int atomic_add_return(int i, atomic_t * v)
{
unsigned long result;
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
"1: ll %1, %2 # atomic_add_return \n"
" addu %0, %1, %3 \n"
" sc %0, %2 \n"
" beqzl %0, 1b \n"
" addu %0, %1, %3 \n"
" sync \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
__asm__ __volatile__(
"1: ll %1, %2 # atomic_add_return \n"
" addu %0, %1, %3 \n"
" sc %0, %2 \n"
" beqz %0, 1b \n"
" addu %0, %1, %3 \n"
" sync \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else {
unsigned long flags;
spin_lock_irqsave(&atomic_lock, flags);
result = v->counter;
result += i;
v->counter = result;
spin_unlock_irqrestore(&atomic_lock, flags);
}
return result;
}
static __inline__ int atomic_sub_return(int i, atomic_t * v)
{
unsigned long result;
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
"1: ll %1, %2 # atomic_sub_return \n"
" subu %0, %1, %3 \n"
" sc %0, %2 \n"
" beqzl %0, 1b \n"
" subu %0, %1, %3 \n"
" sync \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
__asm__ __volatile__(
"1: ll %1, %2 # atomic_sub_return \n"
" subu %0, %1, %3 \n"
" sc %0, %2 \n"
" beqz %0, 1b \n"
" subu %0, %1, %3 \n"
" sync \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else {
unsigned long flags;
spin_lock_irqsave(&atomic_lock, flags);
result = v->counter;
result -= i;
v->counter = result;
spin_unlock_irqrestore(&atomic_lock, flags);
}
return result;
}
/*
* atomic_sub_if_positive - add integer to atomic variable
* @v: pointer of type atomic_t
*
* Atomically test @v and decrement if it is greater than 0.
* The function returns the old value of @v minus 1.
*/
static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
{
unsigned long result;
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
"1: ll %1, %2 # atomic_sub_if_positive\n"
" subu %0, %1, %3 \n"
" bltz %0, 1f \n"
" sc %0, %2 \n"
" beqzl %0, 1b \n"
" sync \n"
"1: \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
__asm__ __volatile__(
"1: ll %1, %2 # atomic_sub_if_positive\n"
" subu %0, %1, %3 \n"
" bltz %0, 1f \n"
" sc %0, %2 \n"
" beqz %0, 1b \n"
" sync \n"
"1: \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else {
unsigned long flags;
spin_lock_irqsave(&atomic_lock, flags);
result = v->counter;
result -= i;
if (result >= 0)
v->counter = result;
spin_unlock_irqrestore(&atomic_lock, flags);
}
return result;
}
#define atomic_dec_return(v) atomic_sub_return(1,(v))
#define atomic_inc_return(v) atomic_add_return(1,(v))
/*
* atomic_sub_and_test - subtract value from variable and test result
* @i: integer value to subtract
* @v: pointer of type atomic_t
*
* Atomically subtracts @i from @v and returns
* true if the result is zero, or false for all
* other cases.
*/
#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
/*
* atomic_inc_and_test - increment and test
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1
* and returns true if the result is zero, or false for all
* other cases.
*/
#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
/*
* atomic_dec_and_test - decrement by 1 and test
* @v: pointer of type atomic_t
*
* Atomically decrements @v by 1 and
* returns true if the result is 0, or false for all other
* cases.
*/
#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
/*
* atomic_dec_if_positive - decrement by 1 if old value positive
* @v: pointer of type atomic_t
*/
#define atomic_dec_if_positive(v) atomic_sub_if_positive(1, v)
/*
* atomic_inc - increment atomic variable
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1.
*/
#define atomic_inc(v) atomic_add(1,(v))
/*
* atomic_dec - decrement and test
* @v: pointer of type atomic_t
*
* Atomically decrements @v by 1.
*/
#define atomic_dec(v) atomic_sub(1,(v))
/*
* atomic_add_negative - add and test if negative
* @v: pointer of type atomic_t
* @i: integer value to add
*
* Atomically adds @i to @v and returns true
* if the result is negative, or false when
* result is greater than or equal to zero.
*/
#define atomic_add_negative(i,v) (atomic_add_return(i, (v)) < 0)
#ifdef CONFIG_MIPS64
typedef struct { volatile __s64 counter; } atomic64_t;
#define ATOMIC64_INIT(i) { (i) }
/*
* atomic64_read - read atomic variable
* @v: pointer of type atomic64_t
*
*/
#define atomic64_read(v) ((v)->counter)
/*
* atomic64_set - set atomic variable
* @v: pointer of type atomic64_t
* @i: required value
*/
#define atomic64_set(v,i) ((v)->counter = (i))
/*
* atomic64_add - add integer to atomic variable
* @i: integer value to add
* @v: pointer of type atomic64_t
*
* Atomically adds @i to @v.
*/
static __inline__ void atomic64_add(long i, atomic64_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
"1: lld %0, %1 # atomic64_add \n"
" addu %0, %2 \n"
" scd %0, %1 \n"
" beqzl %0, 1b \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
unsigned long temp;
__asm__ __volatile__(
"1: lld %0, %1 # atomic64_add \n"
" addu %0, %2 \n"
" scd %0, %1 \n"
" beqz %0, 1b \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else {
unsigned long flags;
spin_lock_irqsave(&atomic_lock, flags);
v->counter += i;
spin_unlock_irqrestore(&atomic_lock, flags);
}
}
/*
* atomic64_sub - subtract the atomic variable
* @i: integer value to subtract
* @v: pointer of type atomic64_t
*
* Atomically subtracts @i from @v.
*/
static __inline__ void atomic64_sub(long i, atomic64_t * v)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
"1: lld %0, %1 # atomic64_sub \n"
" subu %0, %2 \n"
" scd %0, %1 \n"
" beqzl %0, 1b \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else if (cpu_has_llsc) {
unsigned long temp;
__asm__ __volatile__(
"1: lld %0, %1 # atomic64_sub \n"
" subu %0, %2 \n"
" scd %0, %1 \n"
" beqz %0, 1b \n"
: "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter));
} else {
unsigned long flags;
spin_lock_irqsave(&atomic_lock, flags);
v->counter -= i;
spin_unlock_irqrestore(&atomic_lock, flags);
}
}
/*
* Same as above, but return the result value
*/
static __inline__ long atomic64_add_return(long i, atomic64_t * v)
{
unsigned long result;
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
"1: lld %1, %2 # atomic64_add_return \n"
" addu %0, %1, %3 \n"
" scd %0, %2 \n"
" beqzl %0, 1b \n"
" addu %0, %1, %3 \n"
" sync \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
__asm__ __volatile__(
"1: lld %1, %2 # atomic64_add_return \n"
" addu %0, %1, %3 \n"
" scd %0, %2 \n"
" beqz %0, 1b \n"
" addu %0, %1, %3 \n"
" sync \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else {
unsigned long flags;
spin_lock_irqsave(&atomic_lock, flags);
result = v->counter;
result += i;
v->counter = result;
spin_unlock_irqrestore(&atomic_lock, flags);
}
return result;
}
static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
{
unsigned long result;
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
"1: lld %1, %2 # atomic64_sub_return \n"
" subu %0, %1, %3 \n"
" scd %0, %2 \n"
" beqzl %0, 1b \n"
" subu %0, %1, %3 \n"
" sync \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
__asm__ __volatile__(
"1: lld %1, %2 # atomic64_sub_return \n"
" subu %0, %1, %3 \n"
" scd %0, %2 \n"
" beqz %0, 1b \n"
" subu %0, %1, %3 \n"
" sync \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else {
unsigned long flags;
spin_lock_irqsave(&atomic_lock, flags);
result = v->counter;
result -= i;
v->counter = result;
spin_unlock_irqrestore(&atomic_lock, flags);
}
return result;
}
/*
* atomic64_sub_if_positive - add integer to atomic variable
* @v: pointer of type atomic64_t
*
* Atomically test @v and decrement if it is greater than 0.
* The function returns the old value of @v minus 1.
*/
static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
{
unsigned long result;
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long temp;
__asm__ __volatile__(
"1: lld %1, %2 # atomic64_sub_if_positive\n"
" dsubu %0, %1, %3 \n"
" bltz %0, 1f \n"
" scd %0, %2 \n"
" beqzl %0, 1b \n"
" sync \n"
"1: \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else if (cpu_has_llsc) {
unsigned long temp;
__asm__ __volatile__(
"1: lld %1, %2 # atomic64_sub_if_positive\n"
" dsubu %0, %1, %3 \n"
" bltz %0, 1f \n"
" scd %0, %2 \n"
" beqz %0, 1b \n"
" sync \n"
"1: \n"
: "=&r" (result), "=&r" (temp), "=m" (v->counter)
: "Ir" (i), "m" (v->counter)
: "memory");
} else {
unsigned long flags;
spin_lock_irqsave(&atomic_lock, flags);
result = v->counter;
result -= i;
if (result >= 0)
v->counter = result;
spin_unlock_irqrestore(&atomic_lock, flags);
}
return result;
}
#define atomic64_dec_return(v) atomic64_sub_return(1,(v))
#define atomic64_inc_return(v) atomic64_add_return(1,(v))
/*
* atomic64_sub_and_test - subtract value from variable and test result
* @i: integer value to subtract
* @v: pointer of type atomic64_t
*
* Atomically subtracts @i from @v and returns
* true if the result is zero, or false for all
* other cases.
*/
#define atomic64_sub_and_test(i,v) (atomic64_sub_return((i), (v)) == 0)
/*
* atomic64_inc_and_test - increment and test
* @v: pointer of type atomic64_t
*
* Atomically increments @v by 1
* and returns true if the result is zero, or false for all
* other cases.
*/
#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
/*
* atomic64_dec_and_test - decrement by 1 and test
* @v: pointer of type atomic64_t
*
* Atomically decrements @v by 1 and
* returns true if the result is 0, or false for all other
* cases.
*/
#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
/*
* atomic64_dec_if_positive - decrement by 1 if old value positive
* @v: pointer of type atomic64_t
*/
#define atomic64_dec_if_positive(v) atomic64_sub_if_positive(1, v)
/*
* atomic64_inc - increment atomic variable
* @v: pointer of type atomic64_t
*
* Atomically increments @v by 1.
*/
#define atomic64_inc(v) atomic64_add(1,(v))
/*
* atomic64_dec - decrement and test
* @v: pointer of type atomic64_t
*
* Atomically decrements @v by 1.
*/
#define atomic64_dec(v) atomic64_sub(1,(v))
/*
* atomic64_add_negative - add and test if negative
* @v: pointer of type atomic64_t
* @i: integer value to add
*
* Atomically adds @i to @v and returns true
* if the result is negative, or false when
* result is greater than or equal to zero.
*/
#define atomic64_add_negative(i,v) (atomic64_add_return(i, (v)) < 0)
#endif /* CONFIG_MIPS64 */
/*
* atomic*_return operations are serializing but not the non-*_return
* versions.
*/
#define smp_mb__before_atomic_dec() smp_mb()
#define smp_mb__after_atomic_dec() smp_mb()
#define smp_mb__before_atomic_inc() smp_mb()
#define smp_mb__after_atomic_inc() smp_mb()
#endif /* _ASM_ATOMIC_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1997, 1999 by Ralf Baechle
* Copyright (c) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_BCACHE_H
#define _ASM_BCACHE_H
#include <linux/config.h>
/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
chipset implemented caches. On machines with other CPUs the CPU does the
cache thing itself. */
struct bcache_ops {
void (*bc_enable)(void);
void (*bc_disable)(void);
void (*bc_wback_inv)(unsigned long page, unsigned long size);
void (*bc_inv)(unsigned long page, unsigned long size);
};
extern void indy_sc_init(void);
extern void sni_pcimt_sc_init(void);
#ifdef CONFIG_BOARD_SCACHE
extern struct bcache_ops *bcops;
static inline void bc_enable(void)
{
bcops->bc_enable();
}
static inline void bc_disable(void)
{
bcops->bc_disable();
}
static inline void bc_wback_inv(unsigned long page, unsigned long size)
{
bcops->bc_wback_inv(page, size);
}
static inline void bc_inv(unsigned long page, unsigned long size)
{
bcops->bc_inv(page, size);
}
#else /* !defined(CONFIG_BOARD_SCACHE) */
/* Not R4000 / R4400 / R4600 / R5000. */
#define bc_enable() do { } while (0)
#define bc_disable() do { } while (0)
#define bc_wback_inv(page, size) do { } while (0)
#define bc_inv(page, size) do { } while (0)
#endif /* !defined(CONFIG_BOARD_SCACHE) */
#endif /* _ASM_BCACHE_H */

850
extra/linux-2.6.10/include/asm-mips/bitops.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1994 - 1997, 1999, 2000 Ralf Baechle (ralf@gnu.org)
* Copyright (c) 1999, 2000 Silicon Graphics, Inc.
*/
#ifndef _ASM_BITOPS_H
#define _ASM_BITOPS_H
#include <linux/config.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <asm/byteorder.h> /* sigh ... */
#include <asm/cpu-features.h>
#if (_MIPS_SZLONG == 32)
#define SZLONG_LOG 5
#define SZLONG_MASK 31UL
#define __LL "ll "
#define __SC "sc "
#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
#elif (_MIPS_SZLONG == 64)
#define SZLONG_LOG 6
#define SZLONG_MASK 63UL
#define __LL "lld "
#define __SC "scd "
#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
#endif
#ifdef __KERNEL__
#include <asm/interrupt.h>
#include <asm/sgidefs.h>
#include <asm/war.h>
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() smp_mb()
#define smp_mb__after_clear_bit() smp_mb()
/*
* Only disable interrupt for kernel mode stuff to keep usermode stuff
* that dares to use kernel include files alive.
*/
#define __bi_flags unsigned long flags
#define __bi_local_irq_save(x) local_irq_save(x)
#define __bi_local_irq_restore(x) local_irq_restore(x)
#else
#define __bi_flags
#define __bi_local_irq_save(x)
#define __bi_local_irq_restore(x)
#endif /* __KERNEL__ */
/*
* set_bit - Atomically set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* This function is atomic and may not be reordered. See __set_bit()
* if you do not require the atomic guarantees.
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
if (cpu_has_llsc && R10000_LLSC_WAR) {
__asm__ __volatile__(
"1: " __LL "%0, %1 # set_bit \n"
" or %0, %2 \n"
" "__SC "%0, %1 \n"
" beqzl %0, 1b \n"
: "=&r" (temp), "=m" (*m)
: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
} else if (cpu_has_llsc) {
__asm__ __volatile__(
"1: " __LL "%0, %1 # set_bit \n"
" or %0, %2 \n"
" "__SC "%0, %1 \n"
" beqz %0, 1b \n"
: "=&r" (temp), "=m" (*m)
: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
__bi_flags;
a += nr >> SZLONG_LOG;
mask = 1 << (nr & SZLONG_MASK);
__bi_local_irq_save(flags);
*a |= mask;
__bi_local_irq_restore(flags);
}
}
/*
* __set_bit - Set a bit in memory
* @nr: the bit to set
* @addr: the address to start counting from
*
* Unlike set_bit(), this function is non-atomic and may be reordered.
* If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds.
*/
static inline void __set_bit(unsigned long nr, volatile unsigned long * addr)
{
unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
*m |= 1UL << (nr & SZLONG_MASK);
}
/*
* clear_bit - Clears a bit in memory
* @nr: Bit to clear
* @addr: Address to start counting from
*
* clear_bit() is atomic and may not be reordered. However, it does
* not contain a memory barrier, so if it is used for locking purposes,
* you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
* in order to ensure changes are visible on other processors.
*/
static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
{
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
if (cpu_has_llsc && R10000_LLSC_WAR) {
__asm__ __volatile__(
"1: " __LL "%0, %1 # clear_bit \n"
" and %0, %2 \n"
" " __SC "%0, %1 \n"
" beqzl %0, 1b \n"
: "=&r" (temp), "=m" (*m)
: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
} else if (cpu_has_llsc) {
__asm__ __volatile__(
"1: " __LL "%0, %1 # clear_bit \n"
" and %0, %2 \n"
" " __SC "%0, %1 \n"
" beqz %0, 1b \n"
: "=&r" (temp), "=m" (*m)
: "ir" (~(1UL << (nr & SZLONG_MASK))), "m" (*m));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
__bi_flags;
a += nr >> SZLONG_LOG;
mask = 1 << (nr & SZLONG_MASK);
__bi_local_irq_save(flags);
*a &= ~mask;
__bi_local_irq_restore(flags);
}
}
/*
* __clear_bit - Clears a bit in memory
* @nr: Bit to clear
* @addr: Address to start counting from
*
* Unlike clear_bit(), this function is non-atomic and may be reordered.
* If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds.
*/
static inline void __clear_bit(unsigned long nr, volatile unsigned long * addr)
{
unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
*m &= ~(1UL << (nr & SZLONG_MASK));
}
/*
* change_bit - Toggle a bit in memory
* @nr: Bit to change
* @addr: Address to start counting from
*
* change_bit() is atomic and may not be reordered.
* Note that @nr may be almost arbitrarily large; this function is not
* restricted to acting on a single-word quantity.
*/
static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
__asm__ __volatile__(
"1: " __LL "%0, %1 # change_bit \n"
" xor %0, %2 \n"
" "__SC "%0, %1 \n"
" beqzl %0, 1b \n"
: "=&r" (temp), "=m" (*m)
: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
} else if (cpu_has_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp;
__asm__ __volatile__(
"1: " __LL "%0, %1 # change_bit \n"
" xor %0, %2 \n"
" "__SC "%0, %1 \n"
" beqz %0, 1b \n"
: "=&r" (temp), "=m" (*m)
: "ir" (1UL << (nr & SZLONG_MASK)), "m" (*m));
} else {
volatile unsigned long *a = addr;
unsigned long mask;
__bi_flags;
a += nr >> SZLONG_LOG;
mask = 1 << (nr & SZLONG_MASK);
__bi_local_irq_save(flags);
*a ^= mask;
__bi_local_irq_restore(flags);
}
}
/*
* __change_bit - Toggle a bit in memory
* @nr: the bit to change
* @addr: the address to start counting from
*
* Unlike change_bit(), this function is non-atomic and may be reordered.
* If it's called on the same region of memory simultaneously, the effect
* may be that only one operation succeeds.
*/
static inline void __change_bit(unsigned long nr, volatile unsigned long * addr)
{
unsigned long * m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
*m ^= 1UL << (nr & SZLONG_MASK);
}
/*
* test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static inline int test_and_set_bit(unsigned long nr,
volatile unsigned long *addr)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp, res;
__asm__ __volatile__(
"1: " __LL "%0, %1 # test_and_set_bit \n"
" or %2, %0, %3 \n"
" " __SC "%2, %1 \n"
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
#ifdef CONFIG_SMP
"sync \n"
#endif
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
: "memory");
return res != 0;
} else if (cpu_has_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp, res;
__asm__ __volatile__(
" .set noreorder # test_and_set_bit \n"
"1: " __LL "%0, %1 \n"
" or %2, %0, %3 \n"
" " __SC "%2, %1 \n"
" beqz %2, 1b \n"
" and %2, %0, %3 \n"
#ifdef CONFIG_SMP
"sync \n"
#endif
".set\treorder"
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
: "memory");
return res != 0;
} else {
volatile unsigned long *a = addr;
unsigned long mask;
int retval;
__bi_flags;
a += nr >> SZLONG_LOG;
mask = 1 << (nr & SZLONG_MASK);
__bi_local_irq_save(flags);
retval = (mask & *a) != 0;
*a |= mask;
__bi_local_irq_restore(flags);
return retval;
}
}
/*
* __test_and_set_bit - Set a bit and return its old value
* @nr: Bit to set
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
static inline int __test_and_set_bit(unsigned long nr,
volatile unsigned long *addr)
{
volatile unsigned long *a = addr;
unsigned long mask;
int retval;
a += nr >> SZLONG_LOG;
mask = 1 << (nr & SZLONG_MASK);
retval = (mask & *a) != 0;
*a |= mask;
return retval;
}
/*
* test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to clear
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static inline int test_and_clear_bit(unsigned long nr,
volatile unsigned long *addr)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp, res;
__asm__ __volatile__(
"1: " __LL "%0, %1 # test_and_clear_bit \n"
" or %2, %0, %3 \n"
" xor %2, %3 \n"
__SC "%2, %1 \n"
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
#ifdef CONFIG_SMP
" sync \n"
#endif
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
: "memory");
return res != 0;
} else if (cpu_has_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp, res;
__asm__ __volatile__(
" .set noreorder # test_and_clear_bit \n"
"1: " __LL "%0, %1 \n"
" or %2, %0, %3 \n"
" xor %2, %3 \n"
__SC "%2, %1 \n"
" beqz %2, 1b \n"
" and %2, %0, %3 \n"
#ifdef CONFIG_SMP
" sync \n"
#endif
" .set reorder \n"
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
: "memory");
return res != 0;
} else {
volatile unsigned long *a = addr;
unsigned long mask;
int retval;
__bi_flags;
a += nr >> SZLONG_LOG;
mask = 1 << (nr & SZLONG_MASK);
__bi_local_irq_save(flags);
retval = (mask & *a) != 0;
*a &= ~mask;
__bi_local_irq_restore(flags);
return retval;
}
}
/*
* __test_and_clear_bit - Clear a bit and return its old value
* @nr: Bit to clear
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
static inline int __test_and_clear_bit(unsigned long nr,
volatile unsigned long * addr)
{
volatile unsigned long *a = addr;
unsigned long mask;
int retval;
a += (nr >> SZLONG_LOG);
mask = 1UL << (nr & SZLONG_MASK);
retval = ((mask & *a) != 0);
*a &= ~mask;
return retval;
}
/*
* test_and_change_bit - Change a bit and return its old value
* @nr: Bit to change
* @addr: Address to count from
*
* This operation is atomic and cannot be reordered.
* It also implies a memory barrier.
*/
static inline int test_and_change_bit(unsigned long nr,
volatile unsigned long *addr)
{
if (cpu_has_llsc && R10000_LLSC_WAR) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp, res;
__asm__ __volatile__(
"1: " __LL " %0, %1 # test_and_change_bit \n"
" xor %2, %0, %3 \n"
" "__SC "%2, %1 \n"
" beqzl %2, 1b \n"
" and %2, %0, %3 \n"
#ifdef CONFIG_SMP
" sync \n"
#endif
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
: "memory");
return res != 0;
} else if (cpu_has_llsc) {
unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
unsigned long temp, res;
__asm__ __volatile__(
" .set noreorder # test_and_change_bit \n"
"1: " __LL " %0, %1 \n"
" xor %2, %0, %3 \n"
" "__SC "\t%2, %1 \n"
" beqz %2, 1b \n"
" and %2, %0, %3 \n"
#ifdef CONFIG_SMP
" sync \n"
#endif
" .set reorder \n"
: "=&r" (temp), "=m" (*m), "=&r" (res)
: "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
: "memory");
return res != 0;
} else {
volatile unsigned long *a = addr;
unsigned long mask, retval;
__bi_flags;
a += nr >> SZLONG_LOG;
mask = 1 << (nr & SZLONG_MASK);
__bi_local_irq_save(flags);
retval = (mask & *a) != 0;
*a ^= mask;
__bi_local_irq_restore(flags);
return retval;
}
}
/*
* __test_and_change_bit - Change a bit and return its old value
* @nr: Bit to change
* @addr: Address to count from
*
* This operation is non-atomic and can be reordered.
* If two examples of this operation race, one can appear to succeed
* but actually fail. You must protect multiple accesses with a lock.
*/
static inline int __test_and_change_bit(unsigned long nr,
volatile unsigned long *addr)
{
volatile unsigned long *a = addr;
unsigned long mask;
int retval;
a += (nr >> SZLONG_LOG);
mask = 1UL << (nr & SZLONG_MASK);
retval = ((mask & *a) != 0);
*a ^= mask;
return retval;
}
#undef __bi_flags
#undef __bi_local_irq_save
#undef __bi_local_irq_restore
/*
* test_bit - Determine whether a bit is set
* @nr: bit number to test
* @addr: Address to start counting from
*/
static inline int test_bit(unsigned long nr, const volatile unsigned long *addr)
{
return 1UL & (addr[nr >> SZLONG_LOG] >> (nr & SZLONG_MASK));
}
/*
* ffz - find first zero in word.
* @word: The word to search
*
* Undefined if no zero exists, so code should check against ~0UL first.
*/
static inline unsigned long ffz(unsigned long word)
{
int b = 0, s;
word = ~word;
#ifdef CONFIG_MIPS32
s = 16; if (word << 16 != 0) s = 0; b += s; word >>= s;
s = 8; if (word << 24 != 0) s = 0; b += s; word >>= s;
s = 4; if (word << 28 != 0) s = 0; b += s; word >>= s;
s = 2; if (word << 30 != 0) s = 0; b += s; word >>= s;
s = 1; if (word << 31 != 0) s = 0; b += s;
#endif
#ifdef CONFIG_MIPS64
s = 32; if (word << 32 != 0) s = 0; b += s; word >>= s;
s = 16; if (word << 48 != 0) s = 0; b += s; word >>= s;
s = 8; if (word << 56 != 0) s = 0; b += s; word >>= s;
s = 4; if (word << 60 != 0) s = 0; b += s; word >>= s;
s = 2; if (word << 62 != 0) s = 0; b += s; word >>= s;
s = 1; if (word << 63 != 0) s = 0; b += s;
#endif
return b;
}
/*
* __ffs - find first bit in word.
* @word: The word to search
*
* Undefined if no bit exists, so code should check against 0 first.
*/
static inline unsigned long __ffs(unsigned long word)
{
return ffz(~word);
}
/*
* fls: find last bit set.
*/
#define fls(x) generic_fls(x)
/*
* find_next_zero_bit - find the first zero bit in a memory region
* @addr: The address to base the search on
* @offset: The bitnumber to start searching at
* @size: The maximum size to search
*/
static inline unsigned long find_next_zero_bit(const unsigned long *addr,
unsigned long size, unsigned long offset)
{
const unsigned long *p = addr + (offset >> SZLONG_LOG);
unsigned long result = offset & ~SZLONG_MASK;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= SZLONG_MASK;
if (offset) {
tmp = *(p++);
tmp |= ~0UL >> (_MIPS_SZLONG-offset);
if (size < _MIPS_SZLONG)
goto found_first;
if (~tmp)
goto found_middle;
size -= _MIPS_SZLONG;
result += _MIPS_SZLONG;
}
while (size & ~SZLONG_MASK) {
if (~(tmp = *(p++)))
goto found_middle;
result += _MIPS_SZLONG;
size -= _MIPS_SZLONG;
}
if (!size)
return result;
tmp = *p;
found_first:
tmp |= ~0UL << size;
if (tmp == ~0UL) /* Are any bits zero? */
return result + size; /* Nope. */
found_middle:
return result + ffz(tmp);
}
#define find_first_zero_bit(addr, size) \
find_next_zero_bit((addr), (size), 0)
/*
* find_next_bit - find the next set bit in a memory region
* @addr: The address to base the search on
* @offset: The bitnumber to start searching at
* @size: The maximum size to search
*/
static inline unsigned long find_next_bit(const unsigned long *addr,
unsigned long size, unsigned long offset)
{
const unsigned long *p = addr + (offset >> SZLONG_LOG);
unsigned long result = offset & ~SZLONG_MASK;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= SZLONG_MASK;
if (offset) {
tmp = *(p++);
tmp &= ~0UL << offset;
if (size < _MIPS_SZLONG)
goto found_first;
if (tmp)
goto found_middle;
size -= _MIPS_SZLONG;
result += _MIPS_SZLONG;
}
while (size & ~SZLONG_MASK) {
if ((tmp = *(p++)))
goto found_middle;
result += _MIPS_SZLONG;
size -= _MIPS_SZLONG;
}
if (!size)
return result;
tmp = *p;
found_first:
tmp &= ~0UL >> (_MIPS_SZLONG - size);
if (tmp == 0UL) /* Are any bits set? */
return result + size; /* Nope. */
found_middle:
return result + __ffs(tmp);
}
/*
* find_first_bit - find the first set bit in a memory region
* @addr: The address to start the search at
* @size: The maximum size to search
*
* Returns the bit-number of the first set bit, not the number of the byte
* containing a bit.
*/
#define find_first_bit(addr, size) \
find_next_bit((addr), (size), 0)
#ifdef __KERNEL__
/*
* Every architecture must define this function. It's the fastest
* way of searching a 140-bit bitmap where the first 100 bits are
* unlikely to be set. It's guaranteed that at least one of the 140
* bits is cleared.
*/
static inline int sched_find_first_bit(const unsigned long *b)
{
#ifdef CONFIG_MIPS32
if (unlikely(b[0]))
return __ffs(b[0]);
if (unlikely(b[1]))
return __ffs(b[1]) + 32;
if (unlikely(b[2]))
return __ffs(b[2]) + 64;
if (b[3])
return __ffs(b[3]) + 96;
return __ffs(b[4]) + 128;
#endif
#ifdef CONFIG_MIPS64
if (unlikely(b[0]))
return __ffs(b[0]);
if (unlikely(b[1]))
return __ffs(b[1]) + 64;
return __ffs(b[2]) + 128;
#endif
}
/*
* ffs - find first bit set
* @x: the word to search
*
* This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
#define ffs(x) generic_ffs(x)
/*
* hweightN - returns the hamming weight of a N-bit word
* @x: the word to weigh
*
* The Hamming Weight of a number is the total number of bits set in it.
*/
#define hweight64(x) generic_hweight64(x)
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
static inline int __test_and_set_le_bit(unsigned long nr, unsigned long *addr)
{
unsigned char *ADDR = (unsigned char *) addr;
int mask, retval;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
retval = (mask & *ADDR) != 0;
*ADDR |= mask;
return retval;
}
static inline int __test_and_clear_le_bit(unsigned long nr, unsigned long *addr)
{
unsigned char *ADDR = (unsigned char *) addr;
int mask, retval;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
retval = (mask & *ADDR) != 0;
*ADDR &= ~mask;
return retval;
}
static inline int test_le_bit(unsigned long nr, const unsigned long * addr)
{
const unsigned char *ADDR = (const unsigned char *) addr;
int mask;
ADDR += nr >> 3;
mask = 1 << (nr & 0x07);
return ((mask & *ADDR) != 0);
}
static inline unsigned long find_next_zero_le_bit(unsigned long *addr,
unsigned long size, unsigned long offset)
{
unsigned long *p = ((unsigned long *) addr) + (offset >> SZLONG_LOG);
unsigned long result = offset & ~SZLONG_MASK;
unsigned long tmp;
if (offset >= size)
return size;
size -= result;
offset &= SZLONG_MASK;
if (offset) {
tmp = cpu_to_lelongp(p++);
tmp |= ~0UL >> (_MIPS_SZLONG-offset); /* bug or feature ? */
if (size < _MIPS_SZLONG)
goto found_first;
if (~tmp)
goto found_middle;
size -= _MIPS_SZLONG;
result += _MIPS_SZLONG;
}
while (size & ~SZLONG_MASK) {
if (~(tmp = cpu_to_lelongp(p++)))
goto found_middle;
result += _MIPS_SZLONG;
size -= _MIPS_SZLONG;
}
if (!size)
return result;
tmp = cpu_to_lelongp(p);
found_first:
tmp |= ~0UL << size;
if (tmp == ~0UL) /* Are any bits zero? */
return result + size; /* Nope. */
found_middle:
return result + ffz(tmp);
}
#define find_first_zero_le_bit(addr, size) \
find_next_zero_le_bit((addr), (size), 0)
#define ext2_set_bit(nr,addr) \
__test_and_set_le_bit((nr),(unsigned long*)addr)
#define ext2_clear_bit(nr, addr) \
__test_and_clear_le_bit((nr),(unsigned long*)addr)
#define ext2_set_bit_atomic(lock, nr, addr) \
({ \
int ret; \
spin_lock(lock); \
ret = ext2_set_bit((nr), (addr)); \
spin_unlock(lock); \
ret; \
})
#define ext2_clear_bit_atomic(lock, nr, addr) \
({ \
int ret; \
spin_lock(lock); \
ret = ext2_clear_bit((nr), (addr)); \
spin_unlock(lock); \
ret; \
})
#define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr)
#define ext2_find_first_zero_bit(addr, size) \
find_first_zero_le_bit((unsigned long*)addr, size)
#define ext2_find_next_zero_bit(addr, size, off) \
find_next_zero_le_bit((unsigned long*)addr, size, off)
/*
* Bitmap functions for the minix filesystem.
*
* FIXME: These assume that Minix uses the native byte/bitorder.
* This limits the Minix filesystem's value for data exchange very much.
*/
#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr)
#define minix_set_bit(nr,addr) set_bit(nr,addr)
#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr)
#define minix_test_bit(nr,addr) test_bit(nr,addr)
#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size)
#endif /* __KERNEL__ */
#endif /* _ASM_BITOPS_H */

255
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 2003 by Ralf Baechle
* Copyright (C) 1995, 1996 Andreas Busse
* Copyright (C) 1995, 1996 Stoned Elipot
* Copyright (C) 1995, 1996 Paul M. Antoine.
*/
#ifndef _ASM_BOOTINFO_H
#define _ASM_BOOTINFO_H
#include <linux/types.h>
#include <asm/setup.h>
/*
* The MACH_GROUP_ IDs are the equivalent to PCI vendor IDs; the remaining
* MACH_ values equivalent to product IDs. As such the numbers do not
* necessarily reflect technical relations or similarities between systems.
*/
/*
* Valid machtype values for group unknown
*/
#define MACH_GROUP_UNKNOWN 0 /* whatever... */
#define MACH_UNKNOWN 0 /* whatever... */
/*
* Valid machtype values for group JAZZ
*/
#define MACH_GROUP_JAZZ 1 /* Jazz */
#define MACH_ACER_PICA_61 0 /* Acer PICA-61 (PICA1) */
#define MACH_MIPS_MAGNUM_4000 1 /* Mips Magnum 4000 "RC4030" */
#define MACH_OLIVETTI_M700 2 /* Olivetti M700-10 (-15 ??) */
/*
* Valid machtype for group DEC
*/
#define MACH_GROUP_DEC 2 /* Digital Equipment */
#define MACH_DSUNKNOWN 0
#define MACH_DS23100 1 /* DECstation 2100 or 3100 */
#define MACH_DS5100 2 /* DECsystem 5100 */
#define MACH_DS5000_200 3 /* DECstation 5000/200 */
#define MACH_DS5000_1XX 4 /* DECstation 5000/120, 125, 133, 150 */
#define MACH_DS5000_XX 5 /* DECstation 5000/20, 25, 33, 50 */
#define MACH_DS5000_2X0 6 /* DECstation 5000/240, 260 */
#define MACH_DS5400 7 /* DECsystem 5400 */
#define MACH_DS5500 8 /* DECsystem 5500 */
#define MACH_DS5800 9 /* DECsystem 5800 */
#define MACH_DS5900 10 /* DECsystem 5900 */
/*
* Valid machtype for group ARC
*/
#define MACH_GROUP_ARC 3 /* Deskstation */
#define MACH_DESKSTATION_RPC44 0 /* Deskstation rPC44 */
#define MACH_DESKSTATION_TYNE 1 /* Deskstation Tyne */
/*
* Valid machtype for group SNI_RM
*/
#define MACH_GROUP_SNI_RM 4 /* Siemens Nixdorf RM series */
#define MACH_SNI_RM200_PCI 0 /* RM200/RM300/RM400 PCI series */
/*
* Valid machtype for group ACN
*/
#define MACH_GROUP_ACN 5
#define MACH_ACN_MIPS_BOARD 0 /* ACN MIPS single board */
/*
* Valid machtype for group SGI
*/
#define MACH_GROUP_SGI 6 /* Silicon Graphics */
#define MACH_SGI_IP22 0 /* Indy, Indigo2, Challenge S */
#define MACH_SGI_IP27 1 /* Origin 200, Origin 2000, Onyx 2 */
#define MACH_SGI_IP28 2 /* Indigo2 Impact */
#define MACH_SGI_IP32 3 /* O2 */
/*
* Valid machtype for group COBALT
*/
#define MACH_GROUP_COBALT 7 /* Cobalt servers */
#define MACH_COBALT_27 0 /* Proto "27" hardware */
/*
* Valid machtype for group NEC DDB
*/
#define MACH_GROUP_NEC_DDB 8 /* NEC DDB */
#define MACH_NEC_DDB5074 0 /* NEC DDB Vrc-5074 */
#define MACH_NEC_DDB5476 1 /* NEC DDB Vrc-5476 */
#define MACH_NEC_DDB5477 2 /* NEC DDB Vrc-5477 */
#define MACH_NEC_ROCKHOPPER 3 /* Rockhopper base board */
#define MACH_NEC_ROCKHOPPERII 4 /* Rockhopper II base board */
/*
* Valid machtype for group BAGET
*/
#define MACH_GROUP_BAGET 9 /* Baget */
#define MACH_BAGET201 0 /* BT23-201 */
#define MACH_BAGET202 1 /* BT23-202 */
/*
* Cosine boards.
*/
#define MACH_GROUP_COSINE 10 /* CoSine Orion */
#define MACH_COSINE_ORION 0
/*
* Valid machtype for group GALILEO
*/
#define MACH_GROUP_GALILEO 11 /* Galileo Eval Boards */
#define MACH_EV96100 0 /* EV96100 */
#define MACH_EV64120A 1 /* EV64120A */
/*
* Valid machtype for group MOMENCO
*/
#define MACH_GROUP_MOMENCO 12 /* Momentum Boards */
#define MACH_MOMENCO_OCELOT 0
#define MACH_MOMENCO_OCELOT_G 1
#define MACH_MOMENCO_OCELOT_C 2
#define MACH_MOMENCO_JAGUAR_ATX 3
#define MACH_MOMENCO_OCELOT_3 4
/*
* Valid machtype for group ITE
*/
#define MACH_GROUP_ITE 13 /* ITE Semi Eval Boards */
#define MACH_QED_4N_S01B 0 /* ITE8172 based eval board */
/*
* Valid machtype for group PHILIPS
*/
#define MACH_GROUP_PHILIPS 14
#define MACH_PHILIPS_NINO 0 /* Nino */
#define MACH_PHILIPS_VELO 1 /* Velo */
/*
* Valid machtype for group Globespan
*/
#define MACH_GROUP_GLOBESPAN 15 /* Globespan */
#define MACH_IVR 0 /* IVR eval board */
/*
* Valid machtype for group SIBYTE
*/
#define MACH_GROUP_SIBYTE 16 /* Sibyte / Broadcom */
#define MACH_SWARM 0
/*
* Valid machtypes for group Toshiba
*/
#define MACH_GROUP_TOSHIBA 17 /* Toshiba Reference Systems TSBREF */
#define MACH_PALLAS 0
#define MACH_TOPAS 1
#define MACH_JMR 2
#define MACH_TOSHIBA_JMR3927 3 /* JMR-TX3927 CPU/IO board */
#define MACH_TOSHIBA_RBTX4927 4
#define MACH_TOSHIBA_RBTX4937 5
#define GROUP_TOSHIBA_NAMES { "Pallas", "TopasCE", "JMR", "JMR TX3927", \
"RBTX4927", "RBTX4937" }
/*
* Valid machtype for group Alchemy
*/
#define MACH_GROUP_ALCHEMY 18 /* AMD Alchemy */
#define MACH_PB1000 0 /* Au1000-based eval board */
#define MACH_PB1100 1 /* Au1100-based eval board */
#define MACH_PB1500 2 /* Au1500-based eval board */
#define MACH_DB1000 3 /* Au1000-based eval board */
#define MACH_DB1100 4 /* Au1100-based eval board */
#define MACH_DB1500 5 /* Au1500-based eval board */
#define MACH_XXS1500 6 /* Au1500-based eval board */
#define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */
#define MACH_PB1550 8 /* Au1550-based eval board */
#define MACH_DB1550 9 /* Au1550-based eval board */
/*
* Valid machtype for group NEC_VR41XX
*
* Various NEC-based devices.
*
* FIXME: MACH_GROUPs should be by _MANUFACTURER_ of * the device, not by
* technical properties, so no new additions to this group.
*/
#define MACH_GROUP_NEC_VR41XX 19
#define MACH_NEC_OSPREY 0 /* Osprey eval board */
#define MACH_NEC_EAGLE 1 /* NEC Eagle/Hawk board */
#define MACH_ZAO_CAPCELLA 2 /* ZAO Networks Capcella */
#define MACH_VICTOR_MPC30X 3 /* Victor MP-C303/304 */
#define MACH_IBM_WORKPAD 4 /* IBM WorkPad z50 */
#define MACH_CASIO_E55 5 /* CASIO CASSIOPEIA E-10/15/55/65 */
#define MACH_TANBAC_TB0226 6 /* TANBAC TB0226 (Mbase) */
#define MACH_TANBAC_TB0229 7 /* TANBAC TB0229 (VR4131DIMM) */
#define MACH_GROUP_HP_LJ 20 /* Hewlett Packard LaserJet */
#define MACH_HP_LASERJET 1
/*
* Valid machtype for group LASAT
*/
#define MACH_GROUP_LASAT 21
#define MACH_LASAT_100 0 /* Masquerade II/SP100/SP50/SP25 */
#define MACH_LASAT_200 1 /* Masquerade PRO/SP200 */
/*
* Valid machtype for group TITAN
*/
#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
#define CL_SIZE COMMAND_LINE_SIZE
const char *get_system_type(void);
extern unsigned long mips_machtype;
extern unsigned long mips_machgroup;
#define BOOT_MEM_MAP_MAX 32
#define BOOT_MEM_RAM 1
#define BOOT_MEM_ROM_DATA 2
#define BOOT_MEM_RESERVED 3
/*
* A memory map that's built upon what was determined
* or specified on the command line.
*/
struct boot_mem_map {
int nr_map;
struct boot_mem_map_entry {
phys_t addr; /* start of memory segment */
phys_t size; /* size of memory segment */
long type; /* type of memory segment */
} map[BOOT_MEM_MAP_MAX];
};
extern struct boot_mem_map boot_mem_map;
extern void add_memory_region(phys_t start, phys_t size, long type);
extern void prom_init(void);
/*
* Initial kernel command line, usually setup by prom_init()
*/
extern char arcs_cmdline[CL_SIZE];
/*
* Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware
*/
extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
#endif /* _ASM_BOOTINFO_H */

38
extra/linux-2.6.10/include/asm-mips/branch.h Normal file
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
*/
#ifndef _ASM_BRANCH_H
#define _ASM_BRANCH_H
#include <asm/ptrace.h>
static inline int delay_slot(struct pt_regs *regs)
{
return regs->cp0_cause & CAUSEF_BD;
}
static inline unsigned long exception_epc(struct pt_regs *regs)
{
if (!delay_slot(regs))
return regs->cp0_epc;
return regs->cp0_epc + 4;
}
extern int __compute_return_epc(struct pt_regs *regs);
static inline int compute_return_epc(struct pt_regs *regs)
{
if (!delay_slot(regs)) {
regs->cp0_epc += 4;
return 0;
}
return __compute_return_epc(regs);
}
#endif /* _ASM_BRANCH_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 2003 by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef __ASM_BREAK_H
#define __ASM_BREAK_H
/*
* The following break codes are or were in use for specific purposes in
* other MIPS operating systems. Linux/MIPS doesn't use all of them. The
* unused ones are here as placeholders; we might encounter them in
* non-Linux/MIPS object files or make use of them in the future.
*/
#define BRK_USERBP 0 /* User bp (used by debuggers) */
#define BRK_KERNELBP 1 /* Break in the kernel */
#define BRK_ABORT 2 /* Sometimes used by abort(3) to SIGIOT */
#define BRK_BD_TAKEN 3 /* For bd slot emulation - not implemented */
#define BRK_BD_NOTTAKEN 4 /* For bd slot emulation - not implemented */
#define BRK_SSTEPBP 5 /* User bp (used by debuggers) */
#define BRK_OVERFLOW 6 /* Overflow check */
#define BRK_DIVZERO 7 /* Divide by zero check */
#define BRK_RANGE 8 /* Range error check */
#define BRK_STACKOVERFLOW 9 /* For Ada stackchecking */
#define BRK_NORLD 10 /* No rld found - not used by Linux/MIPS */
#define _BRK_THREADBP 11 /* For threads, user bp (used by debuggers) */
#define BRK_MULOVF 1023 /* Multiply overflow */
#define BRK_BUG 512 /* Used by BUG() */
#endif /* __ASM_BREAK_H */

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#ifndef __ASM_BUG_H
#define __ASM_BUG_H
#include <asm/break.h>
#define BUG() \
do { \
__asm__ __volatile__("break %0" : : "i" (BRK_BUG)); \
} while (0)
#define HAVE_ARCH_BUG
#include <asm-generic/bug.h>
#endif

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/*
* This is included by init/main.c to check for architecture-dependent bugs.
*
* Needs:
* void check_bugs(void);
*/
#ifndef _ASM_BUGS_H
#define _ASM_BUGS_H
#include <linux/config.h>
extern void check_bugs32(void);
extern void check_bugs64(void);
static inline void check_bugs(void)
{
check_bugs32();
#ifdef CONFIG_MIPS64
check_bugs64();
#endif
}
#endif /* _ASM_BUGS_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 99, 2003 by Ralf Baechle
*/
#ifndef _ASM_BYTEORDER_H
#define _ASM_BYTEORDER_H
#include <asm/types.h>
#ifdef __GNUC__
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
#endif
#endif /* __GNUC__ */
#if defined (__MIPSEB__)
# include <linux/byteorder/big_endian.h>
#elif defined (__MIPSEL__)
# include <linux/byteorder/little_endian.h>
#else
# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
#endif
#endif /* _ASM_BYTEORDER_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_CACHE_H
#define _ASM_CACHE_H
#include <linux/config.h>
#define L1_CACHE_SHIFT CONFIG_MIPS_L1_CACHE_SHIFT
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define L1_CACHE_SHIFT_MAX 6
#define SMP_CACHE_SHIFT L1_CACHE_SHIFT
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#define ARCH_KMALLOC_MINALIGN 8
#endif /* _ASM_CACHE_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 1995, 1996 by Ralf Baechle
*/
#ifndef _ASM_CACHECTL
#define _ASM_CACHECTL
/*
* Options for cacheflush system call
*/
#define ICACHE (1<<0) /* flush instruction cache */
#define DCACHE (1<<1) /* writeback and flush data cache */
#define BCACHE (ICACHE|DCACHE) /* flush both caches */
/*
* Caching modes for the cachectl(2) call
*
* cachectl(2) is currently not supported and returns ENOSYS.
*/
#define CACHEABLE 0 /* make pages cacheable */
#define UNCACHEABLE 1 /* make pages uncacheable */
#endif /* _ASM_CACHECTL */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
* Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
*/
#ifndef _ASM_CACHEFLUSH_H
#define _ASM_CACHEFLUSH_H
/* Keep includes the same across arches. */
#include <linux/mm.h>
#include <asm/cpu-features.h>
/* Cache flushing:
*
* - flush_cache_all() flushes entire cache
* - flush_cache_mm(mm) flushes the specified mm context's cache lines
* - flush_cache_page(mm, vmaddr) flushes a single page
* - flush_cache_range(vma, start, end) flushes a range of pages
* - flush_icache_range(start, end) flush a range of instructions
* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
* - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
*
* MIPS specific flush operations:
*
* - flush_cache_sigtramp() flush signal trampoline
* - flush_icache_all() flush the entire instruction cache
* - flush_data_cache_page() flushes a page from the data cache
*/
extern void (*flush_cache_all)(void);
extern void (*__flush_cache_all)(void);
extern void (*flush_cache_mm)(struct mm_struct *mm);
extern void (*flush_cache_range)(struct vm_area_struct *vma,
unsigned long start, unsigned long end);
extern void (*flush_cache_page)(struct vm_area_struct *vma,
unsigned long page);
extern void __flush_dcache_page(struct page *page);
static inline void flush_dcache_page(struct page *page)
{
if (cpu_has_dc_aliases)
__flush_dcache_page(page);
}
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
extern void (*flush_icache_page)(struct vm_area_struct *vma,
struct page *page);
extern void (*flush_icache_range)(unsigned long start, unsigned long end);
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { \
memcpy(dst, (void *) src, len); \
flush_icache_page(vma, page); \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
extern void (*flush_cache_sigtramp)(unsigned long addr);
extern void (*flush_icache_all)(void);
extern void (*flush_data_cache_page)(unsigned long addr);
/*
* This flag is used to indicate that the page pointed to by a pte
* is dirty and requires cleaning before returning it to the user.
*/
#define PG_dcache_dirty PG_arch_1
#define Page_dcache_dirty(page) \
test_bit(PG_dcache_dirty, &(page)->flags)
#define SetPageDcacheDirty(page) \
set_bit(PG_dcache_dirty, &(page)->flags)
#define ClearPageDcacheDirty(page) \
clear_bit(PG_dcache_dirty, &(page)->flags)
#endif /* _ASM_CACHEFLUSH_H */

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/*
* Cache operations for the cache instruction.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
* (C) Copyright 1999 Silicon Graphics, Inc.
*/
#ifndef __ASM_CACHEOPS_H
#define __ASM_CACHEOPS_H
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
#define Index_Invalidate_I 0x00
#define Index_Writeback_Inv_D 0x01
#define Index_Load_Tag_I 0x04
#define Index_Load_Tag_D 0x05
#define Index_Store_Tag_I 0x08
#define Index_Store_Tag_D 0x09
#define Hit_Invalidate_I 0x10
#define Hit_Invalidate_D 0x11
#define Hit_Writeback_Inv_D 0x15
/*
* R4000-specific cacheops
*/
#define Create_Dirty_Excl_D 0x0d
#define Fill 0x14
#define Hit_Writeback_I 0x18
#define Hit_Writeback_D 0x19
/*
* R4000SC and R4400SC-specific cacheops
*/
#define Index_Invalidate_SI 0x02
#define Index_Writeback_Inv_SD 0x03
#define Index_Load_Tag_SI 0x06
#define Index_Load_Tag_SD 0x07
#define Index_Store_Tag_SI 0x0A
#define Index_Store_Tag_SD 0x0B
#define Create_Dirty_Excl_SD 0x0f
#define Hit_Invalidate_SI 0x12
#define Hit_Invalidate_SD 0x13
#define Hit_Writeback_Inv_SD 0x17
#define Hit_Writeback_SD 0x1b
#define Hit_Set_Virtual_SI 0x1e
#define Hit_Set_Virtual_SD 0x1f
/*
* R5000-specific cacheops
*/
#define R5K_Page_Invalidate_S 0x17
/*
* RM7000-specific cacheops
*/
#define Page_Invalidate_T 0x16
/*
* R1000-specific cacheops
*
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
#define Index_Writeback_Inv_S 0x03
#define Index_Load_Tag_S 0x07
#define Index_Store_Tag_S 0x0B
#define Hit_Invalidate_S 0x13
#define Cache_Barrier 0x14
#define Hit_Writeback_Inv_S 0x17
#define Index_Load_Data_I 0x18
#define Index_Load_Data_D 0x19
#define Index_Load_Data_S 0x1b
#define Index_Store_Data_I 0x1c
#define Index_Store_Data_D 0x1d
#define Index_Store_Data_S 0x1f
#endif /* __ASM_CACHEOPS_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 96, 97, 98, 99, 2001 by Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
* Copyright (C) 2001 Thiemo Seufer.
* Copyright (C) 2002 Maciej W. Rozycki
*/
#ifndef _ASM_CHECKSUM_H
#define _ASM_CHECKSUM_H
#include <linux/config.h>
#include <linux/in6.h>
#include <asm/uaccess.h>
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum);
/*
* this is a new version of the above that records errors it finds in *errp,
* but continues and zeros the rest of the buffer.
*/
unsigned int csum_partial_copy_from_user(const char *src, char *dst, int len,
unsigned int sum, int *errp);
/*
* Copy and checksum to user
*/
#define HAVE_CSUM_COPY_USER
static inline unsigned int csum_and_copy_to_user (const char *src,
char __user *dst,
int len, int sum,
int *err_ptr)
{
might_sleep();
sum = csum_partial(src, len, sum);
if (copy_to_user(dst, src, len)) {
*err_ptr = -EFAULT;
return -1;
}
return sum;
}
/*
* the same as csum_partial, but copies from user space (but on MIPS
* we have just one address space, so this is identical to the above)
*/
unsigned int csum_partial_copy_nocheck(const char *src, char *dst, int len,
unsigned int sum);
/*
* Fold a partial checksum without adding pseudo headers
*/
static inline unsigned short int csum_fold(unsigned int sum)
{
__asm__(
".set\tnoat\t\t\t# csum_fold\n\t"
"sll\t$1,%0,16\n\t"
"addu\t%0,$1\n\t"
"sltu\t$1,%0,$1\n\t"
"srl\t%0,%0,16\n\t"
"addu\t%0,$1\n\t"
"xori\t%0,0xffff\n\t"
".set\tat"
: "=r" (sum)
: "0" (sum));
return sum;
}
/*
* This is a version of ip_compute_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries.
*
* By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by
* Arnt Gulbrandsen.
*/
static inline unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl)
{
unsigned int *word = (unsigned int *) iph;
unsigned int *stop = word + ihl;
unsigned int csum;
int carry;
csum = word[0];
csum += word[1];
carry = (csum < word[1]);
csum += carry;
csum += word[2];
carry = (csum < word[2]);
csum += carry;
csum += word[3];
carry = (csum < word[3]);
csum += carry;
word += 4;
do {
csum += *word;
carry = (csum < *word);
csum += carry;
word++;
} while (word != stop);
return csum_fold(csum);
}
static inline unsigned int csum_tcpudp_nofold(unsigned long saddr,
unsigned long daddr, unsigned short len, unsigned short proto,
unsigned int sum)
{
__asm__(
".set\tnoat\t\t\t# csum_tcpudp_nofold\n\t"
#ifdef CONFIG_MIPS32
"addu\t%0, %2\n\t"
"sltu\t$1, %0, %2\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %3\n\t"
"sltu\t$1, %0, %3\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %4\n\t"
"sltu\t$1, %0, %4\n\t"
"addu\t%0, $1\n\t"
#endif
#ifdef CONFIG_MIPS64
"daddu\t%0, %2\n\t"
"daddu\t%0, %3\n\t"
"daddu\t%0, %4\n\t"
"dsll32\t$1, %0, 0\n\t"
"daddu\t%0, $1\n\t"
"dsrl32\t%0, %0, 0\n\t"
#endif
".set\tat"
: "=r" (sum)
: "0" (daddr), "r"(saddr),
#ifdef __MIPSEL__
"r" (((unsigned long)htons(len)<<16) + proto*256),
#else
"r" (((unsigned long)(proto)<<16) + len),
#endif
"r" (sum));
return sum;
}
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
static inline unsigned short int csum_tcpudp_magic(unsigned long saddr,
unsigned long daddr,
unsigned short len,
unsigned short proto,
unsigned int sum)
{
return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
}
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
{
return csum_fold(csum_partial(buff, len, 0));
}
#define _HAVE_ARCH_IPV6_CSUM
static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr,
struct in6_addr *daddr,
__u32 len,
unsigned short proto,
unsigned int sum)
{
__asm__(
".set\tpush\t\t\t# csum_ipv6_magic\n\t"
".set\tnoreorder\n\t"
".set\tnoat\n\t"
"addu\t%0, %5\t\t\t# proto (long in network byte order)\n\t"
"sltu\t$1, %0, %5\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %6\t\t\t# csum\n\t"
"sltu\t$1, %0, %6\n\t"
"lw\t%1, 0(%2)\t\t\t# four words source address\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %1\n\t"
"sltu\t$1, %0, %1\n\t"
"lw\t%1, 4(%2)\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %1\n\t"
"sltu\t$1, %0, %1\n\t"
"lw\t%1, 8(%2)\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %1\n\t"
"sltu\t$1, %0, %1\n\t"
"lw\t%1, 12(%2)\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %1\n\t"
"sltu\t$1, %0, %1\n\t"
"lw\t%1, 0(%3)\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %1\n\t"
"sltu\t$1, %0, %1\n\t"
"lw\t%1, 4(%3)\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %1\n\t"
"sltu\t$1, %0, %1\n\t"
"lw\t%1, 8(%3)\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %1\n\t"
"sltu\t$1, %0, %1\n\t"
"lw\t%1, 12(%3)\n\t"
"addu\t%0, $1\n\t"
"addu\t%0, %1\n\t"
"sltu\t$1, %0, %1\n\t"
"addu\t%0, $1\t\t\t# Add final carry\n\t"
".set\tpop"
: "=r" (sum), "=r" (proto)
: "r" (saddr), "r" (daddr),
"0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
return csum_fold(sum);
}
#endif /* _ASM_CHECKSUM_H */

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/*
* Lowlevel hardware stuff for the MIPS based Cobalt microservers.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1997 Cobalt Microserver
* Copyright (C) 1997, 2003 Ralf Baechle
* Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
*/
#ifndef __ASM_COBALT_H
#define __ASM_COBALT_H
/*
* i8259 legacy interrupts used on Cobalt:
*
* 8 - RTC
* 9 - PCI
* 14 - IDE0
* 15 - IDE1
*
* CPU IRQs are 16 ... 23
*/
#define COBALT_TIMER_IRQ 18
#define COBALT_SCC_IRQ 19 /* pre-production has 85C30 */
#define COBALT_RAQ_SCSI_IRQ 19
#define COBALT_ETH0_IRQ 19
#define COBALT_ETH1_IRQ 20
#define COBALT_SERIAL_IRQ 21
#define COBALT_SCSI_IRQ 21
#define COBALT_VIA_IRQ 22 /* Chained to VIA ISA bridge */
#define COBALT_QUBE_SLOT_IRQ 23
/*
* PCI configuration space manifest constants. These are wired into
* the board layout according to the PCI spec to enable the software
* to probe the hardware configuration space in a well defined manner.
*
* The PCI_DEVSHFT() macro transforms these values into numbers
* suitable for passing as the dev parameter to the various
* pcibios_read/write_config routines.
*/
#define COBALT_PCICONF_CPU 0x06
#define COBALT_PCICONF_ETH0 0x07
#define COBALT_PCICONF_RAQSCSI 0x08
#define COBALT_PCICONF_VIA 0x09
#define COBALT_PCICONF_PCISLOT 0x0A
#define COBALT_PCICONF_ETH1 0x0C
/*
* The Cobalt board id information. The boards have an ID number wired
* into the VIA that is available in the high nibble of register 94.
* This register is available in the VIA configuration space through the
* interface routines qube_pcibios_read/write_config. See cobalt/pci.c
*/
#define VIA_COBALT_BRD_ID_REG 0x94
#define VIA_COBALT_BRD_REG_to_ID(reg) ((unsigned char) (reg) >> 4)
#define COBALT_BRD_ID_QUBE1 0x3
#define COBALT_BRD_ID_RAQ1 0x4
#define COBALT_BRD_ID_QUBE2 0x5
#define COBALT_BRD_ID_RAQ2 0x6
/*
* Galileo chipset access macros for the Cobalt. The base address for
* the GT64111 chip is 0x14000000
*
* Most of this really should go into a separate GT64111 header file.
*/
#define GT64111_IO_BASE 0x10000000UL
#define GT64111_BASE 0x14000000UL
#define GALILEO_REG(ofs) (KSEG0 + GT64111_BASE + (unsigned long)(ofs))
#define GALILEO_INL(port) (*(volatile unsigned int *) GALILEO_REG(port))
#define GALILEO_OUTL(val, port) \
do { \
*(volatile unsigned int *) GALILEO_REG(port) = (port); \
} while (0)
#define GALILEO_T0EXP 0x0100
#define GALILEO_ENTC0 0x01
#define GALILEO_SELTC0 0x02
#define PCI_CFG_SET(devfn,where) \
GALILEO_OUTL((0x80000000 | (PCI_SLOT (devfn) << 11) | \
(PCI_FUNC (devfn) << 8) | (where)), GT_PCI0_CFGADDR_OFS)
#endif /* __ASM_COBALT_H */

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#ifndef _ASM_COMPAT_H
#define _ASM_COMPAT_H
/*
* Architecture specific compatibility types
*/
#include <linux/types.h>
#include <asm/page.h>
#define COMPAT_USER_HZ 100
typedef u32 compat_size_t;
typedef s32 compat_ssize_t;
typedef s32 compat_time_t;
typedef s32 compat_clock_t;
typedef s32 compat_suseconds_t;
typedef s32 compat_pid_t;
typedef s32 compat_uid_t;
typedef s32 compat_gid_t;
typedef u32 compat_mode_t;
typedef u32 compat_ino_t;
typedef u32 compat_dev_t;
typedef s32 compat_off_t;
typedef s64 compat_loff_t;
typedef u32 compat_nlink_t;
typedef s32 compat_ipc_pid_t;
typedef s32 compat_daddr_t;
typedef s32 compat_caddr_t;
typedef struct {
s32 val[2];
} compat_fsid_t;
typedef s32 compat_int_t;
typedef s32 compat_long_t;
typedef u32 compat_uint_t;
typedef u32 compat_ulong_t;
struct compat_timespec {
compat_time_t tv_sec;
s32 tv_nsec;
};
struct compat_timeval {
compat_time_t tv_sec;
s32 tv_usec;
};
struct compat_stat {
compat_dev_t st_dev;
s32 st_pad1[3];
compat_ino_t st_ino;
compat_mode_t st_mode;
compat_nlink_t st_nlink;
compat_uid_t st_uid;
compat_gid_t st_gid;
compat_dev_t st_rdev;
s32 st_pad2[2];
compat_off_t st_size;
s32 st_pad3;
compat_time_t st_atime;
s32 st_atime_nsec;
compat_time_t st_mtime;
s32 st_mtime_nsec;
compat_time_t st_ctime;
s32 st_ctime_nsec;
s32 st_blksize;
s32 st_blocks;
s32 st_pad4[14];
};
struct compat_flock {
short l_type;
short l_whence;
compat_off_t l_start;
compat_off_t l_len;
s32 l_sysid;
compat_pid_t l_pid;
short __unused;
s32 pad[4];
};
#define F_GETLK64 33
#define F_SETLK64 34
#define F_SETLKW64 35
struct compat_flock64 {
short l_type;
short l_whence;
compat_loff_t l_start;
compat_loff_t l_len;
compat_pid_t l_pid;
};
struct compat_statfs {
int f_type;
int f_bsize;
int f_frsize;
int f_blocks;
int f_bfree;
int f_files;
int f_ffree;
int f_bavail;
compat_fsid_t f_fsid;
int f_namelen;
int f_spare[6];
};
#define COMPAT_RLIM_INFINITY 0x7fffffffUL
typedef u32 compat_old_sigset_t; /* at least 32 bits */
#define _COMPAT_NSIG 128 /* Don't ask !$@#% ... */
#define _COMPAT_NSIG_BPW 32
typedef u32 compat_sigset_word;
#define COMPAT_OFF_T_MAX 0x7fffffff
#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
/*
* A pointer passed in from user mode. This should not
* be used for syscall parameters, just declare them
* as pointers because the syscall entry code will have
* appropriately comverted them already.
*/
typedef u32 compat_uptr_t;
static inline void *compat_ptr(compat_uptr_t uptr)
{
return (void *)(long)uptr;
}
static inline void *compat_alloc_user_space(long len)
{
struct pt_regs *regs = (struct pt_regs *)
((unsigned long) current_thread_info() + THREAD_SIZE - 32) - 1;
return (void *) (regs->regs[29] - len);
}
#endif /* _ASM_COMPAT_H */

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/*
* Copyright (C) 2004 Maciej W. Rozycki
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef _ASM_COMPILER_H
#define _ASM_COMPILER_H
#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
#define GCC_REG_ACCUM "$0"
#else
#define GCC_REG_ACCUM "accum"
#endif
#endif /* _ASM_COMPILER_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 Ralf Baechle
*/
#ifndef __ASM_CPU_FEATURES_H
#define __ASM_CPU_FEATURES_H
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <cpu-feature-overrides.h>
/*
* SMP assumption: Options of CPU 0 are a superset of all processors.
* This is true for all known MIPS systems.
*/
#ifndef cpu_has_tlb
#define cpu_has_tlb (cpu_data[0].options & MIPS_CPU_TLB)
#endif
#ifndef cpu_has_4kex
#define cpu_has_4kex (cpu_data[0].options & MIPS_CPU_4KEX)
#endif
#ifndef cpu_has_4ktlb
#define cpu_has_4ktlb (cpu_data[0].options & MIPS_CPU_4KTLB)
#endif
#ifndef cpu_has_fpu
#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
#endif
#ifndef cpu_has_32fpr
#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
#endif
#ifndef cpu_has_counter
#define cpu_has_counter (cpu_data[0].options & MIPS_CPU_COUNTER)
#endif
#ifndef cpu_has_watch
#define cpu_has_watch (cpu_data[0].options & MIPS_CPU_WATCH)
#endif
#ifndef cpu_has_mips16
#define cpu_has_mips16 (cpu_data[0].options & MIPS_CPU_MIPS16)
#endif
#ifndef cpu_has_divec
#define cpu_has_divec (cpu_data[0].options & MIPS_CPU_DIVEC)
#endif
#ifndef cpu_has_vce
#define cpu_has_vce (cpu_data[0].options & MIPS_CPU_VCE)
#endif
#ifndef cpu_has_cache_cdex_p
#define cpu_has_cache_cdex_p (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
#endif
#ifndef cpu_has_cache_cdex_s
#define cpu_has_cache_cdex_s (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
#endif
#ifndef cpu_has_prefetch
#define cpu_has_prefetch (cpu_data[0].options & MIPS_CPU_PREFETCH)
#endif
#ifndef cpu_has_mcheck
#define cpu_has_mcheck (cpu_data[0].options & MIPS_CPU_MCHECK)
#endif
#ifndef cpu_has_ejtag
#define cpu_has_ejtag (cpu_data[0].options & MIPS_CPU_EJTAG)
#endif
#ifndef cpu_has_llsc
#define cpu_has_llsc (cpu_data[0].options & MIPS_CPU_LLSC)
#endif
#ifndef cpu_has_vtag_icache
#define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
#endif
#ifndef cpu_has_dc_aliases
#define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
#endif
#ifndef cpu_has_ic_fills_f_dc
#define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
#endif
/*
* Certain CPUs may throw bizarre exceptions if not the whole cacheline
* contains valid instructions. For these we ensure proper alignment of
* signal trampolines and pad them to the size of a full cache lines with
* nops. This is also used in structure definitions so can't be a test macro
* like the others.
*/
#ifndef PLAT_TRAMPOLINE_STUFF_LINE
#define PLAT_TRAMPOLINE_STUFF_LINE 0UL
#endif
#ifdef CONFIG_MIPS32
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex (cpu_data[0].options & MIPS_CPU_NOFPUEX)
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs 0
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses 0
# endif
#endif
#ifdef CONFIG_MIPS64
# ifndef cpu_has_nofpuex
# define cpu_has_nofpuex 0
# endif
# ifndef cpu_has_64bits
# define cpu_has_64bits 1
# endif
# ifndef cpu_has_64bit_zero_reg
# define cpu_has_64bit_zero_reg 1
# endif
# ifndef cpu_has_64bit_gp_regs
# define cpu_has_64bit_gp_regs 1
# endif
# ifndef cpu_has_64bit_addresses
# define cpu_has_64bit_addresses 1
# endif
#endif
#ifndef cpu_has_subset_pcaches
#define cpu_has_subset_pcaches (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
#endif
#ifndef cpu_dcache_line_size
#define cpu_dcache_line_size() current_cpu_data.dcache.linesz
#endif
#ifndef cpu_icache_line_size
#define cpu_icache_line_size() current_cpu_data.icache.linesz
#endif
#ifndef cpu_scache_line_size
#define cpu_scache_line_size() current_cpu_data.scache.linesz
#endif
#endif /* __ASM_CPU_FEATURES_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 Waldorf GMBH
* Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
* Copyright (C) 1996 Paul M. Antoine
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
#ifndef __ASM_CPU_INFO_H
#define __ASM_CPU_INFO_H
#include <linux/config.h>
#include <asm/cache.h>
#ifdef CONFIG_SGI_IP27
#include <asm/sn/types.h>
#endif
/*
* Descriptor for a cache
*/
struct cache_desc {
unsigned short linesz; /* Size of line in bytes */
unsigned short ways; /* Number of ways */
unsigned short sets; /* Number of lines per set */
unsigned int waysize; /* Bytes per way */
unsigned int waybit; /* Bits to select in a cache set */
unsigned int flags; /* Flags describing cache properties */
};
/*
* Flag definitions
*/
#define MIPS_CACHE_NOT_PRESENT 0x00000001
#define MIPS_CACHE_VTAG 0x00000002 /* Virtually tagged cache */
#define MIPS_CACHE_ALIASES 0x00000004 /* Cache could have aliases */
#define MIPS_CACHE_IC_F_DC 0x00000008 /* Ic can refill from D-cache */
struct cpuinfo_mips {
unsigned long udelay_val;
unsigned long asid_cache;
#if defined(CONFIG_SGI_IP27)
// cpuid_t p_cpuid; /* PROM assigned cpuid */
cnodeid_t p_nodeid; /* my node ID in compact-id-space */
nasid_t p_nasid; /* my node ID in numa-as-id-space */
unsigned char p_slice; /* Physical position on node board */
#endif
#if 0
unsigned long loops_per_sec;
unsigned long ipi_count;
unsigned long irq_attempt[NR_IRQS];
unsigned long smp_local_irq_count;
unsigned long prof_multiplier;
unsigned long prof_counter;
#endif
/*
* Capability and feature descriptor structure for MIPS CPU
*/
unsigned long options;
unsigned int processor_id;
unsigned int fpu_id;
unsigned int cputype;
int isa_level;
int tlbsize;
struct cache_desc icache; /* Primary I-cache */
struct cache_desc dcache; /* Primary D or combined I/D cache */
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
void *data; /* Additional data */
} __attribute__((aligned(SMP_CACHE_BYTES)));
extern struct cpuinfo_mips cpu_data[];
#define current_cpu_data cpu_data[smp_processor_id()]
extern void cpu_probe(void);
extern void cpu_report(void);
#endif /* __ASM_CPU_INFO_H */

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/*
* cpu.h: Values of the PRId register used to match up
* various MIPS cpu types.
*
* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
*/
#ifndef _ASM_CPU_H
#define _ASM_CPU_H
/* Assigned Company values for bits 23:16 of the PRId Register
(CP0 register 15, select 0). As of the MIPS32 and MIPS64 specs from
MTI, the PRId register is defined in this (backwards compatible)
way:
+----------------+----------------+----------------+----------------+
| Company Options| Company ID | Processor ID | Revision |
+----------------+----------------+----------------+----------------+
31 24 23 16 15 8 7
I don't have docs for all the previous processors, but my impression is
that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
spec.
*/
#define PRID_COMP_LEGACY 0x000000
#define PRID_COMP_MIPS 0x010000
#define PRID_COMP_BROADCOM 0x020000
#define PRID_COMP_ALCHEMY 0x030000
#define PRID_COMP_SIBYTE 0x040000
#define PRID_COMP_SANDCRAFT 0x050000
/*
* Assigned values for the product ID register. In order to detect a
* certain CPU type exactly eventually additional registers may need to
* be examined. These are valid when 23:16 == PRID_COMP_LEGACY
*/
#define PRID_IMP_R2000 0x0100
#define PRID_IMP_AU1_REV1 0x0100
#define PRID_IMP_AU1_REV2 0x0200
#define PRID_IMP_R3000 0x0200 /* Same as R2000A */
#define PRID_IMP_R6000 0x0300 /* Same as R3000A */
#define PRID_IMP_R4000 0x0400
#define PRID_IMP_R6000A 0x0600
#define PRID_IMP_R10000 0x0900
#define PRID_IMP_R4300 0x0b00
#define PRID_IMP_VR41XX 0x0c00
#define PRID_IMP_R12000 0x0e00
#define PRID_IMP_R8000 0x1000
#define PRID_IMP_R4600 0x2000
#define PRID_IMP_R4700 0x2100
#define PRID_IMP_TX39 0x2200
#define PRID_IMP_R4640 0x2200
#define PRID_IMP_R4650 0x2200 /* Same as R4640 */
#define PRID_IMP_R5000 0x2300
#define PRID_IMP_TX49 0x2d00
#define PRID_IMP_SONIC 0x2400
#define PRID_IMP_MAGIC 0x2500
#define PRID_IMP_RM7000 0x2700
#define PRID_IMP_NEVADA 0x2800 /* RM5260 ??? */
#define PRID_IMP_RM9000 0x3400
#define PRID_IMP_R5432 0x5400
#define PRID_IMP_R5500 0x5500
#define PRID_IMP_4KC 0x8000
#define PRID_IMP_5KC 0x8100
#define PRID_IMP_20KC 0x8200
#define PRID_IMP_4KEC 0x8400
#define PRID_IMP_4KSC 0x8600
#define PRID_IMP_25KF 0x8800
#define PRID_IMP_5KE 0x8900
#define PRID_IMP_4KECR2 0x9000
#define PRID_IMP_4KEMPR2 0x9100
#define PRID_IMP_4KSD 0x9200
#define PRID_IMP_24K 0x9300
#define PRID_IMP_UNKNOWN 0xff00
/*
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
*/
#define PRID_IMP_SB1 0x0100
/*
* These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
*/
#define PRID_IMP_SR71000 0x0400
/*
* Definitions for 7:0 on legacy processors
*/
#define PRID_REV_TX4927 0x0022
#define PRID_REV_TX4937 0x0030
#define PRID_REV_R4400 0x0040
#define PRID_REV_R3000A 0x0030
#define PRID_REV_R3000 0x0020
#define PRID_REV_R2000A 0x0010
#define PRID_REV_TX3912 0x0010
#define PRID_REV_TX3922 0x0030
#define PRID_REV_TX3927 0x0040
#define PRID_REV_VR4111 0x0050
#define PRID_REV_VR4181 0x0050 /* Same as VR4111 */
#define PRID_REV_VR4121 0x0060
#define PRID_REV_VR4122 0x0070
#define PRID_REV_VR4181A 0x0070 /* Same as VR4122 */
#define PRID_REV_VR4130 0x0080
/*
* FPU implementation/revision register (CP1 control register 0).
*
* +---------------------------------+----------------+----------------+
* | 0 | Implementation | Revision |
* +---------------------------------+----------------+----------------+
* 31 16 15 8 7 0
*/
#define FPIR_IMP_NONE 0x0000
#define CPU_UNKNOWN 0
#define CPU_R2000 1
#define CPU_R3000 2
#define CPU_R3000A 3
#define CPU_R3041 4
#define CPU_R3051 5
#define CPU_R3052 6
#define CPU_R3081 7
#define CPU_R3081E 8
#define CPU_R4000PC 9
#define CPU_R4000SC 10
#define CPU_R4000MC 11
#define CPU_R4200 12
#define CPU_R4400PC 13
#define CPU_R4400SC 14
#define CPU_R4400MC 15
#define CPU_R4600 16
#define CPU_R6000 17
#define CPU_R6000A 18
#define CPU_R8000 19
#define CPU_R10000 20
#define CPU_R12000 21
#define CPU_R4300 22
#define CPU_R4650 23
#define CPU_R4700 24
#define CPU_R5000 25
#define CPU_R5000A 26
#define CPU_R4640 27
#define CPU_NEVADA 28
#define CPU_RM7000 29
#define CPU_R5432 30
#define CPU_4KC 31
#define CPU_5KC 32
#define CPU_R4310 33
#define CPU_SB1 34
#define CPU_TX3912 35
#define CPU_TX3922 36
#define CPU_TX3927 37
#define CPU_AU1000 38
#define CPU_4KEC 39
#define CPU_4KSC 40
#define CPU_VR41XX 41
#define CPU_R5500 42
#define CPU_TX49XX 43
#define CPU_AU1500 44
#define CPU_20KC 45
#define CPU_VR4111 46
#define CPU_VR4121 47
#define CPU_VR4122 48
#define CPU_VR4131 49
#define CPU_VR4181 50
#define CPU_VR4181A 51
#define CPU_AU1100 52
#define CPU_SR71000 53
#define CPU_RM9000 54
#define CPU_25KF 55
#define CPU_VR4133 56
#define CPU_AU1550 57
#define CPU_24K 58
#define CPU_LAST 58
/*
* ISA Level encodings
*
*/
#define MIPS_CPU_ISA_I 0x00000001
#define MIPS_CPU_ISA_II 0x00000002
#define MIPS_CPU_ISA_III 0x00008003
#define MIPS_CPU_ISA_IV 0x00008004
#define MIPS_CPU_ISA_V 0x00008005
#define MIPS_CPU_ISA_M32 0x00000020
#define MIPS_CPU_ISA_M64 0x00008040
/*
* Bit 15 encodes if an ISA level supports 64-bit operations.
*/
#define MIPS_CPU_ISA_64BIT 0x00008000
/*
* CPU Option encodings
*/
#define MIPS_CPU_TLB 0x00000001 /* CPU has TLB */
/* Leave a spare bit for variant MMU types... */
#define MIPS_CPU_4KEX 0x00000004 /* "R4K" exception model */
#define MIPS_CPU_4KTLB 0x00000008 /* "R4K" TLB handler */
#define MIPS_CPU_FPU 0x00000010 /* CPU has FPU */
#define MIPS_CPU_32FPR 0x00000020 /* 32 dbl. prec. FP registers */
#define MIPS_CPU_COUNTER 0x00000040 /* Cycle count/compare */
#define MIPS_CPU_WATCH 0x00000080 /* watchpoint registers */
#define MIPS_CPU_MIPS16 0x00000100 /* code compression */
#define MIPS_CPU_DIVEC 0x00000200 /* dedicated interrupt vector */
#define MIPS_CPU_VCE 0x00000400 /* virt. coherence conflict possible */
#define MIPS_CPU_CACHE_CDEX_P 0x00000800 /* Create_Dirty_Exclusive CACHE op */
#define MIPS_CPU_CACHE_CDEX_S 0x00001000 /* ... same for seconary cache ... */
#define MIPS_CPU_MCHECK 0x00002000 /* Machine check exception */
#define MIPS_CPU_EJTAG 0x00004000 /* EJTAG exception */
#define MIPS_CPU_NOFPUEX 0x00008000 /* no FPU exception */
#define MIPS_CPU_LLSC 0x00010000 /* CPU has ll/sc instructions */
#define MIPS_CPU_SUBSET_CACHES 0x00020000 /* P-cache subset enforced */
#define MIPS_CPU_PREFETCH 0x00040000 /* CPU has usable prefetch */
#endif /* _ASM_CPU_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998, 2002 Ralf Baechle
* Copyright (C) 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_CURRENT_H
#define _ASM_CURRENT_H
#include <linux/thread_info.h>
struct task_struct;
static inline struct task_struct * get_current(void)
{
return current_thread_info()->task;
}
#define current get_current()
#endif /* _ASM_CURRENT_H */

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/*
* include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
extern void ddb5074_led_hex(int hex);
extern void ddb5074_led_d2(int on);
extern void ddb5074_led_d3(int on);

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/*
* include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#ifndef _ASM_DDB5XXX_DDB5074_H
#define _ASM_DDB5XXX_DDB5074_H
#include <asm/nile4.h>
#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
#define DDB_PCI_IO_BASE 0x06000000
#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define DDB_PCI_MEM_BASE 0x08000000
#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
#define NILE4_PCI_IO_BASE 0xa6000000
#define NILE4_PCI_MEM_BASE 0xa8000000
#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE
#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS
#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE)
#define CPU_NILE4_CASCADE 2
extern void ddb5074_led_hex(int hex);
extern void ddb5074_led_d2(int on);
extern void ddb5074_led_d3(int on);
extern void nile4_irq_setup(u32 base);
#endif

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/*
* header file specific for ddb5476
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
#define DDB_SDRAM_BASE 0x00000000
#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
#define DDB_DCS3_BASE 0x04000000 /* flash 1 */
#define DDB_DCS3_SIZE 0x01000000 /* 16MB */
#define DDB_DCS2_BASE 0x05000000 /* flash 2 */
#define DDB_DCS2_SIZE 0x01000000 /* 16MB */
#define DDB_PCI_IO_BASE 0x06000000
#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define DDB_PCI_MEM_BASE 0x08000000
#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */
#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */
#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */
#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */
#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */
#define DDB_INTCS_SIZE 0x00200000 /* 2MB */
#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
/* aliases */
#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
/* PCI intr ack share PCIW0 with PCI IO */
#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
/*
* Interrupt mapping
*
* We have three interrupt controllers:
*
* . CPU itself - 8 sources
* . i8259 - 16 sources
* . vrc5476 - 16 sources
*
* They connected as follows:
* all vrc5476 interrupts are routed to cpu IP2 (by software setting)
* all i2869 are routed to INTC in vrc5476 (by hardware connection)
*
* All VRC5476 PCI interrupts are level-triggered (no ack needed).
* All PCI irq but INTC are active low.
*/
/*
* irq number block assignment
*/
#define NUM_CPU_IRQ 8
#define NUM_I8259_IRQ 16
#define NUM_VRC5476_IRQ 16
#define DDB_IRQ_BASE 0
#define I8259_IRQ_BASE DDB_IRQ_BASE
#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
/*
* vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
*/
#define VRC5476_IRQ_CPCE 0 /* cpu parity error */
#define VRC5476_IRQ_CNTD 1 /* cpu no target */
#define VRC5476_IRQ_MCE 2 /* memory check error */
#define VRC5476_IRQ_DMA 3 /* DMA */
#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */
#define VRC5476_IRQ_WDOG 5 /* watchdog timer */
#define VRC5476_IRQ_GPT 6 /* general purpose timer */
#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */
#define VRC5476_IRQ_INTA 8 /* PCI INT #A */
#define VRC5476_IRQ_INTB 9 /* PCI INT #B */
#define VRC5476_IRQ_INTC 10 /* PCI INT #C */
#define VRC5476_IRQ_INTD 11 /* PCI INT #D */
#define VRC5476_IRQ_INTE 12 /* PCI INT #E */
#define VRC5476_IRQ_RESERVED_13 13 /* reserved */
#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */
#define VRC5476_IRQ_PCI 15 /* PCI internal error */
/*
* i2859 irq assignment
*/
#define I8259_IRQ_RESERVED_0 0
#define I8259_IRQ_KEYBOARD 1 /* M1543 default */
#define I8259_IRQ_CASCADE 2
#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */
#define I8259_IRQ_UART_A 4 /* M1543 default */
#define I8259_IRQ_PARALLEL 5 /* M1543 default */
#define I8259_IRQ_RESERVED_6 6
#define I8259_IRQ_RESERVED_7 7
#define I8259_IRQ_RTC 8 /* who set this? */
#define I8259_IRQ_USB 9 /* ddb_setup */
#define I8259_IRQ_PMU 10 /* ddb_setup */
#define I8259_IRQ_RESERVED_11 11
#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */
#define I8259_IRQ_RESERVED_13 13
#define I8259_IRQ_HDC1 14 /* default and ddb_setup */
#define I8259_IRQ_HDC2 15 /* default */
/*
* misc
*/
#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC
#define CPU_VRC5476_CASCADE 2
#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ)
#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ)
#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ)
/*
* low-level irq functions
*/
#ifndef __ASSEMBLY__
extern void nile4_map_irq(int nile4_irq, int cpu_irq);
extern void nile4_map_irq_all(int cpu_irq);
extern void nile4_enable_irq(int nile4_irq);
extern void nile4_disable_irq(int nile4_irq);
extern void nile4_disable_irq_all(void);
extern u16 nile4_get_irq_stat(int cpu_irq);
extern void nile4_enable_irq_output(int cpu_irq);
extern void nile4_disable_irq_output(int cpu_irq);
extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
extern void nile4_clear_irq(int nile4_irq);
extern void nile4_clear_irq_mask(u32 mask);
extern u8 nile4_i8259_iack(void);
extern void nile4_dump_irq_status(void); /* Debug */
#endif /* !__ASSEMBLY__ */

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/***********************************************************************
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* include/asm-mips/ddb5xxx/ddb5477.h
* DDB 5477 specific definitions and macros.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
***********************************************************************
*/
#ifndef __ASM_DDB5XXX_DDB5477_H
#define __ASM_DDB5XXX_DDB5477_H
#include <linux/config.h>
/*
* This contains macros that are specific to DDB5477 or renamed from
* DDB5476.
*/
/*
* renamed PADRs
*/
#define DDB_LCS0 DDB_DCS2
#define DDB_LCS1 DDB_DCS3
#define DDB_LCS2 DDB_DCS4
#define DDB_VRC5477 DDB_INTCS
/*
* New CPU interface registers
*/
#define DDB_INTCTRL0 0x0400 /* Interrupt Control 0 */
#define DDB_INTCTRL1 0x0404 /* Interrupt Control 1 */
#define DDB_INTCTRL2 0x0408 /* Interrupt Control 2 */
#define DDB_INTCTRL3 0x040c /* Interrupt Control 3 */
#define DDB_INT0STAT 0x0420 /* INT0 Status [R] */
#define DDB_INT1STAT 0x0428 /* INT1 Status [R] */
#define DDB_INT2STAT 0x0430 /* INT2 Status [R] */
#define DDB_INT3STAT 0x0438 /* INT3 Status [R] */
#define DDB_INT4STAT 0x0440 /* INT4 Status [R] */
#define DDB_NMISTAT 0x0450 /* NMI Status [R] */
#define DDB_INTCLR32 0x0468 /* Interrupt Clear */
#define DDB_INTPPES0 0x0470 /* PCI0 Interrupt Control */
#define DDB_INTPPES1 0x0478 /* PCI1 Interrupt Control */
#undef DDB_CPUSTAT /* duplicate in Vrc-5477 */
#define DDB_CPUSTAT 0x0480 /* CPU Status [R] */
#define DDB_BUSCTRL 0x0488 /* Internal Bus Control */
/*
* Timer registers
*/
#define DDB_REFCTRL_L DDB_T0CTRL
#define DDB_REFCTRL_H (DDB_T0CTRL+4)
#define DDB_REFCNTR DDB_T0CNTR
#define DDB_SPT0CTRL_L DDB_T1CTRL
#define DDB_SPT0CTRL_H (DDB_T1CTRL+4)
#define DDB_SPT1CTRL_L DDB_T2CTRL
#define DDB_SPT1CTRL_H (DDB_T2CTRL+4)
#define DDB_SPT1CNTR DDB_T1CTRL
#define DDB_WDTCTRL_L DDB_T3CTRL
#define DDB_WDTCTRL_H (DDB_T3CTRL+4)
#define DDB_WDTCNTR DDB_T3CNTR
/*
* DMA registers are moved. We don't care about it for now. TODO.
*/
/*
* BARs for ext PCI (PCI0)
*/
#undef DDB_BARC
#undef DDB_BARB
#define DDB_BARC0 0x0210 /* PCI0 Control */
#define DDB_BARM010 0x0218 /* PCI0 SDRAM bank01 */
#define DDB_BARM230 0x0220 /* PCI0 SDRAM bank23 */
#define DDB_BAR00 0x0240 /* PCI0 LDCS0 */
#define DDB_BAR10 0x0248 /* PCI0 LDCS1 */
#define DDB_BAR20 0x0250 /* PCI0 LDCS2 */
#define DDB_BAR30 0x0258 /* PCI0 LDCS3 */
#define DDB_BAR40 0x0260 /* PCI0 LDCS4 */
#define DDB_BAR50 0x0268 /* PCI0 LDCS5 */
#define DDB_BARB0 0x0280 /* PCI0 BOOT */
#define DDB_BARP00 0x0290 /* PCI0 for IOPCI Window0 */
#define DDB_BARP10 0x0298 /* PCI0 for IOPCI Window1 */
/*
* BARs for IOPIC (PCI1)
*/
#define DDB_BARC1 0x0610 /* PCI1 Control */
#define DDB_BARM011 0x0618 /* PCI1 SDRAM bank01 */
#define DDB_BARM231 0x0620 /* PCI1 SDRAM bank23 */
#define DDB_BAR01 0x0640 /* PCI1 LDCS0 */
#define DDB_BAR11 0x0648 /* PCI1 LDCS1 */
#define DDB_BAR21 0x0650 /* PCI1 LDCS2 */
#define DDB_BAR31 0x0658 /* PCI1 LDCS3 */
#define DDB_BAR41 0x0660 /* PCI1 LDCS4 */
#define DDB_BAR51 0x0668 /* PCI1 LDCS5 */
#define DDB_BARB1 0x0680 /* PCI1 BOOT */
#define DDB_BARP01 0x0690 /* PCI1 for ext PCI Window0 */
#define DDB_BARP11 0x0698 /* PCI1 for ext PCI Window1 */
/*
* Other registers for ext PCI (PCI0)
*/
#define DDB_PCIINIT00 0x02f0 /* PCI0 Initiator 0 */
#define DDB_PCIINIT10 0x02f8 /* PCI0 Initiator 1 */
#define DDB_PCISWP0 0x02b0 /* PCI0 Swap */
#define DDB_PCIERR0 0x02b8 /* PCI0 Error */
#define DDB_PCICTL0_L 0x02e0 /* PCI0 Control-L */
#define DDB_PCICTL0_H 0x02e4 /* PCI0 Control-H */
#define DDB_PCIARB0_L 0x02e8 /* PCI0 Arbitration-L */
#define DDB_PCIARB0_H 0x02ec /* PCI0 Arbitration-H */
/*
* Other registers for IOPCI (PCI1)
*/
#define DDB_IOPCIW0 0x00d0 /* PCI Address Window 0 [R/W] */
#define DDB_IOPCIW1 0x00d8 /* PCI Address Window 1 [R/W] */
#define DDB_PCIINIT01 0x06f0 /* PCI1 Initiator 0 */
#define DDB_PCIINIT11 0x06f8 /* PCI1 Initiator 1 */
#define DDB_PCISWP1 0x06b0 /* PCI1 Swap */
#define DDB_PCIERR1 0x06b8 /* PCI1 Error */
#define DDB_PCICTL1_L 0x06e0 /* PCI1 Control-L */
#define DDB_PCICTL1_H 0x06e4 /* PCI1 Control-H */
#define DDB_PCIARB1_L 0x06e8 /* PCI1 Arbitration-L */
#define DDB_PCIARB1_H 0x06ec /* PCI1 Arbitration-H */
/*
* Local Bus
*/
#define DDB_LCST0 0x0110 /* LB Chip Select Timing 0 */
#define DDB_LCST1 0x0118 /* LB Chip Select Timing 1 */
#undef DDB_LCST2
#define DDB_LCST2 0x0120 /* LB Chip Select Timing 2 */
#undef DDB_LCST3
#undef DDB_LCST4
#undef DDB_LCST5
#undef DDB_LCST6
#undef DDB_LCST7
#undef DDB_LCST8
#define DDB_ERRADR 0x0150 /* Error Address Register */
#define DDB_ERRCS 0x0160
#define DDB_BTM 0x0170 /* Boot Time Mode value */
/*
* MISC registers
*/
#define DDB_GIUFUNSEL 0x4040 /* select dual-func pins */
#define DDB_PIBMISC 0x0750 /* USB buffer enable / power saving */
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
/* the actual ram size is detected at run-time */
#define DDB_SDRAM_BASE 0x00000000
#define DDB_MAX_SDRAM_SIZE 0x08000000 /* less than 128MB */
#define DDB_PCI0_MEM_BASE 0x08000000
#define DDB_PCI0_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_PCI1_MEM_BASE 0x10000000
#define DDB_PCI1_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_PCI0_CONFIG_BASE 0x18000000
#define DDB_PCI0_CONFIG_SIZE 0x01000000 /* 16 MB */
#define DDB_PCI1_CONFIG_BASE 0x19000000
#define DDB_PCI1_CONFIG_SIZE 0x01000000 /* 16 MB */
#define DDB_PCI_IO_BASE 0x1a000000 /* we concatenate two IOs */
#define DDB_PCI0_IO_BASE 0x1a000000
#define DDB_PCI0_IO_SIZE 0x01000000 /* 16 MB */
#define DDB_PCI1_IO_BASE 0x1b000000
#define DDB_PCI1_IO_SIZE 0x01000000 /* 16 MB */
#define DDB_LCS0_BASE 0x1c000000 /* flash memory */
#define DDB_LCS0_SIZE 0x01000000 /* 16 MB */
#define DDB_LCS1_BASE 0x1d000000 /* misc */
#define DDB_LCS1_SIZE 0x01000000 /* 16 MB */
#define DDB_LCS2_BASE 0x1e000000 /* Mezzanine */
#define DDB_LCS2_SIZE 0x01000000 /* 16 MB */
#define DDB_VRC5477_BASE 0x1fa00000 /* VRC5477 control regs */
#define DDB_VRC5477_SIZE 0x00200000 /* 2MB */
#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
#define DDB_LED DDB_LCS1_BASE + 0x10000
/*
* DDB5477 specific functions
*/
#ifndef __ASSEMBLY__
extern void ddb5477_irq_setup(void);
/* route irq to cpu int pin */
extern void ll_vrc5477_irq_route(int vrc5477_irq, int ip);
/* low-level routine for enabling vrc5477 irq, bypassing high-level */
extern void ll_vrc5477_irq_enable(int vrc5477_irq);
extern void ll_vrc5477_irq_disable(int vrc5477_irq);
#endif /* !__ASSEMBLY__ */
/* PCI intr ack share PCIW0 with PCI IO */
#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
/*
* Interrupt mapping
*
* We have three interrupt controllers:
*
* . CPU itself - 8 sources
* . i8259 - 16 sources
* . vrc5477 - 32 sources
*
* They connected as follows:
* all vrc5477 interrupts are routed to cpu IP2 (by software setting)
* all i8359 are routed to INTC in vrc5477 (by hardware connection)
*
* All VRC5477 PCI interrupts are level-triggered (no ack needed).
* All PCI irq but INTC are active low.
*/
/*
* irq number block assignment
*/
#define NUM_CPU_IRQ 8
#define NUM_I8259_IRQ 16
#define NUM_VRC5477_IRQ 32
#define DDB_IRQ_BASE 0
#define I8259_IRQ_BASE DDB_IRQ_BASE
#define VRC5477_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
#define CPU_IRQ_BASE (VRC5477_IRQ_BASE + NUM_VRC5477_IRQ)
/*
* vrc5477 irq defs
*/
#define VRC5477_IRQ_CPCE (0 + VRC5477_IRQ_BASE) /* cpu parity error */
#define VRC5477_IRQ_CNTD (1 + VRC5477_IRQ_BASE) /* cpu no target */
#define VRC5477_IRQ_I2C (2 + VRC5477_IRQ_BASE) /* I2C */
#define VRC5477_IRQ_DMA (3 + VRC5477_IRQ_BASE) /* DMA */
#define VRC5477_IRQ_UART0 (4 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_WDOG (5 + VRC5477_IRQ_BASE) /* watchdog timer */
#define VRC5477_IRQ_SPT1 (6 + VRC5477_IRQ_BASE) /* special purpose timer 1 */
#define VRC5477_IRQ_LBRT (7 + VRC5477_IRQ_BASE) /* local bus read timeout */
#define VRC5477_IRQ_INTA (8 + VRC5477_IRQ_BASE) /* PCI INT #A */
#define VRC5477_IRQ_INTB (9 + VRC5477_IRQ_BASE) /* PCI INT #B */
#define VRC5477_IRQ_INTC (10 + VRC5477_IRQ_BASE) /* PCI INT #C */
#define VRC5477_IRQ_INTD (11 + VRC5477_IRQ_BASE) /* PCI INT #D */
#define VRC5477_IRQ_INTE (12 + VRC5477_IRQ_BASE) /* PCI INT #E */
#define VRC5477_IRQ_RESERVED_13 (13 + VRC5477_IRQ_BASE) /* reserved */
#define VRC5477_IRQ_PCIS (14 + VRC5477_IRQ_BASE) /* PCI SERR # */
#define VRC5477_IRQ_PCI (15 + VRC5477_IRQ_BASE) /* PCI internal error */
#define VRC5477_IRQ_IOPCI_INTA (16 + VRC5477_IRQ_BASE) /* USB-H */
#define VRC5477_IRQ_IOPCI_INTB (17 + VRC5477_IRQ_BASE) /* USB-P */
#define VRC5477_IRQ_IOPCI_INTC (18 + VRC5477_IRQ_BASE) /* AC97 */
#define VRC5477_IRQ_IOPCI_INTD (19 + VRC5477_IRQ_BASE) /* Reserved */
#define VRC5477_IRQ_UART1 (20 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_SPT0 (21 + VRC5477_IRQ_BASE) /* special purpose timer 0 */
#define VRC5477_IRQ_GPT0 (22 + VRC5477_IRQ_BASE) /* general purpose timer 0 */
#define VRC5477_IRQ_GPT1 (23 + VRC5477_IRQ_BASE) /* general purpose timer 1 */
#define VRC5477_IRQ_GPT2 (24 + VRC5477_IRQ_BASE) /* general purpose timer 2 */
#define VRC5477_IRQ_GPT3 (25 + VRC5477_IRQ_BASE) /* general purpose timer 3 */
#define VRC5477_IRQ_GPIO (26 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_SIO0 (27 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_SIO1 (28 + VRC5477_IRQ_BASE)
#define VRC5477_IRQ_RESERVED_29 (29 + VRC5477_IRQ_BASE) /* reserved */
#define VRC5477_IRQ_IOPCISERR (30 + VRC5477_IRQ_BASE) /* IO PCI SERR # */
#define VRC5477_IRQ_IOPCI (31 + VRC5477_IRQ_BASE)
/*
* i2859 irq assignment
*/
#define I8259_IRQ_RESERVED_0 (0 + I8259_IRQ_BASE)
#define I8259_IRQ_KEYBOARD (1 + I8259_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_CASCADE (2 + I8259_IRQ_BASE)
#define I8259_IRQ_UART_B (3 + I8259_IRQ_BASE) /* M1543 default, may conflict with RTC according to schematic diagram */
#define I8259_IRQ_UART_A (4 + I8259_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_PARALLEL (5 + I8259_IRQ_BASE) /* M1543 default */
#define I8259_IRQ_RESERVED_6 (6 + I8259_IRQ_BASE)
#define I8259_IRQ_RESERVED_7 (7 + I8259_IRQ_BASE)
#define I8259_IRQ_RTC (8 + I8259_IRQ_BASE) /* who set this? */
#define I8259_IRQ_USB (9 + I8259_IRQ_BASE) /* ddb_setup */
#define I8259_IRQ_PMU (10 + I8259_IRQ_BASE) /* ddb_setup */
#define I8259_IRQ_RESERVED_11 (11 + I8259_IRQ_BASE)
#define I8259_IRQ_RESERVED_12 (12 + I8259_IRQ_BASE) /* m1543_irq_setup */
#define I8259_IRQ_RESERVED_13 (13 + I8259_IRQ_BASE)
#define I8259_IRQ_HDC1 (14 + I8259_IRQ_BASE) /* default and ddb_setup */
#define I8259_IRQ_HDC2 (15 + I8259_IRQ_BASE) /* default */
/*
* misc
*/
#define VRC5477_I8259_CASCADE (VRC5477_IRQ_INTC - VRC5477_IRQ_BASE)
#define CPU_VRC5477_CASCADE 2
/*
* debug routines
*/
#ifndef __ASSEMBLY__
#if defined(CONFIG_RUNTIME_DEBUG)
extern void vrc5477_show_pdar_regs(void);
extern void vrc5477_show_pci_regs(void);
extern void vrc5477_show_bar_regs(void);
extern void vrc5477_show_int_regs(void);
extern void vrc5477_show_all_regs(void);
#endif
/*
* RAM size
*/
extern int board_ram_size;
#endif /* !__ASSEMBLY__ */
#endif /* __ASM_DDB5XXX_DDB5477_H */

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/*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*
* include/asm-mips/ddb5xxx/ddb5xxx.h
* Common header for all NEC DDB 5xxx boards, including 5074, 5476, 5477.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __ASM_DDB5XXX_DDB5XXX_H
#define __ASM_DDB5XXX_DDB5XXX_H
#include <linux/config.h>
#include <linux/types.h>
/*
* This file is based on the following documentation:
*
* NEC Vrc 5074 System Controller Data Sheet, June 1998
*
* [jsun] It is modified so that this file only contains the macros
* that are true for all DDB 5xxx boards. The modification is based on
*
* uPD31577(VRC5477) VR5432-SDRAM/PCI Bridge (Luke)
* Preliminary Specification Decoment, Rev 1.1, 27 Dec, 2000
*
*/
#define DDB_BASE 0xbfa00000
#define DDB_SIZE 0x00200000 /* 2 MB */
/*
* Physical Device Address Registers (PDARs)
*/
#define DDB_SDRAM0 0x0000 /* SDRAM Bank 0 [R/W] */
#define DDB_SDRAM1 0x0008 /* SDRAM Bank 1 [R/W] */
#define DDB_DCS2 0x0010 /* Device Chip-Select 2 [R/W] */
#define DDB_DCS3 0x0018 /* Device Chip-Select 3 [R/W] */
#define DDB_DCS4 0x0020 /* Device Chip-Select 4 [R/W] */
#define DDB_DCS5 0x0028 /* Device Chip-Select 5 [R/W] */
#define DDB_DCS6 0x0030 /* Device Chip-Select 6 [R/W] */
#define DDB_DCS7 0x0038 /* Device Chip-Select 7 [R/W] */
#define DDB_DCS8 0x0040 /* Device Chip-Select 8 [R/W] */
#define DDB_PCIW0 0x0060 /* PCI Address Window 0 [R/W] */
#define DDB_PCIW1 0x0068 /* PCI Address Window 1 [R/W] */
#define DDB_INTCS 0x0070 /* Controller Internal Registers and Devices */
/* [R/W] */
#define DDB_BOOTCS 0x0078 /* Boot ROM Chip-Select [R/W] */
/* Vrc5477 has two more, IOPCIW0, IOPCIW1 */
/*
* CPU Interface Registers
*/
#define DDB_CPUSTAT 0x0080 /* CPU Status [R/W] */
#define DDB_INTCTRL 0x0088 /* Interrupt Control [R/W] */
#define DDB_INTSTAT0 0x0090 /* Interrupt Status 0 [R] */
#define DDB_INTSTAT1 0x0098 /* Interrupt Status 1 and CPU Interrupt */
/* Enable [R/W] */
#define DDB_INTCLR 0x00A0 /* Interrupt Clear [R/W] */
#define DDB_INTPPES 0x00A8 /* PCI Interrupt Control [R/W] */
/*
* Memory-Interface Registers
*/
#define DDB_MEMCTRL 0x00C0 /* Memory Control */
#define DDB_ACSTIME 0x00C8 /* Memory Access Timing [R/W] */
#define DDB_CHKERR 0x00D0 /* Memory Check Error Status [R] */
/*
* PCI-Bus Registers
*/
#define DDB_PCICTRL 0x00E0 /* PCI Control [R/W] */
#define DDB_PCIARB 0x00E8 /* PCI Arbiter [R/W] */
#define DDB_PCIINIT0 0x00F0 /* PCI Master (Initiator) 0 [R/W] */
#define DDB_PCIINIT1 0x00F8 /* PCI Master (Initiator) 1 [R/W] */
#define DDB_PCIERR 0x00B8 /* PCI Error [R/W] */
/*
* Local-Bus Registers
*/
#define DDB_LCNFG 0x0100 /* Local Bus Configuration [R/W] */
#define DDB_LCST2 0x0110 /* Local Bus Chip-Select Timing 2 [R/W] */
#define DDB_LCST3 0x0118 /* Local Bus Chip-Select Timing 3 [R/W] */
#define DDB_LCST4 0x0120 /* Local Bus Chip-Select Timing 4 [R/W] */
#define DDB_LCST5 0x0128 /* Local Bus Chip-Select Timing 5 [R/W] */
#define DDB_LCST6 0x0130 /* Local Bus Chip-Select Timing 6 [R/W] */
#define DDB_LCST7 0x0138 /* Local Bus Chip-Select Timing 7 [R/W] */
#define DDB_LCST8 0x0140 /* Local Bus Chip-Select Timing 8 [R/W] */
#define DDB_DCSFN 0x0150 /* Device Chip-Select Muxing and Output */
/* Enables [R/W] */
#define DDB_DCSIO 0x0158 /* Device Chip-Selects As I/O Bits [R/W] */
#define DDB_BCST 0x0178 /* Local Boot Chip-Select Timing [R/W] */
/*
* DMA Registers
*/
#define DDB_DMACTRL0 0x0180 /* DMA Control 0 [R/W] */
#define DDB_DMASRCA0 0x0188 /* DMA Source Address 0 [R/W] */
#define DDB_DMADESA0 0x0190 /* DMA Destination Address 0 [R/W] */
#define DDB_DMACTRL1 0x0198 /* DMA Control 1 [R/W] */
#define DDB_DMASRCA1 0x01A0 /* DMA Source Address 1 [R/W] */
#define DDB_DMADESA1 0x01A8 /* DMA Destination Address 1 [R/W] */
/*
* Timer Registers
*/
#define DDB_T0CTRL 0x01C0 /* SDRAM Refresh Control [R/W] */
#define DDB_T0CNTR 0x01C8 /* SDRAM Refresh Counter [R/W] */
#define DDB_T1CTRL 0x01D0 /* CPU-Bus Read Time-Out Control [R/W] */
#define DDB_T1CNTR 0x01D8 /* CPU-Bus Read Time-Out Counter [R/W] */
#define DDB_T2CTRL 0x01E0 /* General-Purpose Timer Control [R/W] */
#define DDB_T2CNTR 0x01E8 /* General-Purpose Timer Counter [R/W] */
#define DDB_T3CTRL 0x01F0 /* Watchdog Timer Control [R/W] */
#define DDB_T3CNTR 0x01F8 /* Watchdog Timer Counter [R/W] */
/*
* PCI Configuration Space Registers
*/
#define DDB_PCI_BASE 0x0200
#define DDB_VID 0x0200 /* PCI Vendor ID [R] */
#define DDB_DID 0x0202 /* PCI Device ID [R] */
#define DDB_PCICMD 0x0204 /* PCI Command [R/W] */
#define DDB_PCISTS 0x0206 /* PCI Status [R/W] */
#define DDB_REVID 0x0208 /* PCI Revision ID [R] */
#define DDB_CLASS 0x0209 /* PCI Class Code [R] */
#define DDB_CLSIZ 0x020C /* PCI Cache Line Size [R/W] */
#define DDB_MLTIM 0x020D /* PCI Latency Timer [R/W] */
#define DDB_HTYPE 0x020E /* PCI Header Type [R] */
#define DDB_BIST 0x020F /* BIST [R] (unimplemented) */
#define DDB_BARC 0x0210 /* PCI Base Address Register Control [R/W] */
#define DDB_BAR0 0x0218 /* PCI Base Address Register 0 [R/W] */
#define DDB_BAR1 0x0220 /* PCI Base Address Register 1 [R/W] */
#define DDB_CIS 0x0228 /* PCI Cardbus CIS Pointer [R] */
/* (unimplemented) */
#define DDB_SSVID 0x022C /* PCI Sub-System Vendor ID [R/W] */
#define DDB_SSID 0x022E /* PCI Sub-System ID [R/W] */
#define DDB_ROM 0x0230 /* Expansion ROM Base Address [R] */
/* (unimplemented) */
#define DDB_INTLIN 0x023C /* PCI Interrupt Line [R/W] */
#define DDB_INTPIN 0x023D /* PCI Interrupt Pin [R] */
#define DDB_MINGNT 0x023E /* PCI Min_Gnt [R] (unimplemented) */
#define DDB_MAXLAT 0x023F /* PCI Max_Lat [R] (unimplemented) */
#define DDB_BAR2 0x0240 /* PCI Base Address Register 2 [R/W] */
#define DDB_BAR3 0x0248 /* PCI Base Address Register 3 [R/W] */
#define DDB_BAR4 0x0250 /* PCI Base Address Register 4 [R/W] */
#define DDB_BAR5 0x0258 /* PCI Base Address Register 5 [R/W] */
#define DDB_BAR6 0x0260 /* PCI Base Address Register 6 [R/W] */
#define DDB_BAR7 0x0268 /* PCI Base Address Register 7 [R/W] */
#define DDB_BAR8 0x0270 /* PCI Base Address Register 8 [R/W] */
#define DDB_BARB 0x0278 /* PCI Base Address Register BOOT [R/W] */
/*
* Nile 4 Register Access
*/
static inline void ddb_sync(void)
{
/* The DDB5074 doesn't seem to like these accesses. They kill the board on
* interrupt load
*/
#ifndef CONFIG_DDB5074
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
#endif
}
static inline void ddb_out32(u32 offset, u32 val)
{
*(volatile u32 *)(DDB_BASE+offset) = val;
ddb_sync();
}
static inline u32 ddb_in32(u32 offset)
{
u32 val = *(volatile u32 *)(DDB_BASE+offset);
ddb_sync();
return val;
}
static inline void ddb_out16(u32 offset, u16 val)
{
*(volatile u16 *)(DDB_BASE+offset) = val;
ddb_sync();
}
static inline u16 ddb_in16(u32 offset)
{
u16 val = *(volatile u16 *)(DDB_BASE+offset);
ddb_sync();
return val;
}
static inline void ddb_out8(u32 offset, u8 val)
{
*(volatile u8 *)(DDB_BASE+offset) = val;
ddb_sync();
}
static inline u8 ddb_in8(u32 offset)
{
u8 val = *(volatile u8 *)(DDB_BASE+offset);
ddb_sync();
return val;
}
/*
* Physical Device Address Registers
*/
extern u32
ddb_calc_pdar(u32 phys, u32 size, int width, int on_memory_bus, int pci_visible);
extern void
ddb_set_pdar(u32 pdar, u32 phys, u32 size, int width,
int on_memory_bus, int pci_visible);
/*
* PCI Master Registers
*/
#define DDB_PCICMD_IACK 0 /* PCI Interrupt Acknowledge */
#define DDB_PCICMD_IO 1 /* PCI I/O Space */
#define DDB_PCICMD_MEM 3 /* PCI Memory Space */
#define DDB_PCICMD_CFG 5 /* PCI Configuration Space */
/*
* additional options for pci init reg (no shifting needed)
*/
#define DDB_PCI_CFGTYPE1 0x200 /* for pci init0/1 regs */
#define DDB_PCI_ACCESS_32 0x10 /* for pci init0/1 regs */
extern void ddb_set_pmr(u32 pmr, u32 type, u32 addr, u32 options);
/*
* we need to reset pci bus when we start up and shutdown
*/
extern void ddb_pci_reset_bus(void);
/*
* include the board dependent part
*/
#if defined(CONFIG_DDB5074)
#include <asm/ddb5xxx/ddb5074.h>
#elif defined(CONFIG_DDB5476)
#include <asm/ddb5xxx/ddb5476.h>
#elif defined(CONFIG_DDB5477)
#include <asm/ddb5xxx/ddb5477.h>
#else
#error "Unknown DDB board!"
#endif
#endif /* __ASM_DDB5XXX_DDB5XXX_H */

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/*
* Debug macros for run-time debugging.
* Turned on/off with CONFIG_RUNTIME_DEBUG option.
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef _ASM_DEBUG_H
#define _ASM_DEBUG_H
#include <linux/config.h>
/*
* run-time macros for catching spurious errors. Eable CONFIG_RUNTIME_DEBUG in
* kernel hacking config menu to use them.
*
* Use them as run-time debugging aid. NEVER USE THEM AS ERROR HANDLING CODE!!!
*/
#ifdef CONFIG_RUNTIME_DEBUG
#include <linux/kernel.h>
#define db_assert(x) if (!(x)) { \
panic("assertion failed at %s:%d: %s\n", __FILE__, __LINE__, #x); }
#define db_warn(x) if (!(x)) { \
printk(KERN_WARNING "warning at %s:%d: %s\n", __FILE__, __LINE__, #x); }
#define db_verify(x, y) db_assert(x y)
#define db_verify_warn(x, y) db_warn(x y)
#define db_run(x) do { x; } while (0)
#else
#define db_assert(x)
#define db_warn(x)
#define db_verify(x, y) x
#define db_verify_warn(x, y) x
#define db_run(x)
#endif
#endif /* _ASM_DEBUG_H */

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/*
* include/asm-mips/dec/ecc.h
*
* ECC handling logic definitions common to DECstation/DECsystem
* 5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and
* DECsystem 5900 (KN03), 5900/260 (KN05) systems.
*
* Copyright (C) 2003 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_ECC_H
#define __ASM_MIPS_DEC_ECC_H
/*
* Error Address Register bits.
* The register is r/wc -- any write clears it.
*/
#define KN0X_EAR_VALID (1<<31) /* error data valid, bus IRQ */
#define KN0X_EAR_CPU (1<<30) /* CPU/DMA transaction */
#define KN0X_EAR_WRITE (1<<29) /* write/read transaction */
#define KN0X_EAR_ECCERR (1<<28) /* ECC/timeout or overrun */
#define KN0X_EAR_RES_27 (1<<27) /* unused */
#define KN0X_EAR_ADDRESS (0x7ffffff<<0) /* address involved */
/*
* Error Syndrome Register bits.
* The register is frozen when EAR.VALID is set, otherwise it records bits
* from the last memory read. The register is r/wc -- any write clears it.
*/
#define KN0X_ESR_VLDHI (1<<31) /* error data valid hi word */
#define KN0X_ESR_CHKHI (0x7f<<24) /* check bits read from mem */
#define KN0X_ESR_SNGHI (1<<23) /* single/double bit error */
#define KN0X_ESR_SYNHI (0x7f<<16) /* syndrome from ECC logic */
#define KN0X_ESR_VLDLO (1<<15) /* error data valid lo word */
#define KN0X_ESR_CHKLO (0x7f<<8) /* check bits read from mem */
#define KN0X_ESR_SNGLO (1<<7) /* single/double bit error */
#define KN0X_ESR_SYNLO (0x7f<<0) /* syndrome from ECC logic */
#ifndef __ASSEMBLY__
#include <linux/interrupt.h>
struct pt_regs;
extern void dec_ecc_be_init(void);
extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id, struct pt_regs *regs);
#endif
#endif /* __ASM_MIPS_DEC_ECC_H */

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/*
* Miscellaneous definitions used to initialise the interrupt vector table
* with the machine-specific interrupt routines.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1997 by Paul M. Antoine.
* reworked 1998 by Harald Koerfgen.
* Copyright (C) 2001, 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_DEC_INTERRUPTS_H
#define __ASM_DEC_INTERRUPTS_H
#include <asm/mipsregs.h>
/*
* The list of possible system devices which provide an
* interrupt. Not all devices exist on a given system.
*/
#define DEC_IRQ_CASCADE 0 /* cascade from CSR or I/O ASIC */
/* Ordinary interrupts */
#define DEC_IRQ_AB_RECV 1 /* ACCESS.bus receive */
#define DEC_IRQ_AB_XMIT 2 /* ACCESS.bus transmit */
#define DEC_IRQ_DZ11 3 /* DZ11 (DC7085) serial */
#define DEC_IRQ_ASC 4 /* ASC (NCR53C94) SCSI */
#define DEC_IRQ_FLOPPY 5 /* 82077 FDC */
#define DEC_IRQ_FPU 6 /* R3k FPU */
#define DEC_IRQ_HALT 7 /* HALT button or from ACCESS.Bus */
#define DEC_IRQ_ISDN 8 /* Am79C30A ISDN */
#define DEC_IRQ_LANCE 9 /* LANCE (Am7990) Ethernet */
#define DEC_IRQ_BUS 10 /* memory, I/O bus read/write errors */
#define DEC_IRQ_PSU 11 /* power supply unit warning */
#define DEC_IRQ_RTC 12 /* DS1287 RTC */
#define DEC_IRQ_SCC0 13 /* SCC (Z85C30) serial #0 */
#define DEC_IRQ_SCC1 14 /* SCC (Z85C30) serial #1 */
#define DEC_IRQ_SII 15 /* SII (DC7061) SCSI */
#define DEC_IRQ_TC0 16 /* TURBOchannel slot #0 */
#define DEC_IRQ_TC1 17 /* TURBOchannel slot #1 */
#define DEC_IRQ_TC2 18 /* TURBOchannel slot #2 */
#define DEC_IRQ_TIMER 19 /* ARC periodic timer */
#define DEC_IRQ_VIDEO 20 /* framebuffer */
/* I/O ASIC DMA interrupts */
#define DEC_IRQ_ASC_MERR 21 /* ASC memory read error */
#define DEC_IRQ_ASC_ERR 22 /* ASC page overrun */
#define DEC_IRQ_ASC_DMA 23 /* ASC buffer pointer loaded */
#define DEC_IRQ_FLOPPY_ERR 24 /* FDC error */
#define DEC_IRQ_ISDN_ERR 25 /* ISDN memory read/overrun error */
#define DEC_IRQ_ISDN_RXDMA 26 /* ISDN recv buffer pointer loaded */
#define DEC_IRQ_ISDN_TXDMA 27 /* ISDN xmit buffer pointer loaded */
#define DEC_IRQ_LANCE_MERR 28 /* LANCE memory read error */
#define DEC_IRQ_SCC0A_RXERR 29 /* SCC0A (printer) receive overrun */
#define DEC_IRQ_SCC0A_RXDMA 30 /* SCC0A receive half page */
#define DEC_IRQ_SCC0A_TXERR 31 /* SCC0A xmit memory read/overrun */
#define DEC_IRQ_SCC0A_TXDMA 32 /* SCC0A transmit page end */
#define DEC_IRQ_AB_RXERR 33 /* ACCESS.bus receive overrun */
#define DEC_IRQ_AB_RXDMA 34 /* ACCESS.bus receive half page */
#define DEC_IRQ_AB_TXERR 35 /* ACCESS.bus xmit memory read/ovrn */
#define DEC_IRQ_AB_TXDMA 36 /* ACCESS.bus transmit page end */
#define DEC_IRQ_SCC1A_RXERR 37 /* SCC1A (modem) receive overrun */
#define DEC_IRQ_SCC1A_RXDMA 38 /* SCC1A receive half page */
#define DEC_IRQ_SCC1A_TXERR 39 /* SCC1A xmit memory read/overrun */
#define DEC_IRQ_SCC1A_TXDMA 40 /* SCC1A transmit page end */
/* TC5 & TC6 are virtual slots for KN02's onboard devices */
#define DEC_IRQ_TC5 DEC_IRQ_ASC /* virtual PMAZ-AA */
#define DEC_IRQ_TC6 DEC_IRQ_LANCE /* virtual PMAD-AA */
#define DEC_NR_INTS 41
/* Largest of cpu mask_nr tables. */
#define DEC_MAX_CPU_INTS 6
/* Largest of asic mask_nr tables. */
#define DEC_MAX_ASIC_INTS 9
/*
* CPU interrupt bits common to all systems.
*/
#define DEC_CPU_INR_FPU 7 /* R3k FPU */
#define DEC_CPU_INR_SW1 1 /* software #1 */
#define DEC_CPU_INR_SW0 0 /* software #0 */
#define DEC_CPU_IRQ_BASE 0 /* first IRQ assigned to CPU */
#define DEC_CPU_IRQ_NR(n) ((n) + DEC_CPU_IRQ_BASE)
#define DEC_CPU_IRQ_MASK(n) (1 << ((n) + CAUSEB_IP))
#define DEC_CPU_IRQ_ALL (0xff << CAUSEB_IP)
#ifndef __ASSEMBLY__
/*
* Interrupt table structures to hide differences between systems.
*/
typedef union { int i; void *p; } int_ptr;
extern int dec_interrupt[DEC_NR_INTS];
extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
extern int cpu_fpu_mask;
/*
* Common interrupt routine prototypes for all DECStations
*/
extern void kn02_io_int(void);
extern void kn02xa_io_int(void);
extern void kn03_io_int(void);
extern void asic_dma_int(void);
extern void asic_all_int(void);
extern void kn02_all_int(void);
extern void cpu_all_int(void);
extern void dec_intr_unimplemented(void);
extern void asic_intr_unimplemented(void);
#endif /* __ASSEMBLY__ */
#endif

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/*
* include/asm-mips/dec/ioasic.h
*
* DEC I/O ASIC access operations.
*
* Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_DEC_IOASIC_H
#define __ASM_DEC_IOASIC_H
#include <linux/spinlock.h>
#include <linux/types.h>
extern spinlock_t ioasic_ssr_lock;
extern volatile u32 *ioasic_base;
static inline void ioasic_write(unsigned int reg, u32 v)
{
ioasic_base[reg / 4] = v;
}
static inline u32 ioasic_read(unsigned int reg)
{
return ioasic_base[reg / 4];
}
extern void init_ioasic_irqs(int base);
#endif /* __ASM_DEC_IOASIC_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Definitions for the address map in the JUNKIO Asic
*
* Created with Information from:
*
* "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
*
* and the Mach Sources
*
* Copyright (C) 199x the Anonymous
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
#define __ASM_MIPS_DEC_IOASIC_ADDRS_H
#define IOASIC_SLOT_SIZE 0x00040000
/*
* Address ranges decoded by the I/O ASIC for onboard devices.
*/
#define IOASIC_SYS_ROM (0*IOASIC_SLOT_SIZE) /* system board ROM */
#define IOASIC_IOCTL (1*IOASIC_SLOT_SIZE) /* I/O ASIC */
#define IOASIC_ESAR (2*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
#define IOASIC_LANCE (3*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
#define IOASIC_SCC0 (4*IOASIC_SLOT_SIZE) /* SCC #0 */
#define IOASIC_VDAC_HI (5*IOASIC_SLOT_SIZE) /* VDAC (maxine) */
#define IOASIC_SCC1 (6*IOASIC_SLOT_SIZE) /* SCC #1 (3min, 3max+) */
#define IOASIC_VDAC_LO (7*IOASIC_SLOT_SIZE) /* VDAC (maxine) */
#define IOASIC_TOY (8*IOASIC_SLOT_SIZE) /* RTC */
#define IOASIC_ISDN (9*IOASIC_SLOT_SIZE) /* ISDN (maxine) */
#define IOASIC_ERRADDR (9*IOASIC_SLOT_SIZE) /* bus error address (3max+) */
#define IOASIC_CHKSYN (10*IOASIC_SLOT_SIZE) /* ECC syndrome (3max+) */
#define IOASIC_ACC_BUS (10*IOASIC_SLOT_SIZE) /* ACCESS.bus (maxine) */
#define IOASIC_MCR (11*IOASIC_SLOT_SIZE) /* memory control (3max+) */
#define IOASIC_FLOPPY (11*IOASIC_SLOT_SIZE) /* FDC (maxine) */
#define IOASIC_SCSI (12*IOASIC_SLOT_SIZE) /* ASC SCSI */
#define IOASIC_FDC_DMA (13*IOASIC_SLOT_SIZE) /* FDC DMA (maxine) */
#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE) /* ??? */
#define IOASIC_RES_15 (15*IOASIC_SLOT_SIZE) /* unused? */
/*
* Offsets for I/O ASIC registers (relative to (system_base + IOASIC_IOCTL)).
*/
/* all systems */
#define IO_REG_SCSI_DMA_P 0x00 /* SCSI DMA Pointer */
#define IO_REG_SCSI_DMA_BP 0x10 /* SCSI DMA Buffer Pointer */
#define IO_REG_LANCE_DMA_P 0x20 /* LANCE DMA Pointer */
#define IO_REG_SCC0A_T_DMA_P 0x30 /* SCC0A Transmit DMA Pointer */
#define IO_REG_SCC0A_R_DMA_P 0x40 /* SCC0A Receive DMA Pointer */
/* except Maxine */
#define IO_REG_SCC1A_T_DMA_P 0x50 /* SCC1A Transmit DMA Pointer */
#define IO_REG_SCC1A_R_DMA_P 0x60 /* SCC1A Receive DMA Pointer */
/* Maxine */
#define IO_REG_AB_T_DMA_P 0x50 /* ACCESS.bus Transmit DMA Pointer */
#define IO_REG_AB_R_DMA_P 0x60 /* ACCESS.bus Receive DMA Pointer */
#define IO_REG_FLOPPY_DMA_P 0x70 /* Floppy DMA Pointer */
#define IO_REG_ISDN_T_DMA_P 0x80 /* ISDN Transmit DMA Pointer */
#define IO_REG_ISDN_T_DMA_BP 0x90 /* ISDN Transmit DMA Buffer Pointer */
#define IO_REG_ISDN_R_DMA_P 0xa0 /* ISDN Receive DMA Pointer */
#define IO_REG_ISDN_R_DMA_BP 0xb0 /* ISDN Receive DMA Buffer Pointer */
/* all systems */
#define IO_REG_DATA_0 0xc0 /* System Data Buffer 0 */
#define IO_REG_DATA_1 0xd0 /* System Data Buffer 1 */
#define IO_REG_DATA_2 0xe0 /* System Data Buffer 2 */
#define IO_REG_DATA_3 0xf0 /* System Data Buffer 3 */
/* all systems */
#define IO_REG_SSR 0x100 /* System Support Register */
#define IO_REG_SIR 0x110 /* System Interrupt Register */
#define IO_REG_SIMR 0x120 /* System Interrupt Mask Reg. */
#define IO_REG_SAR 0x130 /* System Address Register */
/* Maxine */
#define IO_REG_ISDN_T_DATA 0x140 /* ISDN Xmit Data Register */
#define IO_REG_ISDN_R_DATA 0x150 /* ISDN Receive Data Register */
/* all systems */
#define IO_REG_LANCE_SLOT 0x160 /* LANCE I/O Slot Register */
#define IO_REG_SCSI_SLOT 0x170 /* SCSI Slot Register */
#define IO_REG_SCC0A_SLOT 0x180 /* SCC0A DMA Slot Register */
/* except Maxine */
#define IO_REG_SCC1A_SLOT 0x190 /* SCC1A DMA Slot Register */
/* Maxine */
#define IO_REG_AB_SLOT 0x190 /* ACCESS.bus DMA Slot Register */
#define IO_REG_FLOPPY_SLOT 0x1a0 /* Floppy Slot Register */
/* all systems */
#define IO_REG_SCSI_SCR 0x1b0 /* SCSI Partial-Word DMA Control */
#define IO_REG_SCSI_SDR0 0x1c0 /* SCSI DMA Partial Word 0 */
#define IO_REG_SCSI_SDR1 0x1d0 /* SCSI DMA Partial Word 1 */
#define IO_REG_FCTR 0x1e0 /* Free-Running Counter */
#define IO_REG_RES_31 0x1f0 /* unused */
/*
* The upper 16 bits of the System Support Register are a part of the
* I/O ASIC's internal DMA engine and thus are common to all I/O ASIC
* machines. The exception is the Maxine, which makes use of the
* FLOPPY and ISDN bits (otherwise unused) and has a different SCC
* wiring.
*/
/* all systems */
#define IO_SSR_SCC0A_TX_DMA_EN (1<<31) /* SCC0A transmit DMA enable */
#define IO_SSR_SCC0A_RX_DMA_EN (1<<30) /* SCC0A receive DMA enable */
#define IO_SSR_RES_27 (1<<27) /* unused */
#define IO_SSR_RES_26 (1<<26) /* unused */
#define IO_SSR_RES_25 (1<<25) /* unused */
#define IO_SSR_RES_24 (1<<24) /* unused */
#define IO_SSR_RES_23 (1<<23) /* unused */
#define IO_SSR_SCSI_DMA_DIR (1<<18) /* SCSI DMA direction */
#define IO_SSR_SCSI_DMA_EN (1<<17) /* SCSI DMA enable */
#define IO_SSR_LANCE_DMA_EN (1<<16) /* LANCE DMA enable */
/* except Maxine */
#define IO_SSR_SCC1A_TX_DMA_EN (1<<29) /* SCC1A transmit DMA enable */
#define IO_SSR_SCC1A_RX_DMA_EN (1<<28) /* SCC1A receive DMA enable */
#define IO_SSR_RES_22 (1<<22) /* unused */
#define IO_SSR_RES_21 (1<<21) /* unused */
#define IO_SSR_RES_20 (1<<20) /* unused */
#define IO_SSR_RES_19 (1<<19) /* unused */
/* Maxine */
#define IO_SSR_AB_TX_DMA_EN (1<<29) /* ACCESS.bus xmit DMA enable */
#define IO_SSR_AB_RX_DMA_EN (1<<28) /* ACCESS.bus recv DMA enable */
#define IO_SSR_FLOPPY_DMA_DIR (1<<22) /* Floppy DMA direction */
#define IO_SSR_FLOPPY_DMA_EN (1<<21) /* Floppy DMA enable */
#define IO_SSR_ISDN_TX_DMA_EN (1<<20) /* ISDN transmit DMA enable */
#define IO_SSR_ISDN_RX_DMA_EN (1<<19) /* ISDN receive DMA enable */
/*
* The lower 16 bits are system-specific. Bits 15,11:8 are common and
* defined here. The rest is defined in system-specific headers.
*/
#define KN0X_IO_SSR_DIAGDN (1<<15) /* diagnostic jumper */
#define KN0X_IO_SSR_SCC_RST (1<<11) /* ~SCC0,1 (Z85C30) reset */
#define KN0X_IO_SSR_RTC_RST (1<<10) /* ~RTC (DS1287) reset */
#define KN0X_IO_SSR_ASC_RST (1<<9) /* ~ASC (NCR53C94) reset */
#define KN0X_IO_SSR_LANCE_RST (1<<8) /* ~LANCE (Am7990) reset */
#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Definitions for the interrupt related bits in the I/O ASIC
* interrupt status register (and the interrupt mask register, of course)
*
* Created with Information from:
*
* "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
*
* and the Mach Sources
*
* Copyright (C) 199x the Anonymous
* Copyright (C) 2002 Maciej W. Rozycki
*/
#ifndef __ASM_DEC_IOASIC_INTS_H
#define __ASM_DEC_IOASIC_INTS_H
/*
* The upper 16 bits are a part of the I/O ASIC's internal DMA engine
* and thus are common to all I/O ASIC machines. The exception is
* the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise
* unused) and has a different SCC wiring.
*/
/* all systems */
#define IO_INR_SCC0A_TXDMA 31 /* SCC0A transmit page end */
#define IO_INR_SCC0A_TXERR 30 /* SCC0A transmit memory read error */
#define IO_INR_SCC0A_RXDMA 29 /* SCC0A receive half page */
#define IO_INR_SCC0A_RXERR 28 /* SCC0A receive overrun */
#define IO_INR_ASC_DMA 19 /* ASC buffer pointer loaded */
#define IO_INR_ASC_ERR 18 /* ASC page overrun */
#define IO_INR_ASC_MERR 17 /* ASC memory read error */
#define IO_INR_LANCE_MERR 16 /* LANCE memory read error */
/* except Maxine */
#define IO_INR_SCC1A_TXDMA 27 /* SCC1A transmit page end */
#define IO_INR_SCC1A_TXERR 26 /* SCC1A transmit memory read error */
#define IO_INR_SCC1A_RXDMA 25 /* SCC1A receive half page */
#define IO_INR_SCC1A_RXERR 24 /* SCC1A receive overrun */
#define IO_INR_RES_23 23 /* unused */
#define IO_INR_RES_22 22 /* unused */
#define IO_INR_RES_21 21 /* unused */
#define IO_INR_RES_20 20 /* unused */
/* Maxine */
#define IO_INR_AB_TXDMA 27 /* ACCESS.bus transmit page end */
#define IO_INR_AB_TXERR 26 /* ACCESS.bus xmit memory read error */
#define IO_INR_AB_RXDMA 25 /* ACCESS.bus receive half page */
#define IO_INR_AB_RXERR 24 /* ACCESS.bus receive overrun */
#define IO_INR_FLOPPY_ERR 23 /* FDC error */
#define IO_INR_ISDN_TXDMA 22 /* ISDN xmit buffer pointer loaded */
#define IO_INR_ISDN_RXDMA 21 /* ISDN recv buffer pointer loaded */
#define IO_INR_ISDN_ERR 20 /* ISDN memory read/overrun error */
#define IO_INR_DMA 16 /* first DMA IRQ */
/*
* The lower 16 bits are system-specific and thus defined in
* system-specific headers.
*/
#define IO_IRQ_BASE 8 /* first IRQ assigned to I/O ASIC */
#define IO_IRQ_LINES 32 /* number of I/O ASIC interrupts */
#define IO_IRQ_NR(n) ((n) + IO_IRQ_BASE)
#define IO_IRQ_MASK(n) (1 << (n))
#define IO_IRQ_ALL 0x0000ffff
#define IO_IRQ_DMA 0xffff0000
#endif /* __ASM_DEC_IOASIC_INTS_H */

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/*
* Hardware info about DECstation DS2100/3100 systems (otherwise known as
* pmin/pmax or KN01).
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
* are by courtesy of Chris Fraser.
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_KN01_H
#define __ASM_MIPS_DEC_KN01_H
#include <asm/addrspace.h>
#define KN01_SLOT_BASE KSEG1ADDR(0x10000000)
#define KN01_SLOT_SIZE 0x01000000
/*
* Address ranges for devices.
*/
#define KN01_PMASK (0*KN01_SLOT_SIZE) /* color plane mask */
#define KN01_PCC (1*KN01_SLOT_SIZE) /* PCC (DC503) cursor */
#define KN01_VDAC (2*KN01_SLOT_SIZE) /* color map */
#define KN01_RES_3 (3*KN01_SLOT_SIZE) /* unused */
#define KN01_RES_4 (4*KN01_SLOT_SIZE) /* unused */
#define KN01_RES_5 (5*KN01_SLOT_SIZE) /* unused */
#define KN01_RES_6 (6*KN01_SLOT_SIZE) /* unused */
#define KN01_ERRADDR (7*KN01_SLOT_SIZE) /* write error address */
#define KN01_LANCE (8*KN01_SLOT_SIZE) /* LANCE (Am7990) Ethernet */
#define KN01_LANCE_MEM (9*KN01_SLOT_SIZE) /* LANCE buffer memory */
#define KN01_SII (10*KN01_SLOT_SIZE) /* SII (DC7061) SCSI */
#define KN01_SII_MEM (11*KN01_SLOT_SIZE) /* SII buffer memory */
#define KN01_DZ11 (12*KN01_SLOT_SIZE) /* DZ11 (DC7085) serial */
#define KN01_RTC (13*KN01_SLOT_SIZE) /* DS1287 RTC (bytes #0) */
#define KN01_ESAR (13*KN01_SLOT_SIZE) /* MAC address (bytes #1) */
#define KN01_CSR (14*KN01_SLOT_SIZE) /* system ctrl & status reg */
#define KN01_SYS_ROM (15*KN01_SLOT_SIZE) /* system board ROM */
/*
* Some port addresses...
*/
#define KN01_LANCE_BASE (KN01_SLOT_BASE + KN01_LANCE) /* 0xB8000000 */
#define KN01_DZ11_BASE (KN01_SLOT_BASE + KN01_DZ11) /* 0xBC000000 */
#define KN01_RTC_BASE (KN01_SLOT_BASE + KN01_RTC) /* 0xBD000000 */
/*
* Frame buffer memory address.
*/
#define KN01_VFB_MEM KSEG1ADDR(0x0fc00000)
/*
* CPU interrupt bits.
*/
#define KN01_CPU_INR_BUS 6 /* memory, I/O bus read/write errors */
#define KN01_CPU_INR_VIDEO 6 /* PCC area detect #2 */
#define KN01_CPU_INR_RTC 5 /* DS1287 RTC */
#define KN01_CPU_INR_DZ11 4 /* DZ11 (DC7085) serial */
#define KN01_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */
#define KN01_CPU_INR_SII 2 /* SII (DC7061) SCSI */
/*
* System Control & Status Register bits.
*/
#define KN01_CSR_MNFMOD (1<<15) /* MNFMOD manufacturing jumper */
#define KN01_CSR_STATUS (1<<14) /* self-test result status output */
#define KN01_CSR_PARDIS (1<<13) /* parity error disable */
#define KN01_CSR_CRSRTST (1<<12) /* PCC test output */
#define KN01_CSR_MONO (1<<11) /* mono/color fb SIMM installed */
#define KN01_CSR_MEMERR (1<<10) /* write timeout error status & ack*/
#define KN01_CSR_VINT (1<<9) /* PCC area detect #2 status & ack */
#define KN01_CSR_TXDIS (1<<8) /* DZ11 transmit disable */
#define KN01_CSR_VBGTRG (1<<2) /* blue DAC voltage over green (r/o) */
#define KN01_CSR_VRGTRG (1<<1) /* red DAC voltage over green (r/o) */
#define KN01_CSR_VRGTRB (1<<0) /* red DAC voltage over blue (r/o) */
#define KN01_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
#endif /* __ASM_MIPS_DEC_KN01_H */

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/*
* Hardware info about DECstation 5000/200 systems (otherwise known as
* 3max or KN02).
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
* are by courtesy of Chris Fraser.
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_KN02_H
#define __ASM_MIPS_DEC_KN02_H
#ifndef __ASSEMBLY__
#include <linux/spinlock.h>
#include <linux/types.h>
#endif
#include <asm/addrspace.h>
#include <asm/dec/ecc.h>
#define KN02_SLOT_BASE KSEG1ADDR(0x1fc00000)
#define KN02_SLOT_SIZE 0x00080000
/*
* Address ranges decoded by the "system slot" logic for onboard devices.
*/
#define KN02_SYS_ROM (0*KN02_SLOT_SIZE) /* system board ROM */
#define KN02_RES_1 (1*KN02_SLOT_SIZE) /* unused */
#define KN02_CHKSYN (2*KN02_SLOT_SIZE) /* ECC syndrome */
#define KN02_ERRADDR (3*KN02_SLOT_SIZE) /* bus error address */
#define KN02_DZ11 (4*KN02_SLOT_SIZE) /* DZ11 (DC7085) serial */
#define KN02_RTC (5*KN02_SLOT_SIZE) /* DS1287 RTC */
#define KN02_CSR (6*KN02_SLOT_SIZE) /* system ctrl & status reg */
#define KN02_SYS_ROM_7 (7*KN02_SLOT_SIZE) /* system board ROM (alias) */
/*
* Some port addresses...
*/
#define KN02_DZ11_BASE (KN02_SLOT_BASE + KN02_DZ11) /* DZ11 */
#define KN02_RTC_BASE (KN02_SLOT_BASE + KN02_RTC) /* RTC */
#define KN02_CSR_BASE (KN02_SLOT_BASE + KN02_CSR) /* CSR */
/*
* System Control & Status Register bits.
*/
#define KN02_CSR_RES_28 (0xf<<28) /* unused */
#define KN02_CSR_PSU (1<<27) /* power supply unit warning */
#define KN02_CSR_NVRAM (1<<26) /* ~NVRAM clear jumper */
#define KN02_CSR_REFEVEN (1<<25) /* mem refresh bank toggle */
#define KN03_CSR_NRMOD (1<<24) /* ~NRMOD manufact. jumper */
#define KN03_CSR_IOINTEN (0xff<<16) /* IRQ mask bits */
#define KN02_CSR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
#define KN02_CSR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
#define KN02_CSR_CORRECT (1<<13) /* ECC correct/check */
#define KN02_CSR_LEDIAG (1<<12) /* ECC diagn. latch strobe */
#define KN02_CSR_TXDIS (1<<11) /* DZ11 transmit disable */
#define KN02_CSR_BNK32M (1<<10) /* 32M/8M stride */
#define KN02_CSR_DIAGDN (1<<9) /* DIAGDN manufact. jumper */
#define KN02_CSR_BAUD38 (1<<8) /* DZ11 38/19kbps ext. rate */
#define KN03_CSR_IOINT (0xff<<0) /* IRQ status bits (r/o) */
#define KN03_CSR_LEDS (0xff<<0) /* ~diagnostic LEDs (w/o) */
/*
* CPU interrupt bits.
*/
#define KN02_CPU_INR_RES_6 6 /* unused */
#define KN02_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
#define KN02_CPU_INR_RES_4 4 /* unused */
#define KN02_CPU_INR_RTC 3 /* DS1287 RTC */
#define KN02_CPU_INR_CASCADE 2 /* CSR cascade */
/*
* CSR interrupt bits.
*/
#define KN02_CSR_INR_DZ11 7 /* DZ11 (DC7085) serial */
#define KN02_CSR_INR_LANCE 6 /* LANCE (Am7990) Ethernet */
#define KN02_CSR_INR_ASC 5 /* ASC (NCR53C94) SCSI */
#define KN02_CSR_INR_RES_4 4 /* unused */
#define KN02_CSR_INR_RES_3 3 /* unused */
#define KN02_CSR_INR_TC2 2 /* TURBOchannel slot #2 */
#define KN02_CSR_INR_TC1 1 /* TURBOchannel slot #1 */
#define KN02_CSR_INR_TC0 0 /* TURBOchannel slot #0 */
#define KN02_IRQ_BASE 8 /* first IRQ assigned to CSR */
#define KN02_IRQ_LINES 8 /* number of CSR interrupts */
#define KN02_IRQ_NR(n) ((n) + KN02_IRQ_BASE)
#define KN02_IRQ_MASK(n) (1 << (n))
#define KN02_IRQ_ALL 0xff
#ifndef __ASSEMBLY__
extern u32 cached_kn02_csr;
extern spinlock_t kn02_lock;
extern void init_kn02_irqs(int base);
#endif
#endif /* __ASM_MIPS_DEC_KN02_H */

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/*
* include/asm-mips/dec/kn02ba.h
*
* DECstation 5000/1xx (3min or KN02-BA) definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_KN02BA_H
#define __ASM_MIPS_DEC_KN02BA_H
#include <asm/dec/kn02xa.h> /* For common definitions. */
/*
* CPU interrupt bits.
*/
#define KN02BA_CPU_INR_HALT 6 /* HALT button */
#define KN02BA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */
#define KN02BA_CPU_INR_TC2 4 /* TURBOchannel slot #2 */
#define KN02BA_CPU_INR_TC1 3 /* TURBOchannel slot #1 */
#define KN02BA_CPU_INR_TC0 2 /* TURBOchannel slot #0 */
/*
* I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
*/
#define KN02BA_IO_INR_RES_15 15 /* unused */
#define KN02BA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
#define KN02BA_IO_INR_RES_13 13 /* unused */
#define KN02BA_IO_INR_BUS 12 /* memory, I/O bus read/write errors */
#define KN02BA_IO_INR_RES_11 11 /* unused */
#define KN02BA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
#define KN02BA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
#define KN02BA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
#define KN02BA_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
#define KN02BA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
#define KN02BA_IO_INR_RTC 5 /* DS1287 RTC */
#define KN02BA_IO_INR_PSU 4 /* power supply unit warning */
#define KN02BA_IO_INR_RES_3 3 /* unused */
#define KN02BA_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */
#define KN02BA_IO_INR_PBNC 1 /* ~HALT button debouncer */
#define KN02BA_IO_INR_PBNO 0 /* HALT button debouncer */
/*
* Memory Error Register bits.
*/
#define KN02BA_MER_RES_27 (1<<27) /* unused */
/*
* Memory Size Register bits.
*/
#define KN02BA_MSR_RES_17 (0x3ff<<17) /* unused */
/*
* I/O ASIC System Support Register bits.
*/
#define KN02BA_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */
#define KN02BA_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */
#define KN02BA_IO_SSR_RES_12 (1<<12) /* unused */
#define KN02BA_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */
#endif /* __ASM_MIPS_DEC_KN02BA_H */

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/*
* include/asm-mips/dec/kn02ca.h
*
* Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_KN02CA_H
#define __ASM_MIPS_DEC_KN02CA_H
#include <asm/dec/kn02xa.h> /* For common definitions. */
/*
* CPU interrupt bits.
*/
#define KN02CA_CPU_INR_HALT 6 /* HALT from ACCESS.Bus */
#define KN02CA_CPU_INR_CASCADE 5 /* I/O ASIC cascade */
#define KN02CA_CPU_INR_BUS 4 /* memory, I/O bus read/write errors */
#define KN02CA_CPU_INR_RTC 3 /* DS1287 RTC */
#define KN02CA_CPU_INR_TIMER 2 /* ARC periodic timer */
/*
* I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
*/
#define KN02CA_IO_INR_FLOPPY 15 /* 82077 FDC */
#define KN02CA_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
#define KN02CA_IO_INR_POWERON 13 /* (*) ACCESS.Bus/power-on reset */
#define KN02CA_IO_INR_TC0 12 /* TURBOchannel slot #0 */
#define KN02CA_IO_INR_TIMER 12 /* ARC periodic timer (?) */
#define KN02CA_IO_INR_ISDN 11 /* Am79C30A ISDN */
#define KN02CA_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
#define KN02CA_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
#define KN02CA_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
#define KN02CA_IO_INR_HDFLOPPY 7 /* (*) HD (1.44MB) floppy status */
#define KN02CA_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
#define KN02CA_IO_INR_TC1 5 /* TURBOchannel slot #1 */
#define KN02CA_IO_INR_XDFLOPPY 4 /* (*) XD (2.88MB) floppy status */
#define KN02CA_IO_INR_VIDEO 3 /* framebuffer */
#define KN02CA_IO_INR_XVIDEO 2 /* ~framebuffer */
#define KN02CA_IO_INR_AB_XMIT 1 /* ACCESS.bus transmit */
#define KN02CA_IO_INR_AB_RECV 0 /* ACCESS.bus receive */
/*
* Memory Error Register bits.
*/
#define KN02CA_MER_INTR (1<<27) /* ARC IRQ status & ack */
/*
* Memory Size Register bits.
*/
#define KN02CA_MSR_INTREN (1<<26) /* ARC periodic IRQ enable */
#define KN02CA_MSR_MS10EN (1<<25) /* 10/1ms IRQ period select */
#define KN02CA_MSR_PFORCE (0xf<<21) /* byte lane error force */
#define KN02CA_MSR_MABEN (1<<20) /* A side VFB address enable */
#define KN02CA_MSR_LASTBANK (0x7<<17) /* onboard RAM bank # */
/*
* I/O ASIC System Support Register bits.
*/
#define KN03CA_IO_SSR_RES_14 (1<<14) /* unused */
#define KN03CA_IO_SSR_RES_13 (1<<13) /* unused */
#define KN03CA_IO_SSR_ISDN_RST (1<<12) /* ~ISDN (Am79C30A) reset */
#define KN03CA_IO_SSR_FLOPPY_RST (1<<7) /* ~FDC (82077) reset */
#define KN03CA_IO_SSR_VIDEO_RST (1<<6) /* ~framebuffer reset */
#define KN03CA_IO_SSR_AB_RST (1<<5) /* ACCESS.bus reset */
#define KN03CA_IO_SSR_RES_4 (1<<4) /* unused */
#define KN03CA_IO_SSR_RES_3 (1<<4) /* unused */
#define KN03CA_IO_SSR_RES_2 (1<<2) /* unused */
#define KN03CA_IO_SSR_RES_1 (1<<1) /* unused */
#define KN03CA_IO_SSR_LED (1<<0) /* power LED */
#endif /* __ASM_MIPS_DEC_KN02CA_H */

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/*
* Hardware info common to DECstation 5000/1xx systems (otherwise
* known as 3min or kn02ba) and Personal DECstations 5000/xx ones
* (otherwise known as maxine or kn02ca).
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
* are by courtesy of Chris Fraser.
* Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
*
* These are addresses which have to be known early in the boot process.
* For other addresses refer to tc.h, ioasic_addrs.h and friends.
*/
#ifndef __ASM_MIPS_DEC_KN02XA_H
#define __ASM_MIPS_DEC_KN02XA_H
#include <asm/addrspace.h>
#include <asm/dec/ioasic_addrs.h>
#define KN02XA_SLOT_BASE KSEG1ADDR(0x1c000000)
/*
* Some port addresses...
*/
#define KN02XA_IOASIC_BASE (KN02XA_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
#define KN02XA_RTC_BASE (KN02XA_SLOT_BASE + IOASIC_TOY) /* RTC */
/*
* Memory control ASIC registers.
*/
#define KN02XA_MER KSEG1ADDR(0x0c400000) /* memory error register */
#define KN02XA_MSR KSEG1ADDR(0x0c800000) /* memory size register */
/*
* CPU control ASIC registers.
*/
#define KN02XA_MEM_CONF KSEG1ADDR(0x0e000000) /* write timeout config */
#define KN02XA_EAR KSEG1ADDR(0x0e000004) /* error address register */
#define KN02XA_BOOT0 KSEG1ADDR(0x0e000008) /* boot 0 register */
#define KN02XA_MEM_INTR KSEG1ADDR(0x0e00000c) /* write err IRQ stat & ack */
/*
* Memory Error Register bits, common definitions.
* The rest is defined in system-specific headers.
*/
#define KN02XA_MER_RES_28 (0xf<<28) /* unused */
#define KN02XA_MER_RES_17 (0x3ff<<17) /* unused */
#define KN02XA_MER_PAGERR (1<<16) /* 2k page boundary error */
#define KN02XA_MER_TRANSERR (1<<15) /* transfer length error */
#define KN02XA_MER_PARDIS (1<<14) /* parity error disable */
#define KN02XA_MER_RES_12 (0x3<<12) /* unused */
#define KN02XA_MER_BYTERR (0xf<<8) /* byte lane error bitmask */
#define KN02XA_MER_RES_0 (0xff<<0) /* unused */
/*
* Memory Size Register bits, common definitions.
* The rest is defined in system-specific headers.
*/
#define KN02XA_MSR_RES_27 (0x1f<<27) /* unused */
#define KN02XA_MSR_RES_14 (0x7<<14) /* unused */
#define KN02XA_MSR_SIZE (1<<13) /* 16M/4M stride */
#define KN02XA_MSR_RES_0 (0x1fff<<0) /* unused */
/*
* Error Address Register bits.
*/
#define KN02XA_EAR_RES_29 (0x7<<29) /* unused */
#define KN02XA_EAR_ADDRESS (0x7ffffff<<2) /* address involved */
#define KN02XA_EAR_RES_0 (0x3<<0) /* unused */
#endif /* __ASM_MIPS_DEC_KN02XA_H */

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/*
* Hardware info about DECstation 5000/2x0 systems (otherwise known as
* 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which
* differ mechanically but are otherwise identical (both are known as
* KN03).
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
* are by courtesy of Chris Fraser.
* Copyright (C) 2000, 2002, 2003 Maciej W. Rozycki
*/
#ifndef __ASM_MIPS_DEC_KN03_H
#define __ASM_MIPS_DEC_KN03_H
#include <asm/addrspace.h>
#include <asm/dec/ecc.h>
#include <asm/dec/ioasic_addrs.h>
#define KN03_SLOT_BASE KSEG1ADDR(0x1f800000)
/*
* Some port addresses...
*/
#define KN03_IOASIC_BASE (KN03_SLOT_BASE + IOASIC_IOCTL) /* I/O ASIC */
#define KN03_RTC_BASE (KN03_SLOT_BASE + IOASIC_TOY) /* RTC */
#define KN03_MCR_BASE (KN03_SLOT_BASE + IOASIC_MCR) /* MCR */
/*
* CPU interrupt bits.
*/
#define KN03_CPU_INR_HALT 6 /* HALT button */
#define KN03_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
#define KN03_CPU_INR_RES_4 4 /* unused */
#define KN03_CPU_INR_RTC 3 /* DS1287 RTC */
#define KN03_CPU_INR_CASCADE 2 /* I/O ASIC cascade */
/*
* I/O ASIC interrupt bits. Star marks denote non-IRQ status bits.
*/
#define KN03_IO_INR_3MAXP 15 /* (*) 3max+/bigmax ID */
#define KN03_IO_INR_NVRAM 14 /* (*) NVRAM clear jumper */
#define KN03_IO_INR_TC2 13 /* TURBOchannel slot #2 */
#define KN03_IO_INR_TC1 12 /* TURBOchannel slot #1 */
#define KN03_IO_INR_TC0 11 /* TURBOchannel slot #0 */
#define KN03_IO_INR_NRMOD 10 /* (*) NRMOD manufacturing jumper */
#define KN03_IO_INR_ASC 9 /* ASC (NCR53C94) SCSI */
#define KN03_IO_INR_LANCE 8 /* LANCE (Am7990) Ethernet */
#define KN03_IO_INR_SCC1 7 /* SCC (Z85C30) serial #1 */
#define KN03_IO_INR_SCC0 6 /* SCC (Z85C30) serial #0 */
#define KN03_IO_INR_RTC 5 /* DS1287 RTC */
#define KN03_IO_INR_PSU 4 /* power supply unit warning */
#define KN03_IO_INR_RES_3 3 /* unused */
#define KN03_IO_INR_ASC_DATA 2 /* SCSI data ready (for PIO) */
#define KN03_IO_INR_PBNC 1 /* ~HALT button debouncer */
#define KN03_IO_INR_PBNO 0 /* HALT button debouncer */
/*
* Memory Control Register bits.
*/
#define KN03_MCR_RES_16 (0xffff<<16) /* unused */
#define KN03_MCR_DIAGCHK (1<<15) /* diagn/norml ECC reads */
#define KN03_MCR_DIAGGEN (1<<14) /* diagn/norml ECC writes */
#define KN03_MCR_CORRECT (1<<13) /* ECC correct/check */
#define KN03_MCR_RES_11 (0x3<<12) /* unused */
#define KN03_MCR_BNK32M (1<<10) /* 32M/8M stride */
#define KN03_MCR_RES_7 (0x7<<7) /* unused */
#define KN03_MCR_CHECK (0x7f<<0) /* diagnostic check bits */
/*
* I/O ASIC System Support Register bits.
*/
#define KN03_IO_SSR_TXDIS1 (1<<14) /* SCC1 transmit disable */
#define KN03_IO_SSR_TXDIS0 (1<<13) /* SCC0 transmit disable */
#define KN03_IO_SSR_RES_12 (1<<12) /* unused */
#define KN03_IO_SSR_LEDS (0xff<<0) /* ~diagnostic LEDs */
#endif /* __ASM_MIPS_DEC_KN03_H */

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/*
* include/asm-mips/dec/kn05.h
*
* DECstation 5000/260 (4max+ or KN05) and DECsystem 5900/260
* definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* WARNING! All this information is pure guesswork based on the
* ROM. It is provided here in hope it will give someone some
* food for thought. No documentation for the KN05 module has
* been located so far.
*/
#ifndef __ASM_MIPS_DEC_KN05_H
#define __ASM_MIPS_DEC_KN05_H
#include <asm/dec/ioasic_addrs.h>
/*
* The oncard MB (Memory Buffer) ASIC provides an additional address
* decoder. Certain address ranges within the "high" 16 slots are
* passed to the I/O ASIC's decoder like with the KN03. Others are
* handled locally. "Low" slots are always passed.
*/
#define KN05_MB_ROM (16*IOASIC_SLOT_SIZE) /* KN05 card ROM */
#define KN05_IOCTL (17*IOASIC_SLOT_SIZE) /* I/O ASIC */
#define KN05_ESAR (18*IOASIC_SLOT_SIZE) /* LANCE MAC address chip */
#define KN05_LANCE (19*IOASIC_SLOT_SIZE) /* LANCE Ethernet */
#define KN05_MB_INT (20*IOASIC_SLOT_SIZE) /* MB interrupt register */
#define KN05_MB_EA (21*IOASIC_SLOT_SIZE) /* MB error address? */
#define KN05_MB_EC (22*IOASIC_SLOT_SIZE) /* MB error ??? */
#define KN05_MB_CSR (23*IOASIC_SLOT_SIZE) /* MB control & status */
#define KN05_RES_24 (24*IOASIC_SLOT_SIZE) /* unused? */
#define KN05_RES_25 (25*IOASIC_SLOT_SIZE) /* unused? */
#define KN05_RES_26 (26*IOASIC_SLOT_SIZE) /* unused? */
#define KN05_RES_27 (27*IOASIC_SLOT_SIZE) /* unused? */
#define KN05_SCSI (28*IOASIC_SLOT_SIZE) /* ASC SCSI */
#define KN05_RES_29 (29*IOASIC_SLOT_SIZE) /* unused? */
#define KN05_RES_30 (30*IOASIC_SLOT_SIZE) /* unused? */
#define KN05_RES_31 (31*IOASIC_SLOT_SIZE) /* unused? */
/*
* Bits for the MB interrupt register.
* The register appears read-only.
*/
#define KN05_MB_INT_TC (1<<0) /* TURBOchannel? */
#define KN05_MB_INT_RTC (1<<1) /* RTC? */
#define KN05_MB_INT_MT (1<<3) /* ??? */
/*
* Bits for the MB control & status register.
* Set to 0x00bf8001 on my system by the ROM.
*/
#define KN05_MB_CSR_PF (1<<0) /* PreFetching enable? */
#define KN05_MB_CSR_F (1<<1) /* ??? */
#define KN05_MB_CSR_ECC (0xff<<2) /* ??? */
#define KN05_MB_CSR_OD (1<<10) /* ??? */
#define KN05_MB_CSR_CP (1<<11) /* ??? */
#define KN05_MB_CSR_UNC (1<<12) /* ??? */
#define KN05_MB_CSR_IM (1<<13) /* ??? */
#define KN05_MB_CSR_NC (1<<14) /* ??? */
#define KN05_MB_CSR_EE (1<<15) /* (bus) Exception Enable? */
#define KN05_MB_CSR_MSK (0x1f<<16) /* ??? */
#define KN05_MB_CSR_FW (1<<21) /* ??? */
#endif /* __ASM_MIPS_DEC_KN05_H */

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/*
* include/asm-mips/dec/kn230.h
*
* DECsystem 5100 (MIPSmate or KN230) definitions.
*
* Copyright (C) 2002, 2003 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_KN230_H
#define __ASM_MIPS_DEC_KN230_H
/*
* CPU interrupt bits.
*/
#define KN230_CPU_INR_HALT 6 /* HALT button */
#define KN230_CPU_INR_BUS 5 /* memory, I/O bus read/write errors */
#define KN230_CPU_INR_RTC 4 /* DS1287 RTC */
#define KN230_CPU_INR_SII 3 /* SII (DC7061) SCSI */
#define KN230_CPU_INR_LANCE 3 /* LANCE (Am7990) Ethernet */
#define KN230_CPU_INR_DZ11 2 /* DZ11 (DC7085) serial */
#endif /* __ASM_MIPS_DEC_KN230_H */

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/*
* Various machine type macros
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1998, 2000 Harald Koerfgen
*/
#ifndef __ASM_DEC_MACHTYPE_H
#define __ASM_DEC_MACHTYPE_H
#include <asm/bootinfo.h>
#define TURBOCHANNEL (mips_machtype == MACH_DS5000_200 || \
mips_machtype == MACH_DS5000_1XX || \
mips_machtype == MACH_DS5000_XX || \
mips_machtype == MACH_DS5000_2X0 || \
mips_machtype == MACH_DS5900)
#define IOASIC (mips_machtype == MACH_DS5000_1XX || \
mips_machtype == MACH_DS5000_XX || \
mips_machtype == MACH_DS5000_2X0 || \
mips_machtype == MACH_DS5900)
#endif

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/*
* include/asm-mips/dec/prom.h
*
* DECstation PROM interface.
*
* Copyright (C) 2002 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*
* Based on arch/mips/dec/prom/prom.h by the Anonymous.
*/
#ifndef _ASM_DEC_PROM_H
#define _ASM_DEC_PROM_H
#include <linux/config.h>
#include <linux/types.h>
#include <asm/addrspace.h>
/*
* PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
* Many of these will work for MIPSen as well!
*/
#define VEC_RESET (u64 *)KSEG1ADDR(0x1fc00000)
/* Prom base address */
#define PMAX_PROM_ENTRY(x) (VEC_RESET + (x)) /* Prom jump table */
#define PMAX_PROM_HALT PMAX_PROM_ENTRY(2) /* valid on MIPSen */
#define PMAX_PROM_AUTOBOOT PMAX_PROM_ENTRY(5) /* valid on MIPSen */
#define PMAX_PROM_OPEN PMAX_PROM_ENTRY(6)
#define PMAX_PROM_READ PMAX_PROM_ENTRY(7)
#define PMAX_PROM_CLOSE PMAX_PROM_ENTRY(10)
#define PMAX_PROM_LSEEK PMAX_PROM_ENTRY(11)
#define PMAX_PROM_GETCHAR PMAX_PROM_ENTRY(12)
#define PMAX_PROM_PUTCHAR PMAX_PROM_ENTRY(13) /* 12 on MIPSen */
#define PMAX_PROM_GETS PMAX_PROM_ENTRY(15)
#define PMAX_PROM_PRINTF PMAX_PROM_ENTRY(17)
#define PMAX_PROM_GETENV PMAX_PROM_ENTRY(33) /* valid on MIPSen */
/*
* Magic number indicating REX PROM available on DECstation. Found in
* register a2 on transfer of control to program from PROM.
*/
#define REX_PROM_MAGIC 0x30464354
#ifdef CONFIG_MIPS64
#define prom_is_rex(magic) 1 /* KN04 and KN05 are REX PROMs. */
#else /* !CONFIG_MIPS64 */
#define prom_is_rex(magic) ((magic) == REX_PROM_MAGIC)
#endif /* !CONFIG_MIPS64 */
/*
* 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and
* DS5000/2x0.
*/
#define REX_PROM_GETBITMAP 0x84/4 /* get mem bitmap */
#define REX_PROM_GETCHAR 0x24/4 /* getch() */
#define REX_PROM_GETENV 0x64/4 /* get env. variable */
#define REX_PROM_GETSYSID 0x80/4 /* get system id */
#define REX_PROM_GETTCINFO 0xa4/4
#define REX_PROM_PRINTF 0x30/4 /* printf() */
#define REX_PROM_SLOTADDR 0x6c/4 /* slotaddr */
#define REX_PROM_BOOTINIT 0x54/4 /* open() */
#define REX_PROM_BOOTREAD 0x58/4 /* read() */
#define REX_PROM_CLEARCACHE 0x7c/4
/*
* Used by rex_getbitmap().
*/
typedef struct {
int pagesize;
unsigned char bitmap[0];
} memmap;
/*
* Function pointers as read from a PROM's callback vector.
*/
extern int (*__rex_bootinit)(void);
extern int (*__rex_bootread)(void);
extern int (*__rex_getbitmap)(memmap *);
extern unsigned long *(*__rex_slot_address)(int);
extern void *(*__rex_gettcinfo)(void);
extern int (*__rex_getsysid)(void);
extern void (*__rex_clear_cache)(void);
extern int (*__prom_getchar)(void);
extern char *(*__prom_getenv)(char *);
extern int (*__prom_printf)(char *, ...);
extern int (*__pmax_open)(char*, int);
extern int (*__pmax_lseek)(int, long, int);
extern int (*__pmax_read)(int, void *, int);
extern int (*__pmax_close)(int);
#ifdef CONFIG_MIPS64
/*
* On MIPS64 we have to call PROM functions via a helper
* dispatcher to accomodate ABI incompatibilities.
*/
#define __DEC_PROM_O32 __attribute__((alias("call_o32")))
int _rex_bootinit(int (*)(void)) __DEC_PROM_O32;
int _rex_bootread(int (*)(void)) __DEC_PROM_O32;
int _rex_getbitmap(int (*)(memmap *), memmap *) __DEC_PROM_O32;
unsigned long *_rex_slot_address(unsigned long *(*)(int), int) __DEC_PROM_O32;
void *_rex_gettcinfo(void *(*)(void)) __DEC_PROM_O32;
int _rex_getsysid(int (*)(void)) __DEC_PROM_O32;
void _rex_clear_cache(void (*)(void)) __DEC_PROM_O32;
int _prom_getchar(int (*)(void)) __DEC_PROM_O32;
char *_prom_getenv(char *(*)(char *), char *) __DEC_PROM_O32;
int _prom_printf(int (*)(char *, ...), char *, ...) __DEC_PROM_O32;
#define rex_bootinit() _rex_bootinit(__rex_bootinit)
#define rex_bootread() _rex_bootread(__rex_bootread)
#define rex_getbitmap(x) _rex_getbitmap(__rex_getbitmap, x)
#define rex_slot_address(x) _rex_slot_address(__rex_slot_address, x)
#define rex_gettcinfo() _rex_gettcinfo(__rex_gettcinfo)
#define rex_getsysid() _rex_getsysid(__rex_getsysid)
#define rex_clear_cache() _rex_clear_cache(__rex_clear_cache)
#define prom_getchar() _prom_getchar(__prom_getchar)
#define prom_getenv(x) _prom_getenv(__prom_getenv, x)
#define prom_printf(x...) _prom_printf(__prom_printf, x)
#else /* !CONFIG_MIPS64 */
/*
* On plain MIPS we just call PROM functions directly.
*/
#define rex_bootinit __rex_bootinit
#define rex_bootread __rex_bootread
#define rex_getbitmap __rex_getbitmap
#define rex_slot_address __rex_slot_address
#define rex_gettcinfo __rex_gettcinfo
#define rex_getsysid __rex_getsysid
#define rex_clear_cache __rex_clear_cache
#define prom_getchar __prom_getchar
#define prom_getenv __prom_getenv
#define prom_printf __prom_printf
#define pmax_open __pmax_open
#define pmax_lseek __pmax_lseek
#define pmax_read __pmax_read
#define pmax_close __pmax_close
#endif /* !CONFIG_MIPS64 */
extern void prom_meminit(u32);
extern void prom_identify_arch(u32);
extern void prom_init_cmdline(s32, s32 *, u32);
extern void register_prom_console(void);
extern void unregister_prom_console(void);
#endif /* _ASM_DEC_PROM_H */

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/*
* include/asm-mips/dec/serial.h
*
* Definitions common to all DECstation serial devices.
*
* Copyright (C) 2004 Maciej W. Rozycki
*
* Based on bits extracted from drivers/tc/zs.h for which
* the following copyrights apply:
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
* Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
* Copyright (C) Harald Koerfgen
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_MIPS_DEC_SERIAL_H
#define __ASM_MIPS_DEC_SERIAL_H
struct dec_serial_hook {
int (*init_channel)(void *handle);
void (*init_info)(void *handle);
void (*rx_char)(unsigned char ch, unsigned char fl);
int (*poll_rx_char)(void *handle);
int (*poll_tx_char)(void *handle, unsigned char ch);
unsigned int cflags;
};
extern int register_dec_serial_hook(unsigned int channel,
struct dec_serial_hook *hook);
extern int unregister_dec_serial_hook(unsigned int channel);
#endif /* __ASM_MIPS_DEC_SERIAL_H */

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/*
* Interface to the TURBOchannel related routines
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 1998 Harald Koerfgen
*/
#ifndef ASM_TC_H
#define ASM_TC_H
extern unsigned long system_base;
/*
* Search for a TURBOchannel Option Module
* with a certain name. Returns slot number
* of the first card not in use or -ENODEV
* if none found.
*/
extern int search_tc_card(const char *);
/*
* Marks the card in slot as used
*/
extern void claim_tc_card(int);
/*
* Marks the card in slot as free
*/
extern void release_tc_card(int);
/*
* Return base address of card in slot
*/
extern unsigned long get_tc_base_addr(int);
/*
* Return interrupt number of slot
*/
extern unsigned long get_tc_irq_nr(int);
/*
* Return TURBOchannel clock frequency in hz
*/
extern unsigned long get_tc_speed(void);
#endif

47
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/*
* Various TURBOchannel related stuff
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Information obtained through the get_tcinfo prom call
* created from:
*
* TURBOchannel Firmware Specification
*
* EK-TCAAD-FS-004
* from Digital Equipment Corporation
*
* Copyright (c) 1998 Harald Koerfgen
*/
typedef struct {
int revision;
int clk_period;
int slot_size;
int io_timeout;
int dma_range;
int max_dma_burst;
int parity;
int reserved[4];
} tcinfo;
#define MAX_SLOT 7
typedef struct {
unsigned long base_addr;
unsigned char name[9];
unsigned char vendor[9];
unsigned char firmware[9];
int interrupt;
int flags;
} slot_info;
/*
* Values for flags
*/
#define FREE 1<<0
#define IN_USE 1<<1

39
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Offsets for the ROM header locations for
* TURBOchannel cards
*
* created from:
*
* TURBOchannel Firmware Specification
*
* EK-TCAAD-FS-004
* from Digital Equipment Corporation
*
* Jan.1998 Harald Koerfgen
*/
#ifndef __ASM_DEC_TCMODULE_H
#define __ASM_DEC_TCMODULE_H
#define OLDCARD 0x3c0000
#define NEWCARD 0x000000
#define TC_ROM_WIDTH 0x3e0
#define TC_ROM_STRIDE 0x3e4
#define TC_ROM_SIZE 0x3e8
#define TC_SLOT_SIZE 0x3ec
#define TC_PATTERN0 0x3f0
#define TC_PATTERN1 0x3f4
#define TC_PATTERN2 0x3f8
#define TC_PATTERN3 0x3fc
#define TC_FIRM_VER 0x400
#define TC_VENDOR 0x420
#define TC_MODULE 0x440
#define TC_FIRM_TYPE 0x460
#define TC_FLAGS 0x470
#define TC_ROM_OBJECTS 0x480
#endif /* __ASM_DEC_TCMODULE_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 by Waldorf Electronics
* Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
#ifndef _ASM_DELAY_H
#define _ASM_DELAY_H
#include <linux/config.h>
#include <linux/param.h>
#include <asm/compiler.h>
extern unsigned long loops_per_jiffy;
static inline void __delay(unsigned long loops)
{
if (sizeof(long) == 4)
__asm__ __volatile__ (
".set\tnoreorder\n"
"1:\tbnez\t%0,1b\n\t"
"subu\t%0,1\n\t"
".set\treorder"
: "=r" (loops)
: "0" (loops));
else if (sizeof(long) == 8)
__asm__ __volatile__ (
".set\tnoreorder\n"
"1:\tbnez\t%0,1b\n\t"
"dsubu\t%0,1\n\t"
".set\treorder"
:"=r" (loops)
:"0" (loops));
}
/*
* Division by multiplication: you don't have to worry about
* loss of precision.
*
* Use only for very small delays ( < 1 msec). Should probably use a
* lookup table, really, as the multiplications take much too long with
* short delays. This is a "reasonable" implementation, though (and the
* first constant multiplications gets optimized away if the delay is
* a constant)
*/
static inline void __udelay(unsigned long usecs, unsigned long lpj)
{
unsigned long lo;
/*
* The common rates of 1000 and 128 are rounded wrongly by the
* catchall case for 64-bit. Excessive precission? Probably ...
*/
#if defined(CONFIG_MIPS64) && (HZ == 128)
usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */
#elif defined(CONFIG_MIPS64) && (HZ == 1000)
usecs *= 0x004189374BC6A7f0UL; /* 2**64 / (1000000 / HZ) */
#elif defined(CONFIG_MIPS64)
usecs *= (0x8000000000000000UL / (500000 / HZ));
#else /* 32-bit junk follows here */
usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) +
0x80000000ULL) >> 32);
#endif
if (sizeof(long) == 4)
__asm__("multu\t%2, %3"
: "=h" (usecs), "=l" (lo)
: "r" (usecs), "r" (lpj)
: GCC_REG_ACCUM);
else if (sizeof(long) == 8)
__asm__("dmultu\t%2, %3"
: "=h" (usecs), "=l" (lo)
: "r" (usecs), "r" (lpj)
: GCC_REG_ACCUM);
__delay(usecs);
}
#ifdef CONFIG_SMP
#define __udelay_val cpu_data[smp_processor_id()].udelay_val
#else
#define __udelay_val loops_per_jiffy
#endif
#define udelay(usecs) __udelay((usecs),__udelay_val)
#endif /* _ASM_DELAY_H */

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/*
* Copyright (C) 2000, 2004 Maciej W. Rozycki
* Copyright (C) 2003 Ralf Baechle
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef _ASM_DIV64_H
#define _ASM_DIV64_H
#if (_MIPS_SZLONG == 32)
#include <asm/compiler.h>
/*
* No traps on overflows for any of these...
*/
#define do_div64_32(res, high, low, base) ({ \
unsigned long __quot, __mod; \
unsigned long __cf, __tmp, __tmp2, __i; \
\
__asm__(".set push\n\t" \
".set noat\n\t" \
".set noreorder\n\t" \
"move %2, $0\n\t" \
"move %3, $0\n\t" \
"b 1f\n\t" \
" li %4, 0x21\n" \
"0:\n\t" \
"sll $1, %0, 0x1\n\t" \
"srl %3, %0, 0x1f\n\t" \
"or %0, $1, %5\n\t" \
"sll %1, %1, 0x1\n\t" \
"sll %2, %2, 0x1\n" \
"1:\n\t" \
"bnez %3, 2f\n\t" \
" sltu %5, %0, %z6\n\t" \
"bnez %5, 3f\n" \
"2:\n\t" \
" addiu %4, %4, -1\n\t" \
"subu %0, %0, %z6\n\t" \
"addiu %2, %2, 1\n" \
"3:\n\t" \
"bnez %4, 0b\n\t" \
" srl %5, %1, 0x1f\n\t" \
".set pop" \
: "=&r" (__mod), "=&r" (__tmp), "=&r" (__quot), "=&r" (__cf), \
"=&r" (__i), "=&r" (__tmp2) \
: "Jr" (base), "0" (high), "1" (low)); \
\
(res) = __quot; \
__mod; })
#define do_div(n, base) ({ \
unsigned long long __quot; \
unsigned long __mod; \
unsigned long long __div; \
unsigned long __upper, __low, __high, __base; \
\
__div = (n); \
__base = (base); \
\
__high = __div >> 32; \
__low = __div; \
__upper = __high; \
\
if (__high) \
__asm__("divu $0, %z2, %z3" \
: "=h" (__upper), "=l" (__high) \
: "Jr" (__high), "Jr" (__base) \
: GCC_REG_ACCUM); \
\
__mod = do_div64_32(__low, __upper, __low, __base); \
\
__quot = __high; \
__quot = __quot << 32 | __low; \
(n) = __quot; \
__mod; })
#endif /* (_MIPS_SZLONG == 32) */
#if (_MIPS_SZLONG == 64)
/*
* Don't use this one in new code
*/
#define do_div64_32(res, high, low, base) ({ \
unsigned int __quot, __mod; \
unsigned long __div; \
unsigned int __low, __high, __base; \
\
__high = (high); \
__low = (low); \
__div = __high; \
__div = __div << 32 | __low; \
__base = (base); \
\
__mod = __div % __base; \
__div = __div / __base; \
\
__quot = __div; \
(res) = __quot; \
__mod; })
/*
* Hey, we're already 64-bit, no
* need to play games..
*/
#define do_div(n, base) ({ \
unsigned long __quot; \
unsigned int __mod; \
unsigned long __div; \
unsigned int __base; \
\
__div = (n); \
__base = (base); \
\
__mod = __div % __base; \
__quot = __div / __base; \
\
(n) = __quot; \
__mod; })
#endif /* (_MIPS_SZLONG == 64) */
#endif /* _ASM_DIV64_H */

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#ifndef _ASM_DMA_MAPPING_H
#define _ASM_DMA_MAPPING_H
#include <asm/scatterlist.h>
#include <asm/cache.h>
void *dma_alloc_noncoherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag);
void dma_free_noncoherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle);
void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, int flag);
void dma_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle);
extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
enum dma_data_direction direction);
extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
size_t size, enum dma_data_direction direction);
extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
enum dma_data_direction direction);
extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
unsigned long offset, size_t size, enum dma_data_direction direction);
extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
size_t size, enum dma_data_direction direction);
extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
int nhwentries, enum dma_data_direction direction);
extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
size_t size, enum dma_data_direction direction);
extern void dma_sync_single_for_device(struct device *dev,
dma_addr_t dma_handle, size_t size, enum dma_data_direction direction);
extern void dma_sync_single_range_for_cpu(struct device *dev,
dma_addr_t dma_handle, unsigned long offset, size_t size,
enum dma_data_direction direction);
extern void dma_sync_single_range_for_device(struct device *dev,
dma_addr_t dma_handle, unsigned long offset, size_t size,
enum dma_data_direction direction);
extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
int nelems, enum dma_data_direction direction);
extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
int nelems, enum dma_data_direction direction);
extern int dma_mapping_error(dma_addr_t dma_addr);
extern int dma_supported(struct device *dev, u64 mask);
static inline int
dma_set_mask(struct device *dev, u64 mask)
{
if(!dev->dma_mask || !dma_supported(dev, mask))
return -EIO;
*dev->dma_mask = mask;
return 0;
}
static inline int
dma_get_cache_alignment(void)
{
/* XXX Largest on any MIPS */
return 128;
}
extern int dma_is_consistent(dma_addr_t dma_addr);
extern void dma_cache_sync(void *vaddr, size_t size,
enum dma_data_direction direction);
#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
dma_addr_t device_addr, size_t size, int flags);
extern void dma_release_declared_memory(struct device *dev);
extern void * dma_mark_declared_memory_occupied(struct device *dev,
dma_addr_t device_addr, size_t size);
#endif /* _ASM_DMA_MAPPING_H */

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/*
* linux/include/asm/dma.h: Defines for using and allocating dma channels.
* Written by Hennus Bergman, 1992.
* High DMA channel support & info by Hannu Savolainen
* and John Boyd, Nov. 1992.
*
* NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
* and can only be used for expansion cards. Onboard DMA controllers, such
* as the R4030 on Jazz boards behave totally different!
*/
#ifndef _ASM_DMA_H
#define _ASM_DMA_H
#include <linux/config.h>
#include <asm/io.h> /* need byte IO */
#include <linux/spinlock.h> /* And spinlocks */
#include <linux/delay.h>
#include <asm/system.h>
#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
#define dma_outb outb_p
#else
#define dma_outb outb
#endif
#define dma_inb inb
/*
* NOTES about DMA transfers:
*
* controller 1: channels 0-3, byte operations, ports 00-1F
* controller 2: channels 4-7, word operations, ports C0-DF
*
* - ALL registers are 8 bits only, regardless of transfer size
* - channel 4 is not used - cascades 1 into 2.
* - channels 0-3 are byte - addresses/counts are for physical bytes
* - channels 5-7 are word - addresses/counts are for physical words
* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
* - transfer count loaded to registers is 1 less than actual count
* - controller 2 offsets are all even (2x offsets for controller 1)
* - page registers for 5-7 don't use data bit 0, represent 128K pages
* - page registers for 0-3 use bit 0, represent 64K pages
*
* DMA transfers are limited to the lower 16MB of _physical_ memory.
* Note that addresses loaded into registers must be _physical_ addresses,
* not logical addresses (which may differ if paging is active).
*
* Address mapping for channels 0-3:
*
* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* P7 ... P0 A7 ... A0 A7 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Address mapping for channels 5-7:
*
* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
* | ... | \ \ ... \ \ \ ... \ \
* | ... | \ \ ... \ \ \ ... \ (not used)
* | ... | \ \ ... \ \ \ ... \
* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
* the hardware level, so odd-byte transfers aren't possible).
*
* Transfer count (_not # bytes_) is limited to 64K, represented as actual
* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
* and up to 128K bytes may be transferred on channels 5-7 in one operation.
*
*/
#define MAX_DMA_CHANNELS 8
/*
* The maximum address in KSEG0 that we can perform a DMA transfer to on this
* platform. This describes only the PC style part of the DMA logic like on
* Deskstations or Acer PICA but not the much more versatile DMA logic used
* for the local devices on Acer PICA or Magnums.
*/
#ifdef CONFIG_SGI_IP22
/* Horrible hack to have a correct DMA window on IP22 */
#include <asm/sgi/mc.h>
#define MAX_DMA_ADDRESS (PAGE_OFFSET + SGIMC_SEG0_BADDR + 0x01000000)
#else
#define MAX_DMA_ADDRESS (PAGE_OFFSET + 0x01000000)
#endif
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
/* DMA controller registers */
#define DMA1_CMD_REG 0x08 /* command register (w) */
#define DMA1_STAT_REG 0x08 /* status register (r) */
#define DMA1_REQ_REG 0x09 /* request register (w) */
#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
#define DMA1_MODE_REG 0x0B /* mode register (w) */
#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
#define DMA2_CMD_REG 0xD0 /* command register (w) */
#define DMA2_STAT_REG 0xD0 /* status register (r) */
#define DMA2_REQ_REG 0xD2 /* request register (w) */
#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
#define DMA2_MODE_REG 0xD6 /* mode register (w) */
#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
#define DMA_ADDR_0 0x00 /* DMA address registers */
#define DMA_ADDR_1 0x02
#define DMA_ADDR_2 0x04
#define DMA_ADDR_3 0x06
#define DMA_ADDR_4 0xC0
#define DMA_ADDR_5 0xC4
#define DMA_ADDR_6 0xC8
#define DMA_ADDR_7 0xCC
#define DMA_CNT_0 0x01 /* DMA count registers */
#define DMA_CNT_1 0x03
#define DMA_CNT_2 0x05
#define DMA_CNT_3 0x07
#define DMA_CNT_4 0xC2
#define DMA_CNT_5 0xC6
#define DMA_CNT_6 0xCA
#define DMA_CNT_7 0xCE
#define DMA_PAGE_0 0x87 /* DMA page registers */
#define DMA_PAGE_1 0x83
#define DMA_PAGE_2 0x81
#define DMA_PAGE_3 0x82
#define DMA_PAGE_5 0x8B
#define DMA_PAGE_6 0x89
#define DMA_PAGE_7 0x8A
#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
#define DMA_AUTOINIT 0x10
extern spinlock_t dma_spin_lock;
static __inline__ unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(dmanr, DMA1_MASK_REG);
else
dma_outb(dmanr & 3, DMA2_MASK_REG);
}
static __inline__ void disable_dma(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(dmanr | 4, DMA1_MASK_REG);
else
dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
}
/* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while holding the DMA lock ! ---
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
if (dmanr<=3)
dma_outb(0, DMA1_CLEAR_FF_REG);
else
dma_outb(0, DMA2_CLEAR_FF_REG);
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
if (dmanr<=3)
dma_outb(mode | dmanr, DMA1_MODE_REG);
else
dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
}
/* Set only the page register bits of the transfer address.
* This is used for successive transfers when we know the contents of
* the lower 16 bits of the DMA current address register, but a 64k boundary
* may have been crossed.
*/
static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
{
switch(dmanr) {
case 0:
dma_outb(pagenr, DMA_PAGE_0);
break;
case 1:
dma_outb(pagenr, DMA_PAGE_1);
break;
case 2:
dma_outb(pagenr, DMA_PAGE_2);
break;
case 3:
dma_outb(pagenr, DMA_PAGE_3);
break;
case 5:
dma_outb(pagenr & 0xfe, DMA_PAGE_5);
break;
case 6:
dma_outb(pagenr & 0xfe, DMA_PAGE_6);
break;
case 7:
dma_outb(pagenr & 0xfe, DMA_PAGE_7);
break;
}
}
/* Set transfer address & page bits for specific DMA channel.
* Assumes dma flipflop is clear.
*/
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
{
set_dma_page(dmanr, a>>16);
if (dmanr <= 3) {
dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
} else {
dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
}
}
/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
* a specific DMA channel.
* You must ensure the parameters are valid.
* NOTE: from a manual: "the number of transfers is one more
* than the initial word count"! This is taken into account.
* Assumes dma flip-flop is clear.
* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
count--;
if (dmanr <= 3) {
dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
} else {
dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
}
}
/* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* If called before the channel has been used, it may return 1.
* Otherwise, it returns the number of _bytes_ left to transfer.
*
* Assumes DMA flip-flop is clear.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
: ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
/* using short to get 16-bit wrap around */
unsigned short count;
count = 1 + dma_inb(io_port);
count += dma_inb(io_port) << 8;
return (dmanr<=3)? count : (count<<1);
}
/* These are in kernel/dma.c: */
extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
extern void free_dma(unsigned int dmanr); /* release it again */
/* From PCI */
#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy (0)
#endif
#endif /* _ASM_DMA_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Machine dependent access functions for RTC registers.
*
* Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef _ASM_DS1286_H
#define _ASM_DS1286_H
#include <ds1286.h>
#endif /* _ASM_DS1286_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef _ASM_ELF_H
#define _ASM_ELF_H
#include <linux/config.h>
/* ELF header e_flags defines. */
/* MIPS architecture level. */
#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */
#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */
#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */
#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */
#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */
#define EF_MIPS_ARCH_32 0x50000000 /* MIPS32 code. */
#define EF_MIPS_ARCH_64 0x60000000 /* MIPS64 code. */
/* The ABI of a file. */
#define EF_MIPS_ABI_O32 0x00001000 /* O32 ABI. */
#define EF_MIPS_ABI_O64 0x00002000 /* O32 extended for 64 bit. */
#define PT_MIPS_REGINFO 0x70000000
#define PT_MIPS_OPTIONS 0x70000001
/* Flags in the e_flags field of the header */
#define EF_MIPS_NOREORDER 0x00000001
#define EF_MIPS_PIC 0x00000002
#define EF_MIPS_CPIC 0x00000004
#define EF_MIPS_ABI2 0x00000020
#define EF_MIPS_OPTIONS_FIRST 0x00000080
#define EF_MIPS_32BITMODE 0x00000100
#define EF_MIPS_ABI 0x0000f000
#define EF_MIPS_ARCH 0xf0000000
#define DT_MIPS_RLD_VERSION 0x70000001
#define DT_MIPS_TIME_STAMP 0x70000002
#define DT_MIPS_ICHECKSUM 0x70000003
#define DT_MIPS_IVERSION 0x70000004
#define DT_MIPS_FLAGS 0x70000005
#define RHF_NONE 0
#define RHF_HARDWAY 1
#define RHF_NOTPOT 2
#define DT_MIPS_BASE_ADDRESS 0x70000006
#define DT_MIPS_CONFLICT 0x70000008
#define DT_MIPS_LIBLIST 0x70000009
#define DT_MIPS_LOCAL_GOTNO 0x7000000a
#define DT_MIPS_CONFLICTNO 0x7000000b
#define DT_MIPS_LIBLISTNO 0x70000010
#define DT_MIPS_SYMTABNO 0x70000011
#define DT_MIPS_UNREFEXTNO 0x70000012
#define DT_MIPS_GOTSYM 0x70000013
#define DT_MIPS_HIPAGENO 0x70000014
#define DT_MIPS_RLD_MAP 0x70000016
#define R_MIPS_NONE 0
#define R_MIPS_16 1
#define R_MIPS_32 2
#define R_MIPS_REL32 3
#define R_MIPS_26 4
#define R_MIPS_HI16 5
#define R_MIPS_LO16 6
#define R_MIPS_GPREL16 7
#define R_MIPS_LITERAL 8
#define R_MIPS_GOT16 9
#define R_MIPS_PC16 10
#define R_MIPS_CALL16 11
#define R_MIPS_GPREL32 12
/* The remaining relocs are defined on Irix, although they are not
in the MIPS ELF ABI. */
#define R_MIPS_UNUSED1 13
#define R_MIPS_UNUSED2 14
#define R_MIPS_UNUSED3 15
#define R_MIPS_SHIFT5 16
#define R_MIPS_SHIFT6 17
#define R_MIPS_64 18
#define R_MIPS_GOT_DISP 19
#define R_MIPS_GOT_PAGE 20
#define R_MIPS_GOT_OFST 21
/*
* The following two relocation types are specified in the MIPS ABI
* conformance guide version 1.2 but not yet in the psABI.
*/
#define R_MIPS_GOTHI16 22
#define R_MIPS_GOTLO16 23
#define R_MIPS_SUB 24
#define R_MIPS_INSERT_A 25
#define R_MIPS_INSERT_B 26
#define R_MIPS_DELETE 27
#define R_MIPS_HIGHER 28
#define R_MIPS_HIGHEST 29
/*
* The following two relocation types are specified in the MIPS ABI
* conformance guide version 1.2 but not yet in the psABI.
*/
#define R_MIPS_CALLHI16 30
#define R_MIPS_CALLLO16 31
/*
* This range is reserved for vendor specific relocations.
*/
#define R_MIPS_LOVENDOR 100
#define R_MIPS_HIVENDOR 127
#define SHN_MIPS_ACCOMON 0xff00
#define SHT_MIPS_LIST 0x70000000
#define SHT_MIPS_CONFLICT 0x70000002
#define SHT_MIPS_GPTAB 0x70000003
#define SHT_MIPS_UCODE 0x70000004
#define SHF_MIPS_GPREL 0x10000000
#ifndef ELF_ARCH
/* ELF register definitions */
#define ELF_NGREG 45
#define ELF_NFPREG 33
typedef unsigned long elf_greg_t;
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef double elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
#ifdef CONFIG_MIPS32
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(hdr) \
({ \
int __res = 1; \
struct elfhdr *__h = (hdr); \
\
if (__h->e_machine != EM_MIPS) \
__res = 0; \
if (__h->e_ident[EI_CLASS] != ELFCLASS32) \
__res = 0; \
if ((__h->e_flags & EF_MIPS_ABI2) != 0) \
__res = 0; \
if (((__h->e_flags & EF_MIPS_ABI) != 0) && \
((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32)) \
__res = 0; \
\
__res; \
})
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#endif /* CONFIG_MIPS32 */
#ifdef CONFIG_MIPS64
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(hdr) \
({ \
int __res = 1; \
struct elfhdr *__h = (hdr); \
\
if (__h->e_machine != EM_MIPS) \
__res = 0; \
if (__h->e_ident[EI_CLASS] != ELFCLASS64) \
__res = 0; \
\
__res; \
})
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS64
#endif /* CONFIG_MIPS64 */
/*
* These are used to set parameters in the core dumps.
*/
#ifdef __MIPSEB__
#define ELF_DATA ELFDATA2MSB
#elif __MIPSEL__
#define ELF_DATA ELFDATA2LSB
#endif
#define ELF_ARCH EM_MIPS
#endif /* !defined(ELF_ARCH) */
#ifdef __KERNEL__
#ifdef CONFIG_MIPS32
#define SET_PERSONALITY(ex, ibcs2) \
do { \
if (ibcs2) \
set_personality(PER_SVR4); \
set_personality(PER_LINUX); \
} while (0)
#endif /* CONFIG_MIPS32 */
#ifdef CONFIG_MIPS64
#define SET_PERSONALITY(ex, ibcs2) \
do { current->thread.mflags &= ~MF_ABI_MASK; \
if ((ex).e_ident[EI_CLASS] == ELFCLASS32) { \
if ((((ex).e_flags & EF_MIPS_ABI2) != 0) && \
((ex).e_flags & EF_MIPS_ABI) == 0) \
current->thread.mflags |= MF_N32; \
else \
current->thread.mflags |= MF_O32; \
} else \
current->thread.mflags |= MF_N64; \
if (ibcs2) \
set_personality(PER_SVR4); \
else if (current->personality != PER_LINUX32) \
set_personality(PER_LINUX); \
} while (0)
#endif /* CONFIG_MIPS64 */
#endif /* __KERNEL__ */
/* This one accepts IRIX binaries. */
#define irix_elf_check_arch(hdr) ((hdr)->e_machine == EM_MIPS)
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE PAGE_SIZE
#define ELF_CORE_COPY_REGS(_dest,_regs) \
memcpy((char *) &_dest, (char *) _regs, \
sizeof(struct pt_regs));
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. This could be done in userspace,
but it's not easy, and we've already done it here. */
#define ELF_HWCAP (0)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo.
For the moment, we have only optimizations for the Intel generations,
but that could change... */
#define ELF_PLATFORM (NULL)
/*
* See comments in asm-alpha/elf.h, this is the same thing
* on the MIPS.
*/
#define ELF_PLAT_INIT(_r, load_addr) do { \
_r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0; \
_r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0; \
_r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0; \
_r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0; \
_r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0; \
_r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0; \
_r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0; \
_r->regs[30] = _r->regs[31] = 0; \
} while (0)
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#ifndef ELF_ET_DYN_BASE
#define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2)
#endif
#endif /* _ASM_ELF_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle
*/
#ifndef _ASM_ERRNO_H
#define _ASM_ERRNO_H
/*
* These error numbers are intended to be MIPS ABI compatible
*/
#include <asm-generic/errno-base.h>
#define ENOMSG 35 /* No message of desired type */
#define EIDRM 36 /* Identifier removed */
#define ECHRNG 37 /* Channel number out of range */
#define EL2NSYNC 38 /* Level 2 not synchronized */
#define EL3HLT 39 /* Level 3 halted */
#define EL3RST 40 /* Level 3 reset */
#define ELNRNG 41 /* Link number out of range */
#define EUNATCH 42 /* Protocol driver not attached */
#define ENOCSI 43 /* No CSI structure available */
#define EL2HLT 44 /* Level 2 halted */
#define EDEADLK 45 /* Resource deadlock would occur */
#define ENOLCK 46 /* No record locks available */
#define EBADE 50 /* Invalid exchange */
#define EBADR 51 /* Invalid request descriptor */
#define EXFULL 52 /* Exchange full */
#define ENOANO 53 /* No anode */
#define EBADRQC 54 /* Invalid request code */
#define EBADSLT 55 /* Invalid slot */
#define EDEADLOCK 56 /* File locking deadlock error */
#define EBFONT 59 /* Bad font file format */
#define ENOSTR 60 /* Device not a stream */
#define ENODATA 61 /* No data available */
#define ETIME 62 /* Timer expired */
#define ENOSR 63 /* Out of streams resources */
#define ENONET 64 /* Machine is not on the network */
#define ENOPKG 65 /* Package not installed */
#define EREMOTE 66 /* Object is remote */
#define ENOLINK 67 /* Link has been severed */
#define EADV 68 /* Advertise error */
#define ESRMNT 69 /* Srmount error */
#define ECOMM 70 /* Communication error on send */
#define EPROTO 71 /* Protocol error */
#define EDOTDOT 73 /* RFS specific error */
#define EMULTIHOP 74 /* Multihop attempted */
#define EBADMSG 77 /* Not a data message */
#define ENAMETOOLONG 78 /* File name too long */
#define EOVERFLOW 79 /* Value too large for defined data type */
#define ENOTUNIQ 80 /* Name not unique on network */
#define EBADFD 81 /* File descriptor in bad state */
#define EREMCHG 82 /* Remote address changed */
#define ELIBACC 83 /* Can not access a needed shared library */
#define ELIBBAD 84 /* Accessing a corrupted shared library */
#define ELIBSCN 85 /* .lib section in a.out corrupted */
#define ELIBMAX 86 /* Attempting to link in too many shared libraries */
#define ELIBEXEC 87 /* Cannot exec a shared library directly */
#define EILSEQ 88 /* Illegal byte sequence */
#define ENOSYS 89 /* Function not implemented */
#define ELOOP 90 /* Too many symbolic links encountered */
#define ERESTART 91 /* Interrupted system call should be restarted */
#define ESTRPIPE 92 /* Streams pipe error */
#define ENOTEMPTY 93 /* Directory not empty */
#define EUSERS 94 /* Too many users */
#define ENOTSOCK 95 /* Socket operation on non-socket */
#define EDESTADDRREQ 96 /* Destination address required */
#define EMSGSIZE 97 /* Message too long */
#define EPROTOTYPE 98 /* Protocol wrong type for socket */
#define ENOPROTOOPT 99 /* Protocol not available */
#define EPROTONOSUPPORT 120 /* Protocol not supported */
#define ESOCKTNOSUPPORT 121 /* Socket type not supported */
#define EOPNOTSUPP 122 /* Operation not supported on transport endpoint */
#define EPFNOSUPPORT 123 /* Protocol family not supported */
#define EAFNOSUPPORT 124 /* Address family not supported by protocol */
#define EADDRINUSE 125 /* Address already in use */
#define EADDRNOTAVAIL 126 /* Cannot assign requested address */
#define ENETDOWN 127 /* Network is down */
#define ENETUNREACH 128 /* Network is unreachable */
#define ENETRESET 129 /* Network dropped connection because of reset */
#define ECONNABORTED 130 /* Software caused connection abort */
#define ECONNRESET 131 /* Connection reset by peer */
#define ENOBUFS 132 /* No buffer space available */
#define EISCONN 133 /* Transport endpoint is already connected */
#define ENOTCONN 134 /* Transport endpoint is not connected */
#define EUCLEAN 135 /* Structure needs cleaning */
#define ENOTNAM 137 /* Not a XENIX named type file */
#define ENAVAIL 138 /* No XENIX semaphores available */
#define EISNAM 139 /* Is a named type file */
#define EREMOTEIO 140 /* Remote I/O error */
#define EINIT 141 /* Reserved */
#define EREMDEV 142 /* Error 142 */
#define ESHUTDOWN 143 /* Cannot send after transport endpoint shutdown */
#define ETOOMANYREFS 144 /* Too many references: cannot splice */
#define ETIMEDOUT 145 /* Connection timed out */
#define ECONNREFUSED 146 /* Connection refused */
#define EHOSTDOWN 147 /* Host is down */
#define EHOSTUNREACH 148 /* No route to host */
#define EWOULDBLOCK EAGAIN /* Operation would block */
#define EALREADY 149 /* Operation already in progress */
#define EINPROGRESS 150 /* Operation now in progress */
#define ESTALE 151 /* Stale NFS file handle */
#define ECANCELED 158 /* AIO operation canceled */
/*
* These error are Linux extensions.
*/
#define ENOMEDIUM 159 /* No medium found */
#define EMEDIUMTYPE 160 /* Wrong medium type */
#define ENOKEY 161 /* Required key not available */
#define EKEYEXPIRED 162 /* Key has expired */
#define EKEYREVOKED 163 /* Key has been revoked */
#define EKEYREJECTED 164 /* Key was rejected by service */
#define EDQUOT 1133 /* Quota exceeded */
#ifdef __KERNEL__
/* The biggest error number defined here or in <linux/errno.h>. */
#define EMAXERRNO 1133
#endif /* __KERNEL__ */
#endif /* _ASM_ERRNO_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 96, 97, 98, 99, 2003 Ralf Baechle
*/
#ifndef _ASM_FCNTL_H
#define _ASM_FCNTL_H
/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
located on an ext2 file system */
#define O_ACCMODE 0x0003
#define O_RDONLY 0x0000
#define O_WRONLY 0x0001
#define O_RDWR 0x0002
#define O_APPEND 0x0008
#define O_SYNC 0x0010
#define O_NONBLOCK 0x0080
#define O_CREAT 0x0100 /* not fcntl */
#define O_TRUNC 0x0200 /* not fcntl */
#define O_EXCL 0x0400 /* not fcntl */
#define O_NOCTTY 0x0800 /* not fcntl */
#define FASYNC 0x1000 /* fcntl, for BSD compatibility */
#define O_LARGEFILE 0x2000 /* allow large file opens */
#define O_DIRECT 0x8000 /* direct disk access hint */
#define O_DIRECTORY 0x10000 /* must be a directory */
#define O_NOFOLLOW 0x20000 /* don't follow links */
#define O_NOATIME 0x40000
#define O_NDELAY O_NONBLOCK
#define F_DUPFD 0 /* dup */
#define F_GETFD 1 /* get close_on_exec */
#define F_SETFD 2 /* set/clear close_on_exec */
#define F_GETFL 3 /* get file->f_flags */
#define F_SETFL 4 /* set file->f_flags */
#define F_GETLK 14
#define F_SETLK 6
#define F_SETLKW 7
#define F_SETOWN 24 /* for sockets. */
#define F_GETOWN 23 /* for sockets. */
#define F_SETSIG 10 /* for sockets. */
#define F_GETSIG 11 /* for sockets. */
#ifndef __mips64
#define F_GETLK64 33 /* using 'struct flock64' */
#define F_SETLK64 34
#define F_SETLKW64 35
#endif
/* for F_[GET|SET]FL */
#define FD_CLOEXEC 1 /* actually anything with low bit set goes */
/* for posix fcntl() and lockf() */
#define F_RDLCK 0
#define F_WRLCK 1
#define F_UNLCK 2
/* for old implementation of bsd flock () */
#define F_EXLCK 4 /* or 3 */
#define F_SHLCK 8 /* or 4 */
/* for leases */
#define F_INPROGRESS 16
/* operations for bsd flock(), also used by the kernel implementation */
#define LOCK_SH 1 /* shared lock */
#define LOCK_EX 2 /* exclusive lock */
#define LOCK_NB 4 /* or'd with one of the above to prevent
blocking */
#define LOCK_UN 8 /* remove lock */
#define LOCK_MAND 32 /* This is a mandatory flock */
#define LOCK_READ 64 /* ... Which allows concurrent read operations */
#define LOCK_WRITE 128 /* ... Which allows concurrent write operations */
#define LOCK_RW 192 /* ... Which allows concurrent read & write ops */
/*
* The flavours of struct flock. "struct flock" is the ABI compliant
* variant. Finally struct flock64 is the LFS variant of struct flock. As
* a historic accident and inconsistence with the ABI definition it doesn't
* contain all the same fields as struct flock.
*/
#ifndef __mips64
typedef struct flock {
short l_type;
short l_whence;
__kernel_off_t l_start;
__kernel_off_t l_len;
long l_sysid;
__kernel_pid_t l_pid;
long pad[4];
} flock_t;
typedef struct flock64 {
short l_type;
short l_whence;
loff_t l_start;
loff_t l_len;
pid_t l_pid;
} flock64_t;
#else /* 64-bit definitions */
typedef struct flock {
short l_type;
short l_whence;
__kernel_off_t l_start;
__kernel_off_t l_len;
__kernel_pid_t l_pid;
} flock_t;
#ifdef __KERNEL__
#define flock64 flock
#endif
#endif
#define F_LINUX_SPECIFIC_BASE 1024
#endif /* _ASM_FCNTL_H */

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/*
* fixmap.h: compile-time virtual memory allocation
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998 Ingo Molnar
*
* Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
*/
#ifndef _ASM_FIXMAP_H
#define _ASM_FIXMAP_H
#include <linux/config.h>
#include <asm/page.h>
#ifdef CONFIG_HIGHMEM
#include <linux/threads.h>
#include <asm/kmap_types.h>
#endif
/*
* Here we define all the compile-time 'special' virtual
* addresses. The point is to have a constant address at
* compile time, but to set the physical address only
* in the boot process. We allocate these special addresses
* from the end of virtual memory (0xfffff000) backwards.
* Also this lets us do fail-safe vmalloc(), we
* can guarantee that these special addresses and
* vmalloc()-ed addresses never overlap.
*
* these 'compile-time allocated' memory buffers are
* fixed-size 4k pages. (or larger if used with an increment
* highger than 1) use fixmap_set(idx,phys) to associate
* physical memory with fixmap indices.
*
* TLB entries of such buffers will not be flushed across
* task switches.
*/
/*
* on UP currently we will have no trace of the fixmap mechanizm,
* no page table allocations, etc. This might change in the
* future, say framebuffers for the console driver(s) could be
* fix-mapped?
*/
enum fixed_addresses {
#ifdef CONFIG_HIGHMEM
FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
#endif
__end_of_fixed_addresses
};
extern void __set_fixmap (enum fixed_addresses idx,
unsigned long phys, pgprot_t flags);
#define set_fixmap(idx, phys) \
__set_fixmap(idx, phys, PAGE_KERNEL)
/*
* Some hardware wants to get fixmapped without caching.
*/
#define set_fixmap_nocache(idx, phys) \
__set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE)
/*
* used by vmalloc.c.
*
* Leave one empty page between vmalloc'ed areas and
* the start of the fixmap, and leave one page empty
* at the top of mem..
*/
#define FIXADDR_TOP (0xffffe000UL)
#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT)
#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE)
#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT))
#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
extern void __this_fixmap_does_not_exist(void);
/*
* 'index to address' translation. If anyone tries to use the idx
* directly without tranlation, we catch the bug with a NULL-deference
* kernel oops. Illegal ranges of incoming indices are caught too.
*/
static inline unsigned long fix_to_virt(const unsigned int idx)
{
/*
* this branch gets completely eliminated after inlining,
* except when someone tries to use fixaddr indices in an
* illegal way. (such as mixing up address types or using
* out-of-range indices).
*
* If it doesn't get removed, the linker will complain
* loudly with a reasonably clear error message..
*/
if (idx >= __end_of_fixed_addresses)
__this_fixmap_does_not_exist();
return __fix_to_virt(idx);
}
static inline unsigned long virt_to_fix(const unsigned long vaddr)
{
BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
return __virt_to_fix(vaddr);
}
#endif

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/*
* Architecture specific parts of the Floppy driver
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995 - 2000 Ralf Baechle
*/
#ifndef _ASM_FLOPPY_H
#define _ASM_FLOPPY_H
static inline void fd_cacheflush(char * addr, long size)
{
dma_cache_wback_inv((unsigned long)addr,size);
}
#define MAX_BUFFER_SECTORS 24
/*
* And on Mips's the CMOS info fails also ...
*
* FIXME: This information should come from the ARC configuration tree
* or whereever a particular machine has stored this ...
*/
#define FLOPPY0_TYPE fd_drive_type(0)
#define FLOPPY1_TYPE fd_drive_type(1)
#define FDC1 fd_getfdaddr1();
#define N_FDC 1 /* do you *really* want a second controller? */
#define N_DRIVE 8
#define FLOPPY_MOTOR_MASK 0xf0
/*
* The DMA channel used by the floppy controller cannot access data at
* addresses >= 16MB
*
* Went back to the 1MB limit, as some people had problems with the floppy
* driver otherwise. It doesn't matter much for performance anyway, as most
* floppy accesses go through the track buffer.
*
* On MIPSes using vdma, this actually means that *all* transfers go thru
* the * track buffer since 0x1000000 is always smaller than KSEG0/1.
* Actually this needs to be a bit more complicated since the so much different
* hardware available with MIPS CPUs ...
*/
#define CROSS_64KB(a,s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)
#define EXTRA_FLOPPY_PARAMS
#include <floppy.h>
#endif /* _ASM_FLOPPY_H */

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/*
* Definitions for the FPU register names
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1999 Ralf Baechle
* Copyright (C) 1985 MIPS Computer Systems, Inc.
* Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
*/
#ifndef _ASM_FPREGDEF_H
#define _ASM_FPREGDEF_H
#include <asm/sgidefs.h>
#if _MIPS_SIM == _MIPS_SIM_ABI32
/*
* These definitions only cover the R3000-ish 16/32 register model.
* But we're trying to be R3000 friendly anyway ...
*/
#define fv0 $f0 /* return value */
#define fv0f $f1
#define fv1 $f2
#define fv1f $f3
#define fa0 $f12 /* argument registers */
#define fa0f $f13
#define fa1 $f14
#define fa1f $f15
#define ft0 $f4 /* caller saved */
#define ft0f $f5
#define ft1 $f6
#define ft1f $f7
#define ft2 $f8
#define ft2f $f9
#define ft3 $f10
#define ft3f $f11
#define ft4 $f16
#define ft4f $f17
#define ft5 $f18
#define ft5f $f19
#define fs0 $f20 /* callee saved */
#define fs0f $f21
#define fs1 $f22
#define fs1f $f23
#define fs2 $f24
#define fs2f $f25
#define fs3 $f26
#define fs3f $f27
#define fs4 $f28
#define fs4f $f29
#define fs5 $f30
#define fs5f $f31
#define fcr31 $31 /* FPU status register */
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
#define fv0 $f0 /* return value */
#define fv1 $f2
#define fa0 $f12 /* argument registers */
#define fa1 $f13
#define fa2 $f14
#define fa3 $f15
#define fa4 $f16
#define fa5 $f17
#define fa6 $f18
#define fa7 $f19
#define ft0 $f4 /* caller saved */
#define ft1 $f5
#define ft2 $f6
#define ft3 $f7
#define ft4 $f8
#define ft5 $f9
#define ft6 $f10
#define ft7 $f11
#define ft8 $f20
#define ft9 $f21
#define ft10 $f22
#define ft11 $f23
#define ft12 $f1
#define ft13 $f3
#define fs0 $f24 /* callee saved */
#define fs1 $f25
#define fs2 $f26
#define fs3 $f27
#define fs4 $f28
#define fs5 $f29
#define fs6 $f30
#define fs7 $f31
#define fcr31 $31
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
#endif /* _ASM_FPREGDEF_H */

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/*
* Copyright (C) 2002 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _ASM_FPU_H
#define _ASM_FPU_H
#include <linux/config.h>
#include <linux/sched.h>
#include <linux/thread_info.h>
#include <asm/mipsregs.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm/bitops.h>
#include <asm/processor.h>
#include <asm/current.h>
struct sigcontext;
struct sigcontext32;
extern asmlinkage int (*save_fp_context)(struct sigcontext *sc);
extern asmlinkage int (*restore_fp_context)(struct sigcontext *sc);
extern asmlinkage int (*save_fp_context32)(struct sigcontext32 *sc);
extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 *sc);
extern void fpu_emulator_init_fpu(void);
extern void _init_fpu(void);
extern void _save_fp(struct task_struct *);
extern void _restore_fp(struct task_struct *);
#if defined(CONFIG_CPU_SB1)
#define __enable_fpu_hazard() \
do { \
asm(".set push \n\t" \
".set mips64 \n\t" \
".set noreorder \n\t" \
"ssnop \n\t" \
"bnezl $0, .+4 \n\t" \
"ssnop \n\t" \
".set pop"); \
} while (0)
#else
#define __enable_fpu_hazard() \
do { \
asm("nop;nop;nop;nop"); /* max. hazard */ \
} while (0)
#endif
#define __enable_fpu() \
do { \
set_c0_status(ST0_CU1); \
__enable_fpu_hazard(); \
} while (0)
#define __disable_fpu() \
do { \
clear_c0_status(ST0_CU1); \
/* We don't care about the c0 hazard here */ \
} while (0)
#define enable_fpu() \
do { \
if (cpu_has_fpu) \
__enable_fpu(); \
} while (0)
#define disable_fpu() \
do { \
if (cpu_has_fpu) \
__disable_fpu(); \
} while (0)
#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
static inline int is_fpu_owner(void)
{
return cpu_has_fpu && test_thread_flag(TIF_USEDFPU);
}
static inline void own_fpu(void)
{
if (cpu_has_fpu) {
__enable_fpu();
KSTK_STATUS(current) |= ST0_CU1;
set_thread_flag(TIF_USEDFPU);
}
}
static inline void lose_fpu(void)
{
if (cpu_has_fpu) {
KSTK_STATUS(current) &= ~ST0_CU1;
clear_thread_flag(TIF_USEDFPU);
__disable_fpu();
}
}
static inline void init_fpu(void)
{
if (cpu_has_fpu) {
_init_fpu();
} else {
fpu_emulator_init_fpu();
}
}
static inline void save_fp(struct task_struct *tsk)
{
if (cpu_has_fpu)
_save_fp(tsk);
}
static inline void restore_fp(struct task_struct *tsk)
{
if (cpu_has_fpu)
_restore_fp(tsk);
}
static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
{
if (cpu_has_fpu) {
if ((tsk == current) && is_fpu_owner())
_save_fp(current);
return tsk->thread.fpu.hard.fpr;
}
return tsk->thread.fpu.soft.fpr;
}
#endif /* _ASM_FPU_H */

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/*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Further private data for which no space exists in mips_fpu_soft_struct.
* This should be subsumed into the mips_fpu_soft_struct structure as
* defined in processor.h as soon as the absurd wired absolute assembler
* offsets become dynamic at compile time.
*
* Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*/
#ifndef _ASM_FPU_EMULATOR_H
#define _ASM_FPU_EMULATOR_H
struct mips_fpu_emulator_private {
unsigned int eir;
struct {
unsigned int emulated;
unsigned int loads;
unsigned int stores;
unsigned int cp1ops;
unsigned int cp1xops;
unsigned int errors;
} stats;
};
#endif /* _ASM_FPU_EMULATOR_H */

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/*
*
*/
#ifndef _MIPS_EV96100_H
#define _MIPS_EV96100_H
#include <asm/addrspace.h>
/*
* GT64120 config space base address
*/
#define GT64120_BASE (KSEG1ADDR(0x14000000))
#define MIPS_GT_BASE GT64120_BASE
/*
* PCI Bus allocation
*/
#define GT_PCI_MEM_BASE 0x12000000UL
#define GT_PCI_MEM_SIZE 0x02000000UL
#define GT_PCI_IO_BASE 0x10000000UL
#define GT_PCI_IO_SIZE 0x02000000UL
#define GT_ISA_IO_BASE PCI_IO_BASE
/*
* Duart I/O ports.
*/
#define EV96100_COM1_BASE_ADDR (0xBD000000 + 0x20)
#define EV96100_COM2_BASE_ADDR (0xBD000000 + 0x00)
/*
* EV96100 interrupt controller register base.
*/
#define EV96100_ICTRL_REGS_BASE (KSEG1ADDR(0x1f000000))
/*
* EV96100 UART register base.
*/
#define EV96100_UART0_REGS_BASE EV96100_COM1_BASE_ADDR
#define EV96100_UART1_REGS_BASE EV96100_COM2_BASE_ADDR
#define EV96100_BASE_BAUD ( 3686400 / 16 )
/*
* Because of an error/peculiarity in the Galileo chip, we need to swap the
* bytes when running bigendian.
*/
#define __GT_READ(ofs) \
(*(volatile u32 *)(GT64120_BASE+(ofs)))
#define __GT_WRITE(ofs, data) \
do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
#endif /* !(_MIPS_EV96100_H) */

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/*
*
*/
#ifndef _MIPS_EV96100INT_H
#define _MIPS_EV96100INT_H
#define EV96100INT_UART_0 6 /* IP 6 */
#define EV96100INT_TIMER 7 /* IP 7 */
extern void ev96100int_init(void);
#endif /* !(_MIPS_EV96100_H) */

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/*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* stevel@mvista.com or source@mvista.com
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Register offsets of the MIPS GT96100 Advanced Communication Controller.
*/
#ifndef _GT96100_H
#define _GT96100_H
/*
* Galileo GT96100 internal register base.
*/
#define MIPS_GT96100_BASE (KSEG1ADDR(0x14000000))
#define GT96100_WRITE(ofs, data) \
*(volatile u32 *)(MIPS_GT96100_BASE+ofs) = cpu_to_le32(data)
#define GT96100_READ(ofs) \
le32_to_cpu(*(volatile u32 *)(MIPS_GT96100_BASE+ofs))
#define GT96100_ETH_IO_SIZE 0x4000
/************************************************************************
* Register offset addresses follow
************************************************************************/
/* CPU Interface Control Registers */
#define GT96100_CPU_INTERF_CONFIG 0x000000
/* Ethernet Ports */
#define GT96100_ETH_PHY_ADDR_REG 0x080800
#define GT96100_ETH_SMI_REG 0x080810
/*
These are offsets to port 0 registers. Add GT96100_ETH_IO_SIZE to
get offsets to port 1 registers.
*/
#define GT96100_ETH_PORT_CONFIG 0x084800
#define GT96100_ETH_PORT_CONFIG_EXT 0x084808
#define GT96100_ETH_PORT_COMM 0x084810
#define GT96100_ETH_PORT_STATUS 0x084818
#define GT96100_ETH_SER_PARAM 0x084820
#define GT96100_ETH_HASH_TBL_PTR 0x084828
#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_L 0x084830
#define GT96100_ETH_FLOW_CNTRL_SRC_ADDR_H 0x084838
#define GT96100_ETH_SDMA_CONFIG 0x084840
#define GT96100_ETH_SDMA_COMM 0x084848
#define GT96100_ETH_INT_CAUSE 0x084850
#define GT96100_ETH_INT_MASK 0x084858
#define GT96100_ETH_1ST_RX_DESC_PTR0 0x084880
#define GT96100_ETH_1ST_RX_DESC_PTR1 0x084884
#define GT96100_ETH_1ST_RX_DESC_PTR2 0x084888
#define GT96100_ETH_1ST_RX_DESC_PTR3 0x08488C
#define GT96100_ETH_CURR_RX_DESC_PTR0 0x0848A0
#define GT96100_ETH_CURR_RX_DESC_PTR1 0x0848A4
#define GT96100_ETH_CURR_RX_DESC_PTR2 0x0848A8
#define GT96100_ETH_CURR_RX_DESC_PTR3 0x0848AC
#define GT96100_ETH_CURR_TX_DESC_PTR0 0x0848E0
#define GT96100_ETH_CURR_TX_DESC_PTR1 0x0848E4
#define GT96100_ETH_MIB_COUNT_BASE 0x085800
/* SDMAs */
#define GT96100_SDMA_GROUP_CONFIG 0x101AF0
/* SDMA Group 0 */
#define GT96100_SDMA_G0_CHAN0_CONFIG 0x000900
#define GT96100_SDMA_G0_CHAN0_COMM 0x000908
#define GT96100_SDMA_G0_CHAN0_RX_DESC_BASE 0x008900
#define GT96100_SDMA_G0_CHAN0_CURR_RX_DESC_PTR 0x008910
#define GT96100_SDMA_G0_CHAN0_TX_DESC_BASE 0x00C900
#define GT96100_SDMA_G0_CHAN0_CURR_TX_DESC_PTR 0x00C910
#define GT96100_SDMA_G0_CHAN0_1ST_TX_DESC_PTR 0x00C914
#define GT96100_SDMA_G0_CHAN1_CONFIG 0x010900
#define GT96100_SDMA_G0_CHAN1_COMM 0x010908
#define GT96100_SDMA_G0_CHAN1_RX_DESC_BASE 0x018900
#define GT96100_SDMA_G0_CHAN1_CURR_RX_DESC_PTR 0x018910
#define GT96100_SDMA_G0_CHAN1_TX_DESC_BASE 0x01C900
#define GT96100_SDMA_G0_CHAN1_CURR_TX_DESC_PTR 0x01C910
#define GT96100_SDMA_G0_CHAN1_1ST_TX_DESC_PTR 0x01C914
#define GT96100_SDMA_G0_CHAN2_CONFIG 0x020900
#define GT96100_SDMA_G0_CHAN2_COMM 0x020908
#define GT96100_SDMA_G0_CHAN2_RX_DESC_BASE 0x028900
#define GT96100_SDMA_G0_CHAN2_CURR_RX_DESC_PTR 0x028910
#define GT96100_SDMA_G0_CHAN2_TX_DESC_BASE 0x02C900
#define GT96100_SDMA_G0_CHAN2_CURR_TX_DESC_PTR 0x02C910
#define GT96100_SDMA_G0_CHAN2_1ST_TX_DESC_PTR 0x02C914
#define GT96100_SDMA_G0_CHAN3_CONFIG 0x030900
#define GT96100_SDMA_G0_CHAN3_COMM 0x030908
#define GT96100_SDMA_G0_CHAN3_RX_DESC_BASE 0x038900
#define GT96100_SDMA_G0_CHAN3_CURR_RX_DESC_PTR 0x038910
#define GT96100_SDMA_G0_CHAN3_TX_DESC_BASE 0x03C900
#define GT96100_SDMA_G0_CHAN3_CURR_TX_DESC_PTR 0x03C910
#define GT96100_SDMA_G0_CHAN3_1ST_TX_DESC_PTR 0x03C914
#define GT96100_SDMA_G0_CHAN4_CONFIG 0x040900
#define GT96100_SDMA_G0_CHAN4_COMM 0x040908
#define GT96100_SDMA_G0_CHAN4_RX_DESC_BASE 0x048900
#define GT96100_SDMA_G0_CHAN4_CURR_RX_DESC_PTR 0x048910
#define GT96100_SDMA_G0_CHAN4_TX_DESC_BASE 0x04C900
#define GT96100_SDMA_G0_CHAN4_CURR_TX_DESC_PTR 0x04C910
#define GT96100_SDMA_G0_CHAN4_1ST_TX_DESC_PTR 0x04C914
#define GT96100_SDMA_G0_CHAN5_CONFIG 0x050900
#define GT96100_SDMA_G0_CHAN5_COMM 0x050908
#define GT96100_SDMA_G0_CHAN5_RX_DESC_BASE 0x058900
#define GT96100_SDMA_G0_CHAN5_CURR_RX_DESC_PTR 0x058910
#define GT96100_SDMA_G0_CHAN5_TX_DESC_BASE 0x05C900
#define GT96100_SDMA_G0_CHAN5_CURR_TX_DESC_PTR 0x05C910
#define GT96100_SDMA_G0_CHAN5_1ST_TX_DESC_PTR 0x05C914
#define GT96100_SDMA_G0_CHAN6_CONFIG 0x060900
#define GT96100_SDMA_G0_CHAN6_COMM 0x060908
#define GT96100_SDMA_G0_CHAN6_RX_DESC_BASE 0x068900
#define GT96100_SDMA_G0_CHAN6_CURR_RX_DESC_PTR 0x068910
#define GT96100_SDMA_G0_CHAN6_TX_DESC_BASE 0x06C900
#define GT96100_SDMA_G0_CHAN6_CURR_TX_DESC_PTR 0x06C910
#define GT96100_SDMA_G0_CHAN6_1ST_TX_DESC_PTR 0x06C914
#define GT96100_SDMA_G0_CHAN7_CONFIG 0x070900
#define GT96100_SDMA_G0_CHAN7_COMM 0x070908
#define GT96100_SDMA_G0_CHAN7_RX_DESC_BASE 0x078900
#define GT96100_SDMA_G0_CHAN7_CURR_RX_DESC_PTR 0x078910
#define GT96100_SDMA_G0_CHAN7_TX_DESC_BASE 0x07C900
#define GT96100_SDMA_G0_CHAN7_CURR_TX_DESC_PTR 0x07C910
#define GT96100_SDMA_G0_CHAN7_1ST_TX_DESC_PTR 0x07C914
/* SDMA Group 1 */
#define GT96100_SDMA_G1_CHAN0_CONFIG 0x100900
#define GT96100_SDMA_G1_CHAN0_COMM 0x100908
#define GT96100_SDMA_G1_CHAN0_RX_DESC_BASE 0x108900
#define GT96100_SDMA_G1_CHAN0_CURR_RX_DESC_PTR 0x108910
#define GT96100_SDMA_G1_CHAN0_TX_DESC_BASE 0x10C900
#define GT96100_SDMA_G1_CHAN0_CURR_TX_DESC_PTR 0x10C910
#define GT96100_SDMA_G1_CHAN0_1ST_TX_DESC_PTR 0x10C914
#define GT96100_SDMA_G1_CHAN1_CONFIG 0x110900
#define GT96100_SDMA_G1_CHAN1_COMM 0x110908
#define GT96100_SDMA_G1_CHAN1_RX_DESC_BASE 0x118900
#define GT96100_SDMA_G1_CHAN1_CURR_RX_DESC_PTR 0x118910
#define GT96100_SDMA_G1_CHAN1_TX_DESC_BASE 0x11C900
#define GT96100_SDMA_G1_CHAN1_CURR_TX_DESC_PTR 0x11C910
#define GT96100_SDMA_G1_CHAN1_1ST_TX_DESC_PTR 0x11C914
#define GT96100_SDMA_G1_CHAN2_CONFIG 0x120900
#define GT96100_SDMA_G1_CHAN2_COMM 0x120908
#define GT96100_SDMA_G1_CHAN2_RX_DESC_BASE 0x128900
#define GT96100_SDMA_G1_CHAN2_CURR_RX_DESC_PTR 0x128910
#define GT96100_SDMA_G1_CHAN2_TX_DESC_BASE 0x12C900
#define GT96100_SDMA_G1_CHAN2_CURR_TX_DESC_PTR 0x12C910
#define GT96100_SDMA_G1_CHAN2_1ST_TX_DESC_PTR 0x12C914
#define GT96100_SDMA_G1_CHAN3_CONFIG 0x130900
#define GT96100_SDMA_G1_CHAN3_COMM 0x130908
#define GT96100_SDMA_G1_CHAN3_RX_DESC_BASE 0x138900
#define GT96100_SDMA_G1_CHAN3_CURR_RX_DESC_PTR 0x138910
#define GT96100_SDMA_G1_CHAN3_TX_DESC_BASE 0x13C900
#define GT96100_SDMA_G1_CHAN3_CURR_TX_DESC_PTR 0x13C910
#define GT96100_SDMA_G1_CHAN3_1ST_TX_DESC_PTR 0x13C914
#define GT96100_SDMA_G1_CHAN4_CONFIG 0x140900
#define GT96100_SDMA_G1_CHAN4_COMM 0x140908
#define GT96100_SDMA_G1_CHAN4_RX_DESC_BASE 0x148900
#define GT96100_SDMA_G1_CHAN4_CURR_RX_DESC_PTR 0x148910
#define GT96100_SDMA_G1_CHAN4_TX_DESC_BASE 0x14C900
#define GT96100_SDMA_G1_CHAN4_CURR_TX_DESC_PTR 0x14C910
#define GT96100_SDMA_G1_CHAN4_1ST_TX_DESC_PTR 0x14C914
#define GT96100_SDMA_G1_CHAN5_CONFIG 0x150900
#define GT96100_SDMA_G1_CHAN5_COMM 0x150908
#define GT96100_SDMA_G1_CHAN5_RX_DESC_BASE 0x158900
#define GT96100_SDMA_G1_CHAN5_CURR_RX_DESC_PTR 0x158910
#define GT96100_SDMA_G1_CHAN5_TX_DESC_BASE 0x15C900
#define GT96100_SDMA_G1_CHAN5_CURR_TX_DESC_PTR 0x15C910
#define GT96100_SDMA_G1_CHAN5_1ST_TX_DESC_PTR 0x15C914
#define GT96100_SDMA_G1_CHAN6_CONFIG 0x160900
#define GT96100_SDMA_G1_CHAN6_COMM 0x160908
#define GT96100_SDMA_G1_CHAN6_RX_DESC_BASE 0x168900
#define GT96100_SDMA_G1_CHAN6_CURR_RX_DESC_PTR 0x168910
#define GT96100_SDMA_G1_CHAN6_TX_DESC_BASE 0x16C900
#define GT96100_SDMA_G1_CHAN6_CURR_TX_DESC_PTR 0x16C910
#define GT96100_SDMA_G1_CHAN6_1ST_TX_DESC_PTR 0x16C914
#define GT96100_SDMA_G1_CHAN7_CONFIG 0x170900
#define GT96100_SDMA_G1_CHAN7_COMM 0x170908
#define GT96100_SDMA_G1_CHAN7_RX_DESC_BASE 0x178900
#define GT96100_SDMA_G1_CHAN7_CURR_RX_DESC_PTR 0x178910
#define GT96100_SDMA_G1_CHAN7_TX_DESC_BASE 0x17C900
#define GT96100_SDMA_G1_CHAN7_CURR_TX_DESC_PTR 0x17C910
#define GT96100_SDMA_G1_CHAN7_1ST_TX_DESC_PTR 0x17C914
/* MPSCs */
#define GT96100_MPSC0_MAIN_CONFIG_LOW 0x000A00
#define GT96100_MPSC0_MAIN_CONFIG_HIGH 0x000A04
#define GT96100_MPSC0_PROTOCOL_CONFIG 0x000A08
#define GT96100_MPSC_CHAN0_REG1 0x000A0C
#define GT96100_MPSC_CHAN0_REG2 0x000A10
#define GT96100_MPSC_CHAN0_REG3 0x000A14
#define GT96100_MPSC_CHAN0_REG4 0x000A18
#define GT96100_MPSC_CHAN0_REG5 0x000A1C
#define GT96100_MPSC_CHAN0_REG6 0x000A20
#define GT96100_MPSC_CHAN0_REG7 0x000A24
#define GT96100_MPSC_CHAN0_REG8 0x000A28
#define GT96100_MPSC_CHAN0_REG9 0x000A2C
#define GT96100_MPSC_CHAN0_REG10 0x000A30
#define GT96100_MPSC_CHAN0_REG11 0x000A34
#define GT96100_MPSC1_MAIN_CONFIG_LOW 0x008A00
#define GT96100_MPSC1_MAIN_CONFIG_HIGH 0x008A04
#define GT96100_MPSC1_PROTOCOL_CONFIG 0x008A08
#define GT96100_MPSC_CHAN1_REG1 0x008A0C
#define GT96100_MPSC_CHAN1_REG2 0x008A10
#define GT96100_MPSC_CHAN1_REG3 0x008A14
#define GT96100_MPSC_CHAN1_REG4 0x008A18
#define GT96100_MPSC_CHAN1_REG5 0x008A1C
#define GT96100_MPSC_CHAN1_REG6 0x008A20
#define GT96100_MPSC_CHAN1_REG7 0x008A24
#define GT96100_MPSC_CHAN1_REG8 0x008A28
#define GT96100_MPSC_CHAN1_REG9 0x008A2C
#define GT96100_MPSC_CHAN1_REG10 0x008A30
#define GT96100_MPSC_CHAN1_REG11 0x008A34
#define GT96100_MPSC2_MAIN_CONFIG_LOW 0x010A00
#define GT96100_MPSC2_MAIN_CONFIG_HIGH 0x010A04
#define GT96100_MPSC2_PROTOCOL_CONFIG 0x010A08
#define GT96100_MPSC_CHAN2_REG1 0x010A0C
#define GT96100_MPSC_CHAN2_REG2 0x010A10
#define GT96100_MPSC_CHAN2_REG3 0x010A14
#define GT96100_MPSC_CHAN2_REG4 0x010A18
#define GT96100_MPSC_CHAN2_REG5 0x010A1C
#define GT96100_MPSC_CHAN2_REG6 0x010A20
#define GT96100_MPSC_CHAN2_REG7 0x010A24
#define GT96100_MPSC_CHAN2_REG8 0x010A28
#define GT96100_MPSC_CHAN2_REG9 0x010A2C
#define GT96100_MPSC_CHAN2_REG10 0x010A30
#define GT96100_MPSC_CHAN2_REG11 0x010A34
#define GT96100_MPSC3_MAIN_CONFIG_LOW 0x018A00
#define GT96100_MPSC3_MAIN_CONFIG_HIGH 0x018A04
#define GT96100_MPSC3_PROTOCOL_CONFIG 0x018A08
#define GT96100_MPSC_CHAN3_REG1 0x018A0C
#define GT96100_MPSC_CHAN3_REG2 0x018A10
#define GT96100_MPSC_CHAN3_REG3 0x018A14
#define GT96100_MPSC_CHAN3_REG4 0x018A18
#define GT96100_MPSC_CHAN3_REG5 0x018A1C
#define GT96100_MPSC_CHAN3_REG6 0x018A20
#define GT96100_MPSC_CHAN3_REG7 0x018A24
#define GT96100_MPSC_CHAN3_REG8 0x018A28
#define GT96100_MPSC_CHAN3_REG9 0x018A2C
#define GT96100_MPSC_CHAN3_REG10 0x018A30
#define GT96100_MPSC_CHAN3_REG11 0x018A34
#define GT96100_MPSC4_MAIN_CONFIG_LOW 0x020A00
#define GT96100_MPSC4_MAIN_CONFIG_HIGH 0x020A04
#define GT96100_MPSC4_PROTOCOL_CONFIG 0x020A08
#define GT96100_MPSC_CHAN4_REG1 0x020A0C
#define GT96100_MPSC_CHAN4_REG2 0x020A10
#define GT96100_MPSC_CHAN4_REG3 0x020A14
#define GT96100_MPSC_CHAN4_REG4 0x020A18
#define GT96100_MPSC_CHAN4_REG5 0x020A1C
#define GT96100_MPSC_CHAN4_REG6 0x020A20
#define GT96100_MPSC_CHAN4_REG7 0x020A24
#define GT96100_MPSC_CHAN4_REG8 0x020A28
#define GT96100_MPSC_CHAN4_REG9 0x020A2C
#define GT96100_MPSC_CHAN4_REG10 0x020A30
#define GT96100_MPSC_CHAN4_REG11 0x020A34
#define GT96100_MPSC5_MAIN_CONFIG_LOW 0x028A00
#define GT96100_MPSC5_MAIN_CONFIG_HIGH 0x028A04
#define GT96100_MPSC5_PROTOCOL_CONFIG 0x028A08
#define GT96100_MPSC_CHAN5_REG1 0x028A0C
#define GT96100_MPSC_CHAN5_REG2 0x028A10
#define GT96100_MPSC_CHAN5_REG3 0x028A14
#define GT96100_MPSC_CHAN5_REG4 0x028A18
#define GT96100_MPSC_CHAN5_REG5 0x028A1C
#define GT96100_MPSC_CHAN5_REG6 0x028A20
#define GT96100_MPSC_CHAN5_REG7 0x028A24
#define GT96100_MPSC_CHAN5_REG8 0x028A28
#define GT96100_MPSC_CHAN5_REG9 0x028A2C
#define GT96100_MPSC_CHAN5_REG10 0x028A30
#define GT96100_MPSC_CHAN5_REG11 0x028A34
#define GT96100_MPSC6_MAIN_CONFIG_LOW 0x030A00
#define GT96100_MPSC6_MAIN_CONFIG_HIGH 0x030A04
#define GT96100_MPSC6_PROTOCOL_CONFIG 0x030A08
#define GT96100_MPSC_CHAN6_REG1 0x030A0C
#define GT96100_MPSC_CHAN6_REG2 0x030A10
#define GT96100_MPSC_CHAN6_REG3 0x030A14
#define GT96100_MPSC_CHAN6_REG4 0x030A18
#define GT96100_MPSC_CHAN6_REG5 0x030A1C
#define GT96100_MPSC_CHAN6_REG6 0x030A20
#define GT96100_MPSC_CHAN6_REG7 0x030A24
#define GT96100_MPSC_CHAN6_REG8 0x030A28
#define GT96100_MPSC_CHAN6_REG9 0x030A2C
#define GT96100_MPSC_CHAN6_REG10 0x030A30
#define GT96100_MPSC_CHAN6_REG11 0x030A34
#define GT96100_MPSC7_MAIN_CONFIG_LOW 0x038A00
#define GT96100_MPSC7_MAIN_CONFIG_HIGH 0x038A04
#define GT96100_MPSC7_PROTOCOL_CONFIG 0x038A08
#define GT96100_MPSC_CHAN7_REG1 0x038A0C
#define GT96100_MPSC_CHAN7_REG2 0x038A10
#define GT96100_MPSC_CHAN7_REG3 0x038A14
#define GT96100_MPSC_CHAN7_REG4 0x038A18
#define GT96100_MPSC_CHAN7_REG5 0x038A1C
#define GT96100_MPSC_CHAN7_REG6 0x038A20
#define GT96100_MPSC_CHAN7_REG7 0x038A24
#define GT96100_MPSC_CHAN7_REG8 0x038A28
#define GT96100_MPSC_CHAN7_REG9 0x038A2C
#define GT96100_MPSC_CHAN7_REG10 0x038A30
#define GT96100_MPSC_CHAN7_REG11 0x038A34
/* FlexTDMs */
/* TDPR0 - Transmit Dual Port RAM. block size 0xff */
#define GT96100_FXTDM0_TDPR0_BLK0_BASE 0x000B00
#define GT96100_FXTDM0_TDPR0_BLK1_BASE 0x001B00
#define GT96100_FXTDM0_TDPR0_BLK2_BASE 0x002B00
#define GT96100_FXTDM0_TDPR0_BLK3_BASE 0x003B00
/* RDPR0 - Receive Dual Port RAM. block size 0xff */
#define GT96100_FXTDM0_RDPR0_BLK0_BASE 0x004B00
#define GT96100_FXTDM0_RDPR0_BLK1_BASE 0x005B00
#define GT96100_FXTDM0_RDPR0_BLK2_BASE 0x006B00
#define GT96100_FXTDM0_RDPR0_BLK3_BASE 0x007B00
#define GT96100_FXTDM0_TX_READ_PTR 0x008B00
#define GT96100_FXTDM0_RX_READ_PTR 0x008B04
#define GT96100_FXTDM0_CONFIG 0x008B08
#define GT96100_FXTDM0_AUX_CHANA_TX 0x008B0C
#define GT96100_FXTDM0_AUX_CHANA_RX 0x008B10
#define GT96100_FXTDM0_AUX_CHANB_TX 0x008B14
#define GT96100_FXTDM0_AUX_CHANB_RX 0x008B18
#define GT96100_FXTDM1_TDPR1_BLK0_BASE 0x010B00
#define GT96100_FXTDM1_TDPR1_BLK1_BASE 0x011B00
#define GT96100_FXTDM1_TDPR1_BLK2_BASE 0x012B00
#define GT96100_FXTDM1_TDPR1_BLK3_BASE 0x013B00
#define GT96100_FXTDM1_RDPR1_BLK0_BASE 0x014B00
#define GT96100_FXTDM1_RDPR1_BLK1_BASE 0x015B00
#define GT96100_FXTDM1_RDPR1_BLK2_BASE 0x016B00
#define GT96100_FXTDM1_RDPR1_BLK3_BASE 0x017B00
#define GT96100_FXTDM1_TX_READ_PTR 0x018B00
#define GT96100_FXTDM1_RX_READ_PTR 0x018B04
#define GT96100_FXTDM1_CONFIG 0x018B08
#define GT96100_FXTDM1_AUX_CHANA_TX 0x018B0C
#define GT96100_FXTDM1_AUX_CHANA_RX 0x018B10
#define GT96100_FLTDM1_AUX_CHANB_TX 0x018B14
#define GT96100_FLTDM1_AUX_CHANB_RX 0x018B18
#define GT96100_FLTDM2_TDPR2_BLK0_BASE 0x020B00
#define GT96100_FLTDM2_TDPR2_BLK1_BASE 0x021B00
#define GT96100_FLTDM2_TDPR2_BLK2_BASE 0x022B00
#define GT96100_FLTDM2_TDPR2_BLK3_BASE 0x023B00
#define GT96100_FLTDM2_RDPR2_BLK0_BASE 0x024B00
#define GT96100_FLTDM2_RDPR2_BLK1_BASE 0x025B00
#define GT96100_FLTDM2_RDPR2_BLK2_BASE 0x026B00
#define GT96100_FLTDM2_RDPR2_BLK3_BASE 0x027B00
#define GT96100_FLTDM2_TX_READ_PTR 0x028B00
#define GT96100_FLTDM2_RX_READ_PTR 0x028B04
#define GT96100_FLTDM2_CONFIG 0x028B08
#define GT96100_FLTDM2_AUX_CHANA_TX 0x028B0C
#define GT96100_FLTDM2_AUX_CHANA_RX 0x028B10
#define GT96100_FLTDM2_AUX_CHANB_TX 0x028B14
#define GT96100_FLTDM2_AUX_CHANB_RX 0x028B18
#define GT96100_FLTDM3_TDPR3_BLK0_BASE 0x030B00
#define GT96100_FLTDM3_TDPR3_BLK1_BASE 0x031B00
#define GT96100_FLTDM3_TDPR3_BLK2_BASE 0x032B00
#define GT96100_FLTDM3_TDPR3_BLK3_BASE 0x033B00
#define GT96100_FXTDM3_RDPR3_BLK0_BASE 0x034B00
#define GT96100_FXTDM3_RDPR3_BLK1_BASE 0x035B00
#define GT96100_FXTDM3_RDPR3_BLK2_BASE 0x036B00
#define GT96100_FXTDM3_RDPR3_BLK3_BASE 0x037B00
#define GT96100_FXTDM3_TX_READ_PTR 0x038B00
#define GT96100_FXTDM3_RX_READ_PTR 0x038B04
#define GT96100_FXTDM3_CONFIG 0x038B08
#define GT96100_FXTDM3_AUX_CHANA_TX 0x038B0C
#define GT96100_FXTDM3_AUX_CHANA_RX 0x038B10
#define GT96100_FXTDM3_AUX_CHANB_TX 0x038B14
#define GT96100_FXTDM3_AUX_CHANB_RX 0x038B18
/* Baud Rate Generators */
#define GT96100_BRG0_CONFIG 0x102A00
#define GT96100_BRG0_BAUD_TUNE 0x102A04
#define GT96100_BRG1_CONFIG 0x102A08
#define GT96100_BRG1_BAUD_TUNE 0x102A0C
#define GT96100_BRG2_CONFIG 0x102A10
#define GT96100_BRG2_BAUD_TUNE 0x102A14
#define GT96100_BRG3_CONFIG 0x102A18
#define GT96100_BRG3_BAUD_TUNE 0x102A1C
#define GT96100_BRG4_CONFIG 0x102A20
#define GT96100_BRG4_BAUD_TUNE 0x102A24
#define GT96100_BRG5_CONFIG 0x102A28
#define GT96100_BRG5_BAUD_TUNE 0x102A2C
#define GT96100_BRG6_CONFIG 0x102A30
#define GT96100_BRG6_BAUD_TUNE 0x102A34
#define GT96100_BRG7_CONFIG 0x102A38
#define GT96100_BRG7_BAUD_TUNE 0x102A3C
/* Routing Registers */
#define GT96100_ROUTE_MAIN 0x101A00
#define GT96100_ROUTE_RX_CLOCK 0x101A10
#define GT96100_ROUTE_TX_CLOCK 0x101A20
/* General Purpose Ports */
#define GT96100_GPP_CONFIG0 0x100A00
#define GT96100_GPP_CONFIG1 0x100A04
#define GT96100_GPP_CONFIG2 0x100A08
#define GT96100_GPP_CONFIG3 0x100A0C
#define GT96100_GPP_IO0 0x100A20
#define GT96100_GPP_IO1 0x100A24
#define GT96100_GPP_IO2 0x100A28
#define GT96100_GPP_IO3 0x100A2C
#define GT96100_GPP_DATA0 0x100A40
#define GT96100_GPP_DATA1 0x100A44
#define GT96100_GPP_DATA2 0x100A48
#define GT96100_GPP_DATA3 0x100A4C
#define GT96100_GPP_LEVEL0 0x100A60
#define GT96100_GPP_LEVEL1 0x100A64
#define GT96100_GPP_LEVEL2 0x100A68
#define GT96100_GPP_LEVEL3 0x100A6C
/* Watchdog */
#define GT96100_WD_CONFIG 0x101A80
#define GT96100_WD_VALUE 0x101A84
/* Communication Unit Arbiter */
#define GT96100_COMM_UNIT_ARBTR_CONFIG 0x101AC0
/* PCI Arbiters */
#define GT96100_PCI0_ARBTR_CONFIG 0x101AE0
#define GT96100_PCI1_ARBTR_CONFIG 0x101AE4
/* CIU Arbiter */
#define GT96100_CIU_ARBITER_CONFIG 0x101AC0
/* Interrupt Controller */
#define GT96100_MAIN_CAUSE 0x000C18
#define GT96100_INT0_MAIN_MASK 0x000C1C
#define GT96100_INT1_MAIN_MASK 0x000C24
#define GT96100_HIGH_CAUSE 0x000C98
#define GT96100_INT0_HIGH_MASK 0x000C9C
#define GT96100_INT1_HIGH_MASK 0x000CA4
#define GT96100_INT0_SELECT 0x000C70
#define GT96100_INT1_SELECT 0x000C74
#define GT96100_SERIAL_CAUSE 0x103A00
#define GT96100_SERINT0_MASK 0x103A80
#define GT96100_SERINT1_MASK 0x103A88
#endif /* _GT96100_H */

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/*
* include/sgidefs.h
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996 by Ralf Baechle
*
* This file is here to satisfy GCC's expectations.
*/
#ifndef __SGIDEFS_H
#define __SGIDEFS_H
#include <asm/sgidefs.h>
#endif /* __SGIDEFS_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995 Andreas Busse
* Copyright (C) 2003 Ralf Baechle
*/
#ifndef _ASM_GDB_STUB_H
#define _ASM_GDB_STUB_H
/*
* important register numbers
*/
#define REG_EPC 37
#define REG_FP 72
#define REG_SP 29
/*
* Stack layout for the GDB exception handler
* Derived from the stack layout described in asm-mips/stackframe.h
*
* The first PTRSIZE*6 bytes are argument save space for C subroutines.
*/
#define NUMREGS 90
#define GDB_FR_REG0 (PTRSIZE*6) /* 0 */
#define GDB_FR_REG1 ((GDB_FR_REG0) + LONGSIZE) /* 1 */
#define GDB_FR_REG2 ((GDB_FR_REG1) + LONGSIZE) /* 2 */
#define GDB_FR_REG3 ((GDB_FR_REG2) + LONGSIZE) /* 3 */
#define GDB_FR_REG4 ((GDB_FR_REG3) + LONGSIZE) /* 4 */
#define GDB_FR_REG5 ((GDB_FR_REG4) + LONGSIZE) /* 5 */
#define GDB_FR_REG6 ((GDB_FR_REG5) + LONGSIZE) /* 6 */
#define GDB_FR_REG7 ((GDB_FR_REG6) + LONGSIZE) /* 7 */
#define GDB_FR_REG8 ((GDB_FR_REG7) + LONGSIZE) /* 8 */
#define GDB_FR_REG9 ((GDB_FR_REG8) + LONGSIZE) /* 9 */
#define GDB_FR_REG10 ((GDB_FR_REG9) + LONGSIZE) /* 10 */
#define GDB_FR_REG11 ((GDB_FR_REG10) + LONGSIZE) /* 11 */
#define GDB_FR_REG12 ((GDB_FR_REG11) + LONGSIZE) /* 12 */
#define GDB_FR_REG13 ((GDB_FR_REG12) + LONGSIZE) /* 13 */
#define GDB_FR_REG14 ((GDB_FR_REG13) + LONGSIZE) /* 14 */
#define GDB_FR_REG15 ((GDB_FR_REG14) + LONGSIZE) /* 15 */
#define GDB_FR_REG16 ((GDB_FR_REG15) + LONGSIZE) /* 16 */
#define GDB_FR_REG17 ((GDB_FR_REG16) + LONGSIZE) /* 17 */
#define GDB_FR_REG18 ((GDB_FR_REG17) + LONGSIZE) /* 18 */
#define GDB_FR_REG19 ((GDB_FR_REG18) + LONGSIZE) /* 19 */
#define GDB_FR_REG20 ((GDB_FR_REG19) + LONGSIZE) /* 20 */
#define GDB_FR_REG21 ((GDB_FR_REG20) + LONGSIZE) /* 21 */
#define GDB_FR_REG22 ((GDB_FR_REG21) + LONGSIZE) /* 22 */
#define GDB_FR_REG23 ((GDB_FR_REG22) + LONGSIZE) /* 23 */
#define GDB_FR_REG24 ((GDB_FR_REG23) + LONGSIZE) /* 24 */
#define GDB_FR_REG25 ((GDB_FR_REG24) + LONGSIZE) /* 25 */
#define GDB_FR_REG26 ((GDB_FR_REG25) + LONGSIZE) /* 26 */
#define GDB_FR_REG27 ((GDB_FR_REG26) + LONGSIZE) /* 27 */
#define GDB_FR_REG28 ((GDB_FR_REG27) + LONGSIZE) /* 28 */
#define GDB_FR_REG29 ((GDB_FR_REG28) + LONGSIZE) /* 29 */
#define GDB_FR_REG30 ((GDB_FR_REG29) + LONGSIZE) /* 30 */
#define GDB_FR_REG31 ((GDB_FR_REG30) + LONGSIZE) /* 31 */
/*
* Saved special registers
*/
#define GDB_FR_STATUS ((GDB_FR_REG31) + LONGSIZE) /* 32 */
#define GDB_FR_LO ((GDB_FR_STATUS) + LONGSIZE) /* 33 */
#define GDB_FR_HI ((GDB_FR_LO) + LONGSIZE) /* 34 */
#define GDB_FR_BADVADDR ((GDB_FR_HI) + LONGSIZE) /* 35 */
#define GDB_FR_CAUSE ((GDB_FR_BADVADDR) + LONGSIZE) /* 36 */
#define GDB_FR_EPC ((GDB_FR_CAUSE) + LONGSIZE) /* 37 */
/*
* Saved floating point registers
*/
#define GDB_FR_FPR0 ((GDB_FR_EPC) + LONGSIZE) /* 38 */
#define GDB_FR_FPR1 ((GDB_FR_FPR0) + LONGSIZE) /* 39 */
#define GDB_FR_FPR2 ((GDB_FR_FPR1) + LONGSIZE) /* 40 */
#define GDB_FR_FPR3 ((GDB_FR_FPR2) + LONGSIZE) /* 41 */
#define GDB_FR_FPR4 ((GDB_FR_FPR3) + LONGSIZE) /* 42 */
#define GDB_FR_FPR5 ((GDB_FR_FPR4) + LONGSIZE) /* 43 */
#define GDB_FR_FPR6 ((GDB_FR_FPR5) + LONGSIZE) /* 44 */
#define GDB_FR_FPR7 ((GDB_FR_FPR6) + LONGSIZE) /* 45 */
#define GDB_FR_FPR8 ((GDB_FR_FPR7) + LONGSIZE) /* 46 */
#define GDB_FR_FPR9 ((GDB_FR_FPR8) + LONGSIZE) /* 47 */
#define GDB_FR_FPR10 ((GDB_FR_FPR9) + LONGSIZE) /* 48 */
#define GDB_FR_FPR11 ((GDB_FR_FPR10) + LONGSIZE) /* 49 */
#define GDB_FR_FPR12 ((GDB_FR_FPR11) + LONGSIZE) /* 50 */
#define GDB_FR_FPR13 ((GDB_FR_FPR12) + LONGSIZE) /* 51 */
#define GDB_FR_FPR14 ((GDB_FR_FPR13) + LONGSIZE) /* 52 */
#define GDB_FR_FPR15 ((GDB_FR_FPR14) + LONGSIZE) /* 53 */
#define GDB_FR_FPR16 ((GDB_FR_FPR15) + LONGSIZE) /* 54 */
#define GDB_FR_FPR17 ((GDB_FR_FPR16) + LONGSIZE) /* 55 */
#define GDB_FR_FPR18 ((GDB_FR_FPR17) + LONGSIZE) /* 56 */
#define GDB_FR_FPR19 ((GDB_FR_FPR18) + LONGSIZE) /* 57 */
#define GDB_FR_FPR20 ((GDB_FR_FPR19) + LONGSIZE) /* 58 */
#define GDB_FR_FPR21 ((GDB_FR_FPR20) + LONGSIZE) /* 59 */
#define GDB_FR_FPR22 ((GDB_FR_FPR21) + LONGSIZE) /* 60 */
#define GDB_FR_FPR23 ((GDB_FR_FPR22) + LONGSIZE) /* 61 */
#define GDB_FR_FPR24 ((GDB_FR_FPR23) + LONGSIZE) /* 62 */
#define GDB_FR_FPR25 ((GDB_FR_FPR24) + LONGSIZE) /* 63 */
#define GDB_FR_FPR26 ((GDB_FR_FPR25) + LONGSIZE) /* 64 */
#define GDB_FR_FPR27 ((GDB_FR_FPR26) + LONGSIZE) /* 65 */
#define GDB_FR_FPR28 ((GDB_FR_FPR27) + LONGSIZE) /* 66 */
#define GDB_FR_FPR29 ((GDB_FR_FPR28) + LONGSIZE) /* 67 */
#define GDB_FR_FPR30 ((GDB_FR_FPR29) + LONGSIZE) /* 68 */
#define GDB_FR_FPR31 ((GDB_FR_FPR30) + LONGSIZE) /* 69 */
#define GDB_FR_FSR ((GDB_FR_FPR31) + LONGSIZE) /* 70 */
#define GDB_FR_FIR ((GDB_FR_FSR) + LONGSIZE) /* 71 */
#define GDB_FR_FRP ((GDB_FR_FIR) + LONGSIZE) /* 72 */
#define GDB_FR_DUMMY ((GDB_FR_FRP) + LONGSIZE) /* 73, unused ??? */
/*
* Again, CP0 registers
*/
#define GDB_FR_CP0_INDEX ((GDB_FR_DUMMY) + LONGSIZE) /* 74 */
#define GDB_FR_CP0_RANDOM ((GDB_FR_CP0_INDEX) + LONGSIZE) /* 75 */
#define GDB_FR_CP0_ENTRYLO0 ((GDB_FR_CP0_RANDOM) + LONGSIZE)/* 76 */
#define GDB_FR_CP0_ENTRYLO1 ((GDB_FR_CP0_ENTRYLO0) + LONGSIZE)/* 77 */
#define GDB_FR_CP0_CONTEXT ((GDB_FR_CP0_ENTRYLO1) + LONGSIZE)/* 78 */
#define GDB_FR_CP0_PAGEMASK ((GDB_FR_CP0_CONTEXT) + LONGSIZE)/* 79 */
#define GDB_FR_CP0_WIRED ((GDB_FR_CP0_PAGEMASK) + LONGSIZE)/* 80 */
#define GDB_FR_CP0_REG7 ((GDB_FR_CP0_WIRED) + LONGSIZE) /* 81 */
#define GDB_FR_CP0_REG8 ((GDB_FR_CP0_REG7) + LONGSIZE) /* 82 */
#define GDB_FR_CP0_REG9 ((GDB_FR_CP0_REG8) + LONGSIZE) /* 83 */
#define GDB_FR_CP0_ENTRYHI ((GDB_FR_CP0_REG9) + LONGSIZE) /* 84 */
#define GDB_FR_CP0_REG11 ((GDB_FR_CP0_ENTRYHI) + LONGSIZE)/* 85 */
#define GDB_FR_CP0_REG12 ((GDB_FR_CP0_REG11) + LONGSIZE) /* 86 */
#define GDB_FR_CP0_REG13 ((GDB_FR_CP0_REG12) + LONGSIZE) /* 87 */
#define GDB_FR_CP0_REG14 ((GDB_FR_CP0_REG13) + LONGSIZE) /* 88 */
#define GDB_FR_CP0_PRID ((GDB_FR_CP0_REG14) + LONGSIZE) /* 89 */
#define GDB_FR_SIZE ((((GDB_FR_CP0_PRID) + LONGSIZE) + (PTRSIZE-1)) & ~(PTRSIZE-1))
#ifndef __ASSEMBLY__
/*
* This is the same as above, but for the high-level
* part of the GDB stub.
*/
struct gdb_regs {
/*
* Pad bytes for argument save space on the stack
* 24/48 Bytes for 32/64 bit code
*/
unsigned long pad0[6];
/*
* saved main processor registers
*/
long reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7;
long reg8, reg9, reg10, reg11, reg12, reg13, reg14, reg15;
long reg16, reg17, reg18, reg19, reg20, reg21, reg22, reg23;
long reg24, reg25, reg26, reg27, reg28, reg29, reg30, reg31;
/*
* Saved special registers
*/
long cp0_status;
long lo;
long hi;
long cp0_badvaddr;
long cp0_cause;
long cp0_epc;
/*
* Saved floating point registers
*/
long fpr0, fpr1, fpr2, fpr3, fpr4, fpr5, fpr6, fpr7;
long fpr8, fpr9, fpr10, fpr11, fpr12, fpr13, fpr14, fpr15;
long fpr16, fpr17, fpr18, fpr19, fpr20, fpr21, fpr22, fpr23;
long fpr24, fpr25, fpr26, fpr27, fpr28, fpr29, fpr30, fpr31;
long cp1_fsr;
long cp1_fir;
/*
* Frame pointer
*/
long frame_ptr;
long dummy; /* unused */
/*
* saved cp0 registers
*/
long cp0_index;
long cp0_random;
long cp0_entrylo0;
long cp0_entrylo1;
long cp0_context;
long cp0_pagemask;
long cp0_wired;
long cp0_reg7;
long cp0_reg8;
long cp0_reg9;
long cp0_entryhi;
long cp0_reg11;
long cp0_reg12;
long cp0_reg13;
long cp0_reg14;
long cp0_prid;
};
/*
* Prototypes
*/
extern int kgdb_enabled;
void set_debug_traps(void);
void set_async_breakpoint(unsigned long *epc);
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_GDB_STUB_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* This is the user-visible SGI GFX interface.
*
* This must be used verbatim into the GNU libc. It does not include
* any kernel-only bits on it.
*
* miguel@nuclecu.unam.mx
*/
#ifndef _ASM_GFX_H
#define _ASM_GFX_H
/* The iocls, yes, they do not make sense, but such is life */
#define GFX_BASE 100
#define GFX_GETNUM_BOARDS (GFX_BASE + 1)
#define GFX_GETBOARD_INFO (GFX_BASE + 2)
#define GFX_ATTACH_BOARD (GFX_BASE + 3)
#define GFX_DETACH_BOARD (GFX_BASE + 4)
#define GFX_IS_MANAGED (GFX_BASE + 5)
#define GFX_MAPALL (GFX_BASE + 10)
#define GFX_LABEL (GFX_BASE + 11)
#define GFX_INFO_NAME_SIZE 16
#define GFX_INFO_LABEL_SIZE 16
struct gfx_info {
char name [GFX_INFO_NAME_SIZE]; /* board name */
char label [GFX_INFO_LABEL_SIZE]; /* label name */
unsigned short int xpmax, ypmax; /* screen resolution */
unsigned int lenght; /* size of a complete gfx_info for this board */
};
struct gfx_getboardinfo_args {
unsigned int board; /* board number. starting from zero */
void *buf; /* pointer to gfx_info */
unsigned int len; /* buffer size of buf */
};
struct gfx_attach_board_args {
unsigned int board; /* board number, starting from zero */
void *vaddr; /* address where the board registers should be mapped */
};
#ifdef __KERNEL__
/* umap.c */
extern void remove_mapping (struct vm_area_struct *vma, struct task_struct *, unsigned long, unsigned long);
extern void *vmalloc_uncached (unsigned long size);
extern int vmap_page_range (struct vm_area_struct *vma, unsigned long from, unsigned long size, unsigned long vaddr);
#endif
#endif /* _ASM_GFX_H */

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/*
* Carsten Langgaard, carstenl@mips.com
* Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*/
#ifndef _ASM_GT64120_H
#define _ASM_GT64120_H
#include <linux/config.h>
#include <asm/addrspace.h>
#include <asm/byteorder.h>
#define MSK(n) ((1 << (n)) - 1)
/*
* Register offset addresses
*/
#define GT_CPU_OFS 0x000
/*
* Interrupt Registers
*/
#define GT_SCS10LD_OFS 0x008
#define GT_SCS10HD_OFS 0x010
#define GT_SCS32LD_OFS 0x018
#define GT_SCS32HD_OFS 0x020
#define GT_CS20LD_OFS 0x028
#define GT_CS20HD_OFS 0x030
#define GT_CS3BOOTLD_OFS 0x038
#define GT_CS3BOOTHD_OFS 0x040
#define GT_PCI0IOLD_OFS 0x048
#define GT_PCI0IOHD_OFS 0x050
#define GT_PCI0M0LD_OFS 0x058
#define GT_PCI0M0HD_OFS 0x060
#define GT_ISD_OFS 0x068
#define GT_PCI0M1LD_OFS 0x080
#define GT_PCI0M1HD_OFS 0x088
#define GT_PCI1IOLD_OFS 0x090
#define GT_PCI1IOHD_OFS 0x098
#define GT_PCI1M0LD_OFS 0x0a0
#define GT_PCI1M0HD_OFS 0x0a8
#define GT_PCI1M1LD_OFS 0x0b0
#define GT_PCI1M1HD_OFS 0x0b8
/*
* GT64120A only
*/
#define GT_PCI0IOREMAP_OFS 0x0f0
#define GT_PCI0M0REMAP_OFS 0x0f8
#define GT_PCI0M1REMAP_OFS 0x100
#define GT_PCI1IOREMAP_OFS 0x108
#define GT_PCI1M0REMAP_OFS 0x110
#define GT_PCI1M1REMAP_OFS 0x118
#define GT_SCS0LD_OFS 0x400
#define GT_SCS0HD_OFS 0x404
#define GT_SCS1LD_OFS 0x408
#define GT_SCS1HD_OFS 0x40c
#define GT_SCS2LD_OFS 0x410
#define GT_SCS2HD_OFS 0x414
#define GT_SCS3LD_OFS 0x418
#define GT_SCS3HD_OFS 0x41c
#define GT_CS0LD_OFS 0x420
#define GT_CS0HD_OFS 0x424
#define GT_CS1LD_OFS 0x428
#define GT_CS1HD_OFS 0x42c
#define GT_CS2LD_OFS 0x430
#define GT_CS2HD_OFS 0x434
#define GT_CS3LD_OFS 0x438
#define GT_CS3HD_OFS 0x43c
#define GT_BOOTLD_OFS 0x440
#define GT_BOOTHD_OFS 0x444
#define GT_SDRAM_B0_OFS 0x44c
#define GT_SDRAM_CFG_OFS 0x448
#define GT_SDRAM_B2_OFS 0x454
#define GT_SDRAM_OPMODE_OFS 0x474
#define GT_SDRAM_BM_OFS 0x478
#define GT_SDRAM_ADDRDECODE_OFS 0x47c
#define GT_PCI0_CMD_OFS 0xc00 /* GT64120A only */
#define GT_PCI0_TOR_OFS 0xc04
#define GT_PCI0_BS_SCS10_OFS 0xc08
#define GT_PCI0_BS_SCS32_OFS 0xc0c
#define GT_INTRCAUSE_OFS 0xc18
#define GT_INTRMASK_OFS 0xc1c /* GT64120A only */
#define GT_PCI0_IACK_OFS 0xc34
#define GT_PCI0_BARE_OFS 0xc3c
#define GT_HINTRCAUSE_OFS 0xc98 /* GT64120A only */
#define GT_HINTRMASK_OFS 0xc9c /* GT64120A only */
#define GT_PCI1_CFGADDR_OFS 0xcf0 /* GT64120A only */
#define GT_PCI1_CFGDATA_OFS 0xcf4 /* GT64120A only */
#define GT_PCI0_CFGADDR_OFS 0xcf8
#define GT_PCI0_CFGDATA_OFS 0xcfc
/*
* Timer/Counter. GT64120A only.
*/
#define GT_TC0_OFS 0x850
#define GT_TC1_OFS 0x854
#define GT_TC2_OFS 0x858
#define GT_TC3_OFS 0x85C
#define GT_TC_CONTROL_OFS 0x864
/*
* I2O Support Registers
*/
#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01c
#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02c
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06c
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07c
#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c10
#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c14
#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1c18
#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1c1c
#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c20
#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c24
#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c28
#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1c2c
#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1c30
#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1c34
#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c40
#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1c44
#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1c50
#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1c54
#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c60
#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c64
#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c68
#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c6c
#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c70
#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c74
#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1c78
#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1c7c
/*
* Register encodings
*/
#define GT_CPU_ENDIAN_SHF 12
#define GT_CPU_ENDIAN_MSK (MSK(1) << GT_CPU_ENDIAN_SHF)
#define GT_CPU_ENDIAN_BIT GT_CPU_ENDIAN_MSK
#define GT_CPU_WR_SHF 16
#define GT_CPU_WR_MSK (MSK(1) << GT_CPU_WR_SHF)
#define GT_CPU_WR_BIT GT_CPU_WR_MSK
#define GT_CPU_WR_DXDXDXDX 0
#define GT_CPU_WR_DDDD 1
#define GT_CFGADDR_CFGEN_SHF 31
#define GT_CFGADDR_CFGEN_MSK (MSK(1) << GT_CFGADDR_CFGEN_SHF)
#define GT_CFGADDR_CFGEN_BIT GT_CFGADDR_CFGEN_MSK
#define GT_CFGADDR_BUSNUM_SHF 16
#define GT_CFGADDR_BUSNUM_MSK (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
#define GT_CFGADDR_DEVNUM_SHF 11
#define GT_CFGADDR_DEVNUM_MSK (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
#define GT_CFGADDR_FUNCNUM_SHF 8
#define GT_CFGADDR_FUNCNUM_MSK (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
#define GT_CFGADDR_REGNUM_SHF 2
#define GT_CFGADDR_REGNUM_MSK (MSK(6) << GT_CFGADDR_REGNUM_SHF)
#define GT_SDRAM_BM_ORDER_SHF 2
#define GT_SDRAM_BM_ORDER_MSK (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
#define GT_SDRAM_BM_ORDER_BIT GT_SDRAM_BM_ORDER_MSK
#define GT_SDRAM_BM_ORDER_SUB 1
#define GT_SDRAM_BM_ORDER_LIN 0
#define GT_SDRAM_BM_RSVD_ALL1 0xffb
#define GT_SDRAM_ADDRDECODE_ADDR_SHF 0
#define GT_SDRAM_ADDRDECODE_ADDR_MSK (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
#define GT_SDRAM_ADDRDECODE_ADDR_0 0
#define GT_SDRAM_ADDRDECODE_ADDR_1 1
#define GT_SDRAM_ADDRDECODE_ADDR_2 2
#define GT_SDRAM_ADDRDECODE_ADDR_3 3
#define GT_SDRAM_ADDRDECODE_ADDR_4 4
#define GT_SDRAM_ADDRDECODE_ADDR_5 5
#define GT_SDRAM_ADDRDECODE_ADDR_6 6
#define GT_SDRAM_ADDRDECODE_ADDR_7 7
#define GT_SDRAM_B0_CASLAT_SHF 0
#define GT_SDRAM_B0_CASLAT_MSK (MSK(2) << GT_SDRAM_B0__SHF)
#define GT_SDRAM_B0_CASLAT_2 1
#define GT_SDRAM_B0_CASLAT_3 2
#define GT_SDRAM_B0_FTDIS_SHF 2
#define GT_SDRAM_B0_FTDIS_MSK (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
#define GT_SDRAM_B0_FTDIS_BIT GT_SDRAM_B0_FTDIS_MSK
#define GT_SDRAM_B0_SRASPRCHG_SHF 3
#define GT_SDRAM_B0_SRASPRCHG_MSK (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
#define GT_SDRAM_B0_SRASPRCHG_BIT GT_SDRAM_B0_SRASPRCHG_MSK
#define GT_SDRAM_B0_SRASPRCHG_2 0
#define GT_SDRAM_B0_SRASPRCHG_3 1
#define GT_SDRAM_B0_B0COMPAB_SHF 4
#define GT_SDRAM_B0_B0COMPAB_MSK (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
#define GT_SDRAM_B0_B0COMPAB_BIT GT_SDRAM_B0_B0COMPAB_MSK
#define GT_SDRAM_B0_64BITINT_SHF 5
#define GT_SDRAM_B0_64BITINT_MSK (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
#define GT_SDRAM_B0_64BITINT_BIT GT_SDRAM_B0_64BITINT_MSK
#define GT_SDRAM_B0_64BITINT_2 0
#define GT_SDRAM_B0_64BITINT_4 1
#define GT_SDRAM_B0_BW_SHF 6
#define GT_SDRAM_B0_BW_MSK (MSK(1) << GT_SDRAM_B0_BW_SHF)
#define GT_SDRAM_B0_BW_BIT GT_SDRAM_B0_BW_MSK
#define GT_SDRAM_B0_BW_32 0
#define GT_SDRAM_B0_BW_64 1
#define GT_SDRAM_B0_BLODD_SHF 7
#define GT_SDRAM_B0_BLODD_MSK (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
#define GT_SDRAM_B0_BLODD_BIT GT_SDRAM_B0_BLODD_MSK
#define GT_SDRAM_B0_PAR_SHF 8
#define GT_SDRAM_B0_PAR_MSK (MSK(1) << GT_SDRAM_B0_PAR_SHF)
#define GT_SDRAM_B0_PAR_BIT GT_SDRAM_B0_PAR_MSK
#define GT_SDRAM_B0_BYPASS_SHF 9
#define GT_SDRAM_B0_BYPASS_MSK (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
#define GT_SDRAM_B0_BYPASS_BIT GT_SDRAM_B0_BYPASS_MSK
#define GT_SDRAM_B0_SRAS2SCAS_SHF 10
#define GT_SDRAM_B0_SRAS2SCAS_MSK (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
#define GT_SDRAM_B0_SRAS2SCAS_BIT GT_SDRAM_B0_SRAS2SCAS_MSK
#define GT_SDRAM_B0_SRAS2SCAS_2 0
#define GT_SDRAM_B0_SRAS2SCAS_3 1
#define GT_SDRAM_B0_SIZE_SHF 11
#define GT_SDRAM_B0_SIZE_MSK (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
#define GT_SDRAM_B0_SIZE_BIT GT_SDRAM_B0_SIZE_MSK
#define GT_SDRAM_B0_SIZE_16M 0
#define GT_SDRAM_B0_SIZE_64M 1
#define GT_SDRAM_B0_EXTPAR_SHF 12
#define GT_SDRAM_B0_EXTPAR_MSK (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
#define GT_SDRAM_B0_EXTPAR_BIT GT_SDRAM_B0_EXTPAR_MSK
#define GT_SDRAM_B0_BLEN_SHF 13
#define GT_SDRAM_B0_BLEN_MSK (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
#define GT_SDRAM_B0_BLEN_BIT GT_SDRAM_B0_BLEN_MSK
#define GT_SDRAM_B0_BLEN_8 0
#define GT_SDRAM_B0_BLEN_4 1
#define GT_SDRAM_CFG_REFINT_SHF 0
#define GT_SDRAM_CFG_REFINT_MSK (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
#define GT_SDRAM_CFG_NINTERLEAVE_SHF 14
#define GT_SDRAM_CFG_NINTERLEAVE_MSK (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
#define GT_SDRAM_CFG_NINTERLEAVE_BIT GT_SDRAM_CFG_NINTERLEAVE_MSK
#define GT_SDRAM_CFG_RMW_SHF 15
#define GT_SDRAM_CFG_RMW_MSK (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
#define GT_SDRAM_CFG_RMW_BIT GT_SDRAM_CFG_RMW_MSK
#define GT_SDRAM_CFG_NONSTAGREF_SHF 16
#define GT_SDRAM_CFG_NONSTAGREF_MSK (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
#define GT_SDRAM_CFG_NONSTAGREF_BIT GT_SDRAM_CFG_NONSTAGREF_MSK
#define GT_SDRAM_CFG_DUPCNTL_SHF 19
#define GT_SDRAM_CFG_DUPCNTL_MSK (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
#define GT_SDRAM_CFG_DUPCNTL_BIT GT_SDRAM_CFG_DUPCNTL_MSK
#define GT_SDRAM_CFG_DUPBA_SHF 20
#define GT_SDRAM_CFG_DUPBA_MSK (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
#define GT_SDRAM_CFG_DUPBA_BIT GT_SDRAM_CFG_DUPBA_MSK
#define GT_SDRAM_CFG_DUPEOT0_SHF 21
#define GT_SDRAM_CFG_DUPEOT0_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
#define GT_SDRAM_CFG_DUPEOT0_BIT GT_SDRAM_CFG_DUPEOT0_MSK
#define GT_SDRAM_CFG_DUPEOT1_SHF 22
#define GT_SDRAM_CFG_DUPEOT1_MSK (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
#define GT_SDRAM_CFG_DUPEOT1_BIT GT_SDRAM_CFG_DUPEOT1_MSK
#define GT_SDRAM_OPMODE_OP_SHF 0
#define GT_SDRAM_OPMODE_OP_MSK (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
#define GT_SDRAM_OPMODE_OP_NORMAL 0
#define GT_SDRAM_OPMODE_OP_NOP 1
#define GT_SDRAM_OPMODE_OP_PRCHG 2
#define GT_SDRAM_OPMODE_OP_MODE 3
#define GT_SDRAM_OPMODE_OP_CBR 4
#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF 0
#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
#define GT_PCI0_BARE_SWSCS32DIS_SHF 1
#define GT_PCI0_BARE_SWSCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
#define GT_PCI0_BARE_SWSCS32DIS_BIT GT_PCI0_BARE_SWSCS32DIS_MSK
#define GT_PCI0_BARE_SWSCS10DIS_SHF 2
#define GT_PCI0_BARE_SWSCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
#define GT_PCI0_BARE_SWSCS10DIS_BIT GT_PCI0_BARE_SWSCS10DIS_MSK
#define GT_PCI0_BARE_INTIODIS_SHF 3
#define GT_PCI0_BARE_INTIODIS_MSK (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
#define GT_PCI0_BARE_INTIODIS_BIT GT_PCI0_BARE_INTIODIS_MSK
#define GT_PCI0_BARE_INTMEMDIS_SHF 4
#define GT_PCI0_BARE_INTMEMDIS_MSK (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
#define GT_PCI0_BARE_INTMEMDIS_BIT GT_PCI0_BARE_INTMEMDIS_MSK
#define GT_PCI0_BARE_CS3BOOTDIS_SHF 5
#define GT_PCI0_BARE_CS3BOOTDIS_MSK (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
#define GT_PCI0_BARE_CS3BOOTDIS_BIT GT_PCI0_BARE_CS3BOOTDIS_MSK
#define GT_PCI0_BARE_CS20DIS_SHF 6
#define GT_PCI0_BARE_CS20DIS_MSK (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
#define GT_PCI0_BARE_CS20DIS_BIT GT_PCI0_BARE_CS20DIS_MSK
#define GT_PCI0_BARE_SCS32DIS_SHF 7
#define GT_PCI0_BARE_SCS32DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
#define GT_PCI0_BARE_SCS32DIS_BIT GT_PCI0_BARE_SCS32DIS_MSK
#define GT_PCI0_BARE_SCS10DIS_SHF 8
#define GT_PCI0_BARE_SCS10DIS_MSK (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
#define GT_PCI0_BARE_SCS10DIS_BIT GT_PCI0_BARE_SCS10DIS_MSK
#define GT_INTRCAUSE_MASABORT0_SHF 18
#define GT_INTRCAUSE_MASABORT0_MSK (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
#define GT_INTRCAUSE_MASABORT0_BIT GT_INTRCAUSE_MASABORT0_MSK
#define GT_INTRCAUSE_TARABORT0_SHF 19
#define GT_INTRCAUSE_TARABORT0_MSK (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
#define GT_INTRCAUSE_TARABORT0_BIT GT_INTRCAUSE_TARABORT0_MSK
#define GT_PCI0_CFGADDR_REGNUM_SHF 2
#define GT_PCI0_CFGADDR_REGNUM_MSK (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
#define GT_PCI0_CFGADDR_FUNCTNUM_SHF 8
#define GT_PCI0_CFGADDR_FUNCTNUM_MSK (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
#define GT_PCI0_CFGADDR_DEVNUM_SHF 11
#define GT_PCI0_CFGADDR_DEVNUM_MSK (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
#define GT_PCI0_CFGADDR_BUSNUM_SHF 16
#define GT_PCI0_CFGADDR_BUSNUM_MSK (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_SHF 31
#define GT_PCI0_CFGADDR_CONFIGEN_MSK (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
#define GT_PCI0_CFGADDR_CONFIGEN_BIT GT_PCI0_CFGADDR_CONFIGEN_MSK
#define GT_PCI0_CMD_MBYTESWAP_SHF 0
#define GT_PCI0_CMD_MBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
#define GT_PCI0_CMD_MBYTESWAP_BIT GT_PCI0_CMD_MBYTESWAP_MSK
#define GT_PCI0_CMD_MWORDSWAP_SHF 10
#define GT_PCI0_CMD_MWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
#define GT_PCI0_CMD_MWORDSWAP_BIT GT_PCI0_CMD_MWORDSWAP_MSK
#define GT_PCI0_CMD_SBYTESWAP_SHF 16
#define GT_PCI0_CMD_SBYTESWAP_MSK (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
#define GT_PCI0_CMD_SBYTESWAP_BIT GT_PCI0_CMD_SBYTESWAP_MSK
#define GT_PCI0_CMD_SWORDSWAP_SHF 11
#define GT_PCI0_CMD_SWORDSWAP_MSK (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
#define GT_PCI0_CMD_SWORDSWAP_BIT GT_PCI0_CMD_SWORDSWAP_MSK
/*
* Misc
*/
#define GT_DEF_PCI0_IO_BASE 0x10000000UL
#define GT_DEF_PCI0_IO_SIZE 0x02000000UL
#define GT_DEF_PCI0_MEM0_BASE 0x12000000UL
#define GT_DEF_PCI0_MEM0_SIZE 0x02000000UL
#define GT_DEF_BASE 0x14000000UL
#define GT_MAX_BANKSIZE (256 * 1024 * 1024) /* Max 256MB bank */
#define GT_LATTIM_MIN 6 /* Minimum lat */
/*
* The gt64120_dep.h file must define the following macros
*
* GT_READ(ofs, data_pointer)
* GT_WRITE(ofs, data) - read/write GT64120 registers in 32bit
*
* TIMER - gt64120 timer irq, temporary solution until
* full gt64120 cascade interrupt support is in place
*/
#include <mach-gt64120.h>
/*
* Because of an error/peculiarity in the Galileo chip, we need to swap the
* bytes when running bigendian. We also provide non-swapping versions.
*/
#define __GT_READ(ofs) \
(*(volatile u32 *)(GT64120_BASE+(ofs)))
#define __GT_WRITE(ofs, data) \
do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
#define GT_READ(ofs) le32_to_cpu(__GT_READ(ofs))
#define GT_WRITE(ofs, data) __GT_WRITE(ofs, cpu_to_le32(data))
#endif /* _ASM_GT64120_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1997, 1998, 1999, 2000, 2001 by Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
* Copyright (C) 2001 MIPS Technologies, Inc.
*/
#ifndef _ASM_HARDIRQ_H
#define _ASM_HARDIRQ_H
#include <linux/config.h>
#include <linux/threads.h>
#include <linux/irq.h>
typedef struct {
unsigned int __softirq_pending;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
extern void ack_bad_irq(unsigned int irq);
#endif /* _ASM_HARDIRQ_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
*/
#ifndef _ASM_HAZARDS_H
#define _ASM_HAZARDS_H
#include <linux/config.h>
#ifdef __ASSEMBLY__
.macro _ssnop
sll $0, $0, 1
.endm
/*
* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
* use of the JTLB for instructions should not occur for 4 cpu cycles and use
* for data translations should not occur for 3 cpu cycles.
*/
#ifdef CONFIG_CPU_RM9000
#define mtc0_tlbw_hazard \
.set push; \
.set mips32; \
_ssnop; _ssnop; _ssnop; _ssnop; \
.set pop
#define tlbw_eret_hazard \
.set push; \
.set mips32; \
_ssnop; _ssnop; _ssnop; _ssnop; \
.set pop
#else
/*
* The taken branch will result in a two cycle penalty for the two killed
* instructions on R4000 / R4400. Other processors only have a single cycle
* hazard so this is nice trick to have an optimal code for a range of
* processors.
*/
#define mtc0_tlbw_hazard \
b . + 8
#define tlbw_eret_hazard
#endif
/*
* mtc0->mfc0 hazard
* The 24K has a 2 cycle mtc0/mfc0 execution hazard.
* It is a MIPS32R2 processor so ehb will clear the hazard.
*/
#ifdef CONFIG_CPU_MIPSR2
/*
* Use a macro for ehb unless explicit support for MIPSR2 is enabled
*/
.macro ehb
sll $0, $0, 3
.endm
#define irq_enable_hazard \
ehb # irq_enable_hazard
#define irq_disable_hazard \
ehb # irq_disable_hazard
#else
#define irq_enable_hazard
#define irq_disable_hazard
#endif
#else /* __ASSEMBLY__ */
/*
* RM9000 hazards. When the JTLB is updated by tlbwi or tlbwr, a subsequent
* use of the JTLB for instructions should not occur for 4 cpu cycles and use
* for data translations should not occur for 3 cpu cycles.
*/
#ifdef CONFIG_CPU_RM9000
#define mtc0_tlbw_hazard() \
__asm__ __volatile__( \
".set\tmips32\n\t" \
"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
".set\tmips0")
#define tlbw_use_hazard() \
__asm__ __volatile__( \
".set\tmips32\n\t" \
"_ssnop; _ssnop; _ssnop; _ssnop\n\t" \
".set\tmips0")
#else
/*
* Overkill warning ...
*/
#define mtc0_tlbw_hazard() \
__asm__ __volatile__( \
".set noreorder\n\t" \
"nop; nop; nop; nop; nop; nop;\n\t" \
".set reorder\n\t")
#define tlbw_use_hazard() \
__asm__ __volatile__( \
".set noreorder\n\t" \
"nop; nop; nop; nop; nop; nop;\n\t" \
".set reorder\n\t")
#endif
/*
* mtc0->mfc0 hazard
* The 24K has a 2 cycle mtc0/mfc0 execution hazard.
* It is a MIPS32R2 processor so ehb will clear the hazard.
*/
#ifdef CONFIG_CPU_MIPSR2
/*
* Use a macro for ehb unless explicit support for MIPSR2 is enabled
*/
__asm__(
" .macro ehb \n\t"
" sll $0, $0, 3 \n\t"
" .endm \n\t"
" \n\t"
" .macro\tirq_enable_hazard \n\t"
" ehb \n\t"
" .endm \n\t"
" \n\t"
" .macro\tirq_disable_hazard \n\t"
" ehb \n\t"
" .endm");
#define irq_enable_hazard() \
__asm__ __volatile__( \
"ehb\t\t\t\t# irq_enable_hazard")
#define irq_disable_hazard() \
__asm__ __volatile__( \
"ehb\t\t\t\t# irq_disable_hazard")
#elif defined(CONFIG_CPU_R10000)
/*
* R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
*/
__asm__(
" .macro\tirq_enable_hazard \n\t"
" .endm \n\t"
" \n\t"
" .macro\tirq_disable_hazard \n\t"
" .endm");
#define irq_enable_hazard() do { } while (0)
#define irq_disable_hazard() do { } while (0)
#else
/*
* Default for classic MIPS processors. Assume worst case hazards but don't
* care about the irq_enable_hazard - sooner or later the hardware will
* enable it and we don't care when exactly.
*/
__asm__(
" .macro _ssnop \n\t"
" sll $0, $2, 1 \n\t"
" .endm \n\t"
" \n\t"
" # \n\t"
" # There is a hazard but we do not care \n\t"
" # \n\t"
" .macro\tirq_enable_hazard \n\t"
" .endm \n\t"
" \n\t"
" .macro\tirq_disable_hazard \n\t"
" _ssnop; _ssnop; _ssnop \n\t"
" .endm");
#define irq_enable_hazard() do { } while (0)
#define irq_disable_hazard() \
__asm__ __volatile__( \
"_ssnop; _ssnop; _ssnop;\t\t# irq_disable_hazard")
#endif
#endif /* __ASSEMBLY__ */
#endif /* _ASM_HAZARDS_H */

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#warning this file is obsolete, please do not use it

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/*
* highmem.h: virtual kernel memory mappings for high memory
*
* Used in CONFIG_HIGHMEM systems for memory pages which
* are not addressable by direct kernel virtual addresses.
*
* Copyright (C) 1999 Gerhard Wichert, Siemens AG
* Gerhard.Wichert@pdb.siemens.de
*
*
* Redesigned the x86 32-bit VM architecture to deal with
* up to 16 Terabyte physical memory. With current x86 CPUs
* we now support up to 64 Gigabytes physical RAM.
*
* Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
*/
#ifndef _ASM_HIGHMEM_H
#define _ASM_HIGHMEM_H
#ifdef __KERNEL__
#include <linux/config.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/kmap_types.h>
/* undef for production */
#define HIGHMEM_DEBUG 1
/* declarations for highmem.c */
extern unsigned long highstart_pfn, highend_pfn;
extern pte_t *kmap_pte;
extern pgprot_t kmap_prot;
extern pte_t *pkmap_page_table;
/*
* Right now we initialize only a single pte table. It can be extended
* easily, subsequent pte tables have to be allocated in one physical
* chunk of RAM.
*/
#define PKMAP_BASE (0xfe000000UL)
#define LAST_PKMAP 1024
#define LAST_PKMAP_MASK (LAST_PKMAP-1)
#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
extern void * kmap_high(struct page *page);
extern void kunmap_high(struct page *page);
/*
* CONFIG_LIMITED_DMA is for systems with DMA limitations such as Momentum's
* Jaguar ATX. This option exploits the highmem code in the kernel so is
* always enabled together with CONFIG_HIGHMEM but at this time doesn't
* actually add highmem functionality.
*/
#ifdef CONFIG_LIMITED_DMA
/*
* These are the default functions for the no-highmem case from
* <linux/highmem.h>
*/
static inline void *kmap(struct page *page)
{
might_sleep();
return page_address(page);
}
#define kunmap(page) do { (void) (page); } while (0)
static inline void *kmap_atomic(struct page *page, enum km_type type)
{
return page_address(page);
}
static inline void kunmap_atomic(void *kvaddr, enum km_type type) { }
#define kmap_atomic_to_page(ptr) virt_to_page(ptr)
#define flush_cache_kmaps() do { } while (0)
#else /* LIMITED_DMA */
extern void *__kmap(struct page *page);
extern void __kunmap(struct page *page);
extern void *__kmap_atomic(struct page *page, enum km_type type);
extern void __kunmap_atomic(void *kvaddr, enum km_type type);
extern struct page *__kmap_atomic_to_page(void *ptr);
#define kmap __kmap
#define kunmap __kunmap
#define kmap_atomic __kmap_atomic
#define kunmap_atomic __kunmap_atomic
#define kmap_atomic_to_page __kmap_atomic_to_page
#define flush_cache_kmaps() flush_cache_all()
#endif /* LIMITED_DMA */
#endif /* __KERNEL__ */
#endif /* _ASM_HIGHMEM_H */

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typedef enum { IllegalAsic, UnknownAsic, AndrosAsic, HarmonyAsic } AsicId;
AsicId GetAsicId(void);
const char* const GetAsicName(void);

27
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000, 2001, 2002 by Ralf Baechle
*/
#ifndef __ASM_HW_IRQ_H
#define __ASM_HW_IRQ_H
#include <linux/profile.h>
#include <asm/atomic.h>
extern void disable_8259A_irq(unsigned int irq);
extern void enable_8259A_irq(unsigned int irq);
extern int i8259A_irq_pending(unsigned int irq);
extern void make_8259A_irq(unsigned int irq);
extern void init_8259A(int aeoi);
extern atomic_t irq_err_count;
/* This may not be apropriate for all machines, we'll see ... */
static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i)
{
}
#endif /* __ASM_HW_IRQ_H */

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/*
* include/asm-mips/i8259.h
*
* i8259A interrupt definitions.
*
* Copyright (C) 2003 Maciej W. Rozycki
* Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_I8259_H
#define _ASM_I8259_H
#include <linux/compiler.h>
#include <linux/spinlock.h>
#include <asm/io.h>
extern spinlock_t i8259A_lock;
extern void init_i8259_irqs(void);
/*
* Do the traditional i8259 interrupt polling thing. This is for the few
* cases where no better interrupt acknowledge method is available and we
* absolutely must touch the i8259.
*/
static inline int i8259_irq(void)
{
int irq;
spin_lock(&i8259A_lock);
/* Perform an interrupt acknowledge cycle on controller 1. */
outb(0x0C, 0x20); /* prepare for poll */
irq = inb(0x20) & 7;
if (irq == 2) {
/*
* Interrupt is cascaded so perform interrupt
* acknowledge on controller 2.
*/
outb(0x0C, 0xA0); /* prepare for poll */
irq = (inb(0xA0) & 7) + 8;
}
if (unlikely(irq == 7)) {
/*
* This may be a spurious interrupt.
*
* Read the interrupt status register (ISR). If the most
* significant bit is not set then there is no valid
* interrupt.
*/
outb(0x0B, 0x20); /* ISR register */
if(~inb(0x20) & 0x80)
irq = -1;
}
spin_unlock(&i8259A_lock);
return irq;
}
#endif /* _ASM_I8259_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* This file contains the MIPS architecture specific IDE code.
*/
#ifndef __ASM_IDE_H
#define __ASM_IDE_H
#include <ide.h>
#endif /* __ASM_IDE_H */

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/*
* Format of an instruction in memory.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1996, 2000 by Ralf Baechle
*/
#ifndef _ASM_INST_H
#define _ASM_INST_H
/*
* Major opcodes; before MIPS IV cop1x was called cop3.
*/
enum major_op {
spec_op, bcond_op, j_op, jal_op,
beq_op, bne_op, blez_op, bgtz_op,
addi_op, addiu_op, slti_op, sltiu_op,
andi_op, ori_op, xori_op, lui_op,
cop0_op, cop1_op, cop2_op, cop1x_op,
beql_op, bnel_op, blezl_op, bgtzl_op,
daddi_op, daddiu_op, ldl_op, ldr_op,
major_1c_op, jalx_op, major_1e_op, major_1f_op,
lb_op, lh_op, lwl_op, lw_op,
lbu_op, lhu_op, lwr_op, lwu_op,
sb_op, sh_op, swl_op, sw_op,
sdl_op, sdr_op, swr_op, cache_op,
ll_op, lwc1_op, lwc2_op, pref_op,
lld_op, ldc1_op, ldc2_op, ld_op,
sc_op, swc1_op, swc2_op, major_3b_op, /* Opcode 0x3b is unused */
scd_op, sdc1_op, sdc2_op, sd_op
};
/*
* func field of spec opcode.
*/
enum spec_op {
sll_op, movc_op, srl_op, sra_op,
sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */
jr_op, jalr_op, movz_op, movn_op,
syscall_op, break_op, spim_op, sync_op,
mfhi_op, mthi_op, mflo_op, mtlo_op,
dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
mult_op, multu_op, div_op, divu_op,
dmult_op, dmultu_op, ddiv_op, ddivu_op,
add_op, addu_op, sub_op, subu_op,
and_op, or_op, xor_op, nor_op,
spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
dadd_op, daddu_op, dsub_op, dsubu_op,
tge_op, tgeu_op, tlt_op, tltu_op,
teq_op, spec5_unused_op, tne_op, spec6_unused_op,
dsll_op, spec7_unused_op, dsrl_op, dsra_op,
dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
};
/*
* rt field of bcond opcodes.
*/
enum rt_op {
bltz_op, bgez_op, bltzl_op, bgezl_op,
spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
tgei_op, tgeiu_op, tlti_op, tltiu_op,
teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
bltzal_op, bgezal_op, bltzall_op, bgezall_op
/*
* The others (0x14 - 0x1f) are unused.
*/
};
/*
* rs field of cop opcodes.
*/
enum cop_op {
mfc_op = 0x00, dmfc_op = 0x01,
cfc_op = 0x02, mtc_op = 0x04,
dmtc_op = 0x05, ctc_op = 0x06,
bc_op = 0x08, cop_op = 0x10,
copm_op = 0x18
};
/*
* rt field of cop.bc_op opcodes
*/
enum bcop_op {
bcf_op, bct_op, bcfl_op, bctl_op
};
/*
* func field of cop0 coi opcodes.
*/
enum cop0_coi_func {
tlbr_op = 0x01, tlbwi_op = 0x02,
tlbwr_op = 0x06, tlbp_op = 0x08,
rfe_op = 0x10, eret_op = 0x18
};
/*
* func field of cop0 com opcodes.
*/
enum cop0_com_func {
tlbr1_op = 0x01, tlbw_op = 0x02,
tlbp1_op = 0x08, dctr_op = 0x09,
dctw_op = 0x0a
};
/*
* fmt field of cop1 opcodes.
*/
enum cop1_fmt {
s_fmt, d_fmt, e_fmt, q_fmt,
w_fmt, l_fmt
};
/*
* func field of cop1 instructions using d, s or w format.
*/
enum cop1_sdw_func {
fadd_op = 0x00, fsub_op = 0x01,
fmul_op = 0x02, fdiv_op = 0x03,
fsqrt_op = 0x04, fabs_op = 0x05,
fmov_op = 0x06, fneg_op = 0x07,
froundl_op = 0x08, ftruncl_op = 0x09,
fceill_op = 0x0a, ffloorl_op = 0x0b,
fround_op = 0x0c, ftrunc_op = 0x0d,
fceil_op = 0x0e, ffloor_op = 0x0f,
fmovc_op = 0x11, fmovz_op = 0x12,
fmovn_op = 0x13, frecip_op = 0x15,
frsqrt_op = 0x16, fcvts_op = 0x20,
fcvtd_op = 0x21, fcvte_op = 0x22,
fcvtw_op = 0x24, fcvtl_op = 0x25,
fcmp_op = 0x30
};
/*
* func field of cop1x opcodes (MIPS IV).
*/
enum cop1x_func {
lwxc1_op = 0x00, ldxc1_op = 0x01,
pfetch_op = 0x07, swxc1_op = 0x08,
sdxc1_op = 0x09, madd_s_op = 0x20,
madd_d_op = 0x21, madd_e_op = 0x22,
msub_s_op = 0x28, msub_d_op = 0x29,
msub_e_op = 0x2a, nmadd_s_op = 0x30,
nmadd_d_op = 0x31, nmadd_e_op = 0x32,
nmsub_s_op = 0x38, nmsub_d_op = 0x39,
nmsub_e_op = 0x3a
};
/*
* func field for mad opcodes (MIPS IV).
*/
enum mad_func {
madd_op = 0x08, msub_op = 0x0a,
nmadd_op = 0x0c, nmsub_op = 0x0e
};
/*
* Damn ... bitfields depend from byteorder :-(
*/
#ifdef __MIPSEB__
struct j_format { /* Jump format */
unsigned int opcode : 6;
unsigned int target : 26;
};
struct i_format { /* Immediate format (addi, lw, ...) */
unsigned int opcode : 6;
unsigned int rs : 5;
unsigned int rt : 5;
signed int simmediate : 16;
};
struct u_format { /* Unsigned immediate format (ori, xori, ...) */
unsigned int opcode : 6;
unsigned int rs : 5;
unsigned int rt : 5;
unsigned int uimmediate : 16;
};
struct c_format { /* Cache (>= R6000) format */
unsigned int opcode : 6;
unsigned int rs : 5;
unsigned int c_op : 3;
unsigned int cache : 2;
unsigned int simmediate : 16;
};
struct r_format { /* Register format */
unsigned int opcode : 6;
unsigned int rs : 5;
unsigned int rt : 5;
unsigned int rd : 5;
unsigned int re : 5;
unsigned int func : 6;
};
struct p_format { /* Performance counter format (R10000) */
unsigned int opcode : 6;
unsigned int rs : 5;
unsigned int rt : 5;
unsigned int rd : 5;
unsigned int re : 5;
unsigned int func : 6;
};
struct f_format { /* FPU register format */
unsigned int opcode : 6;
unsigned int : 1;
unsigned int fmt : 4;
unsigned int rt : 5;
unsigned int rd : 5;
unsigned int re : 5;
unsigned int func : 6;
};
struct ma_format { /* FPU multipy and add format (MIPS IV) */
unsigned int opcode : 6;
unsigned int fr : 5;
unsigned int ft : 5;
unsigned int fs : 5;
unsigned int fd : 5;
unsigned int func : 4;
unsigned int fmt : 2;
};
#elif defined(__MIPSEL__)
struct j_format { /* Jump format */
unsigned int target : 26;
unsigned int opcode : 6;
};
struct i_format { /* Immediate format */
signed int simmediate : 16;
unsigned int rt : 5;
unsigned int rs : 5;
unsigned int opcode : 6;
};
struct u_format { /* Unsigned immediate format */
unsigned int uimmediate : 16;
unsigned int rt : 5;
unsigned int rs : 5;
unsigned int opcode : 6;
};
struct c_format { /* Cache (>= R6000) format */
unsigned int simmediate : 16;
unsigned int cache : 2;
unsigned int c_op : 3;
unsigned int rs : 5;
unsigned int opcode : 6;
};
struct r_format { /* Register format */
unsigned int func : 6;
unsigned int re : 5;
unsigned int rd : 5;
unsigned int rt : 5;
unsigned int rs : 5;
unsigned int opcode : 6;
};
struct p_format { /* Performance counter format (R10000) */
unsigned int func : 6;
unsigned int re : 5;
unsigned int rd : 5;
unsigned int rt : 5;
unsigned int rs : 5;
unsigned int opcode : 6;
};
struct f_format { /* FPU register format */
unsigned int func : 6;
unsigned int re : 5;
unsigned int rd : 5;
unsigned int rt : 5;
unsigned int fmt : 4;
unsigned int : 1;
unsigned int opcode : 6;
};
struct ma_format { /* FPU multipy and add format (MIPS IV) */
unsigned int fmt : 2;
unsigned int func : 4;
unsigned int fd : 5;
unsigned int fs : 5;
unsigned int ft : 5;
unsigned int fr : 5;
unsigned int opcode : 6;
};
#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
#endif
union mips_instruction {
unsigned int word;
unsigned short halfword[2];
unsigned char byte[4];
struct j_format j_format;
struct i_format i_format;
struct u_format u_format;
struct c_format c_format;
struct r_format r_format;
struct f_format f_format;
struct ma_format ma_format;
};
/* HACHACHAHCAHC ... */
/* In case some other massaging is needed, keep MIPSInst as wrapper */
#define MIPSInst(x) x
#define I_OPCODE_SFT 26
#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
#define I_JTARGET_SFT 0
#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
#define I_RS_SFT 21
#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
#define I_RT_SFT 16
#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
#define I_IMM_SFT 0
#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
#define I_CACHEOP_SFT 18
#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
#define I_CACHESEL_SFT 16
#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
#define I_RD_SFT 11
#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
#define I_RE_SFT 6
#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
#define I_FUNC_SFT 0
#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
#define I_FFMT_SFT 21
#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
#define I_FT_SFT 16
#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
#define I_FS_SFT 11
#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
#define I_FD_SFT 6
#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
#define I_FR_SFT 21
#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
#define I_FMA_FUNC_SFT 2
#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
#define I_FMA_FFMT_SFT 0
#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
typedef unsigned int mips_instruction;
#endif /* _ASM_INST_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
* Copyright (C) 1996 by Paul M. Antoine
* Copyright (C) 1999 Silicon Graphics
* Copyright (C) 2000 MIPS Technologies, Inc.
*/
#ifndef _ASM_INTERRUPT_H
#define _ASM_INTERRUPT_H
#include <asm/hazards.h>
__asm__ (
".macro\tlocal_irq_enable\n\t"
".set\tpush\n\t"
".set\treorder\n\t"
".set\tnoat\n\t"
"mfc0\t$1,$12\n\t"
"ori\t$1,0x1f\n\t"
"xori\t$1,0x1e\n\t"
"mtc0\t$1,$12\n\t"
"irq_enable_hazard\n\t"
".set\tpop\n\t"
".endm");
static inline void local_irq_enable(void)
{
__asm__ __volatile__(
"local_irq_enable"
: /* no outputs */
: /* no inputs */
: "memory");
}
/*
* For cli() we have to insert nops to make sure that the new value
* has actually arrived in the status register before the end of this
* macro.
* R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
* no nops at all.
*/
__asm__ (
".macro\tlocal_irq_disable\n\t"
".set\tpush\n\t"
".set\tnoat\n\t"
"mfc0\t$1,$12\n\t"
"ori\t$1,1\n\t"
"xori\t$1,1\n\t"
".set\tnoreorder\n\t"
"mtc0\t$1,$12\n\t"
"irq_disable_hazard\n\t"
".set\tpop\n\t"
".endm");
static inline void local_irq_disable(void)
{
__asm__ __volatile__(
"local_irq_disable"
: /* no outputs */
: /* no inputs */
: "memory");
}
__asm__ (
".macro\tlocal_save_flags flags\n\t"
".set\tpush\n\t"
".set\treorder\n\t"
"mfc0\t\\flags, $12\n\t"
".set\tpop\n\t"
".endm");
#define local_save_flags(x) \
__asm__ __volatile__( \
"local_save_flags %0" \
: "=r" (x))
__asm__ (
".macro\tlocal_irq_save result\n\t"
".set\tpush\n\t"
".set\treorder\n\t"
".set\tnoat\n\t"
"mfc0\t\\result, $12\n\t"
"ori\t$1, \\result, 1\n\t"
"xori\t$1, 1\n\t"
".set\tnoreorder\n\t"
"mtc0\t$1, $12\n\t"
"irq_disable_hazard\n\t"
".set\tpop\n\t"
".endm");
#define local_irq_save(x) \
__asm__ __volatile__( \
"local_irq_save\t%0" \
: "=r" (x) \
: /* no inputs */ \
: "memory")
__asm__ (
".macro\tlocal_irq_restore flags\n\t"
".set\tnoreorder\n\t"
".set\tnoat\n\t"
"mfc0\t$1, $12\n\t"
"andi\t\\flags, 1\n\t"
"ori\t$1, 1\n\t"
"xori\t$1, 1\n\t"
"or\t\\flags, $1\n\t"
"mtc0\t\\flags, $12\n\t"
"irq_disable_hazard\n\t"
".set\tat\n\t"
".set\treorder\n\t"
".endm");
#define local_irq_restore(flags) \
do { \
unsigned long __tmp1; \
\
__asm__ __volatile__( \
"local_irq_restore\t%0" \
: "=r" (__tmp1) \
: "0" (flags) \
: "memory"); \
} while(0)
#define irqs_disabled() \
({ \
unsigned long flags; \
local_save_flags(flags); \
!(flags & 1); \
})
#endif /* _ASM_INTERRUPT_H */

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/*
* Miguel de Icaza
*/
#ifndef __ASM_INVENTORY_H
#define __ASM_INVENTORY_H
typedef struct inventory_s {
struct inventory_s *inv_next;
int inv_class;
int inv_type;
int inv_controller;
int inv_unit;
int inv_state;
} inventory_t;
extern int inventory_items;
void add_to_inventory (int class, int type, int controller, int unit, int state);
int dump_inventory_to_user (void *userbuf, int size);
#endif /* __ASM_INVENTORY_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994, 1995 Waldorf GmbH
* Copyright (C) 1994 - 2000 Ralf Baechle
* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
*/
#ifndef _ASM_IO_H
#define _ASM_IO_H
#include <linux/config.h>
#include <linux/compiler.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm/page.h>
#include <asm/pgtable-bits.h>
#include <asm/processor.h>
#include <asm/byteorder.h>
#include <mangle-port.h>
/*
* Slowdown I/O port space accesses for antique hardware.
*/
#undef CONF_SLOWDOWN_IO
/*
* Sane hardware offers swapping of I/O space accesses in hardware; less
* sane hardware forces software to fiddle with this ...
*/
#if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
#define __ioswab8(x) (x)
#ifdef CONFIG_SGI_IP22
/*
* IP22 seems braindead enough to swap 16bits values in hardware, but
* not 32bits. Go figure... Can't tell without documentation.
*/
#define __ioswab16(x) (x)
#else
#define __ioswab16(x) swab16(x)
#endif
#define __ioswab32(x) swab32(x)
#define __ioswab64(x) swab64(x)
#else
#define __ioswab8(x) (x)
#define __ioswab16(x) (x)
#define __ioswab32(x) (x)
#define __ioswab64(x) (x)
#endif
#define IO_SPACE_LIMIT 0xffff
/*
* On MIPS I/O ports are memory mapped, so we access them using normal
* load/store instructions. mips_io_port_base is the virtual address to
* which all ports are being mapped. For sake of efficiency some code
* assumes that this is an address that can be loaded with a single lui
* instruction, so the lower 16 bits must be zero. Should be true on
* on any sane architecture; generic code does not use this assumption.
*/
extern const unsigned long mips_io_port_base;
#define set_io_port_base(base) \
do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
/*
* Thanks to James van Artsdalen for a better timing-fix than
* the two short jumps: using outb's to a nonexistent port seems
* to guarantee better timings even on fast machines.
*
* On the other hand, I'd like to be sure of a non-existent port:
* I feel a bit unsafe about using 0x80 (should be safe, though)
*
* Linus
*
*/
#define __SLOW_DOWN_IO \
__asm__ __volatile__( \
"sb\t$0,0x80(%0)" \
: : "r" (mips_io_port_base));
#ifdef CONF_SLOWDOWN_IO
#ifdef REALLY_SLOW_IO
#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
#else
#define SLOW_DOWN_IO __SLOW_DOWN_IO
#endif
#else
#define SLOW_DOWN_IO
#endif
/*
* virt_to_phys - map virtual addresses to physical
* @address: address to remap
*
* The returned physical address is the physical (CPU) mapping for
* the memory address given. It is only valid to use this function on
* addresses directly mapped or allocated via kmalloc.
*
* This function does not give bus mappings for DMA transfers. In
* almost all conceivable cases a device driver should not be using
* this function
*/
static inline unsigned long virt_to_phys(volatile void * address)
{
return (unsigned long)address - PAGE_OFFSET;
}
/*
* phys_to_virt - map physical address to virtual
* @address: address to remap
*
* The returned virtual address is a current CPU mapping for
* the memory address given. It is only valid to use this function on
* addresses that have a kernel mapping
*
* This function does not handle bus mappings for DMA transfers. In
* almost all conceivable cases a device driver should not be using
* this function
*/
static inline void * phys_to_virt(unsigned long address)
{
return (void *)(address + PAGE_OFFSET);
}
/*
* ISA I/O bus memory addresses are 1:1 with the physical address.
*/
static inline unsigned long isa_virt_to_bus(volatile void * address)
{
return (unsigned long)address - PAGE_OFFSET;
}
static inline void * isa_bus_to_virt(unsigned long address)
{
return (void *)(address + PAGE_OFFSET);
}
#define isa_page_to_bus page_to_phys
/*
* However PCI ones are not necessarily 1:1 and therefore these interfaces
* are forbidden in portable PCI drivers.
*
* Allow them for x86 for legacy drivers, though.
*/
#define virt_to_bus virt_to_phys
#define bus_to_virt phys_to_virt
/*
* isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
* for the processor. This implies the assumption that there is only
* one of these busses.
*/
extern unsigned long isa_slot_offset;
/*
* Change "struct page" to physical address.
*/
#define page_to_phys(page) ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
extern void __iounmap(volatile void __iomem *addr);
static inline void * __ioremap_mode(phys_t offset, unsigned long size,
unsigned long flags)
{
if (cpu_has_64bit_addresses) {
u64 base = UNCAC_BASE;
/*
* R10000 supports a 2 bit uncached attribute therefore
* UNCAC_BASE may not equal IO_BASE.
*/
if (flags == _CACHE_UNCACHED)
base = (u64) IO_BASE;
return (void *) (unsigned long) (base + offset);
}
return __ioremap(offset, size, flags);
}
/*
* ioremap - map bus memory into CPU space
* @offset: bus address of the memory
* @size: size of the resource to map
*
* ioremap performs a platform specific sequence of operations to
* make bus memory CPU accessible via the readb/readw/readl/writeb/
* writew/writel functions and the other mmio helpers. The returned
* address is not guaranteed to be usable directly as a virtual
* address.
*/
#define ioremap(offset, size) \
__ioremap_mode((offset), (size), _CACHE_UNCACHED)
/*
* ioremap_nocache - map bus memory into CPU space
* @offset: bus address of the memory
* @size: size of the resource to map
*
* ioremap_nocache performs a platform specific sequence of operations to
* make bus memory CPU accessible via the readb/readw/readl/writeb/
* writew/writel functions and the other mmio helpers. The returned
* address is not guaranteed to be usable directly as a virtual
* address.
*
* This version of ioremap ensures that the memory is marked uncachable
* on the CPU as well as honouring existing caching rules from things like
* the PCI bus. Note that there are other caches and buffers on many
* busses. In paticular driver authors should read up on PCI writes
*
* It's useful if some control registers are in such an area and
* write combining or read caching is not desirable:
*/
#define ioremap_nocache(offset, size) \
__ioremap_mode((offset), (size), _CACHE_UNCACHED)
/*
* These two are MIPS specific ioremap variant. ioremap_cacheable_cow
* requests a cachable mapping, ioremap_uncached_accelerated requests a
* mapping using the uncached accelerated mode which isn't supported on
* all processors.
*/
#define ioremap_cacheable_cow(offset, size) \
__ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
#define ioremap_uncached_accelerated(offset, size) \
__ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
static inline void iounmap(volatile void __iomem *addr)
{
if (cpu_has_64bits)
return;
__iounmap(addr);
}
#define __raw_readb(addr) \
(*(volatile unsigned char *) __swizzle_addr_b((unsigned long)(addr)))
#define __raw_readw(addr) \
(*(volatile unsigned short *) __swizzle_addr_w((unsigned long)(addr)))
#define __raw_readl(addr) \
(*(volatile unsigned int *) __swizzle_addr_l((unsigned long)(addr)))
#ifdef CONFIG_MIPS32
#define ____raw_readq(addr) \
({ \
u64 __res; \
\
__asm__ __volatile__ ( \
" .set mips3 # ____raw_readq \n" \
" ld %L0, (%1) \n" \
" dsra32 %M0, %L0, 0 \n" \
" sll %L0, %L0, 0 \n" \
" .set mips0 \n" \
: "=r" (__res) \
: "r" (__swizzle_addr_q((unsigned long)(addr)))); \
__res; \
})
#define __raw_readq(addr) \
({ \
unsigned long __flags; \
u64 __res; \
\
local_irq_save(__flags); \
__res = ____raw_readq(addr); \
local_irq_restore(__flags); \
__res; \
})
#endif
#ifdef CONFIG_MIPS64
#define ____raw_readq(addr) \
(*(volatile unsigned long *)__swizzle_addr_q((unsigned long)(addr)))
#define __raw_readq(addr) ____raw_readq(addr)
#endif
#define readb(addr) __ioswab8(__raw_readb(addr))
#define readw(addr) __ioswab16(__raw_readw(addr))
#define readl(addr) __ioswab32(__raw_readl(addr))
#define readq(addr) __ioswab64(__raw_readq(addr))
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
#define readq_relaxed(addr) readq(addr)
#define __raw_writeb(b,addr) \
do { \
((*(volatile unsigned char *)__swizzle_addr_b((unsigned long)(addr))) = (b)); \
} while (0)
#define __raw_writew(w,addr) \
do { \
((*(volatile unsigned short *)__swizzle_addr_w((unsigned long)(addr))) = (w)); \
} while (0)
#define __raw_writel(l,addr) \
do { \
((*(volatile unsigned int *)__swizzle_addr_l((unsigned long)(addr))) = (l)); \
} while (0)
#ifdef CONFIG_MIPS32
#define ____raw_writeq(val,addr) \
do { \
u64 __tmp; \
\
__asm__ __volatile__ ( \
" .set mips3 \n" \
" dsll32 %L0, %L0, 0 # ____raw_writeq\n" \
" dsrl32 %L0, %L0, 0 \n" \
" dsll32 %M0, %M0, 0 \n" \
" or %L0, %L0, %M0 \n" \
" sd %L0, (%2) \n" \
" .set mips0 \n" \
: "=r" (__tmp) \
: "0" ((unsigned long long)val), \
"r" (__swizzle_addr_q((unsigned long)(addr)))); \
} while (0)
#define __raw_writeq(val,addr) \
do { \
unsigned long __flags; \
\
local_irq_save(__flags); \
____raw_writeq(val, addr); \
local_irq_restore(__flags); \
} while (0)
#endif
#ifdef CONFIG_MIPS64
#define ____raw_writeq(q,addr) \
do { \
*(volatile unsigned long *)__swizzle_addr_q((unsigned long)(addr)) = (q); \
} while (0)
#define __raw_writeq(q,addr) ____raw_writeq(q, addr)
#endif
#define writeb(b,addr) __raw_writeb(__ioswab8(b),(addr))
#define writew(w,addr) __raw_writew(__ioswab16(w),(addr))
#define writel(l,addr) __raw_writel(__ioswab32(l),(addr))
#define writeq(q,addr) __raw_writeq(__ioswab64(q),(addr))
/* Depends on MIPS II instruction set */
#define mmiowb() asm volatile ("sync" ::: "memory")
#define memset_io(a,b,c) memset((void *)(a),(b),(c))
#define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
#define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
/*
* ISA space is 'always mapped' on currently supported MIPS systems, no need
* to explicitly ioremap() it. The fact that the ISA IO space is mapped
* to PAGE_OFFSET is pure coincidence - it does not mean ISA values
* are physical addresses. The following constant pointer can be
* used as the IO-area pointer (it can be iounmapped as well, so the
* analogy with PCI is quite large):
*/
#define __ISA_IO_base ((char *)(isa_slot_offset))
#define isa_readb(a) readb(__ISA_IO_base + (a))
#define isa_readw(a) readw(__ISA_IO_base + (a))
#define isa_readl(a) readl(__ISA_IO_base + (a))
#define isa_readq(a) readq(__ISA_IO_base + (a))
#define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
#define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
#define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
#define isa_writeq(q,a) writeq(q,__ISA_IO_base + (a))
#define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
#define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
#define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
/*
* We don't have csum_partial_copy_fromio() yet, so we cheat here and
* just copy it. The net code will then do the checksum later.
*/
#define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
#define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
/*
* check_signature - find BIOS signatures
* @io_addr: mmio address to check
* @signature: signature block
* @length: length of signature
*
* Perform a signature comparison with the mmio address io_addr. This
* address should have been obtained by ioremap.
* Returns 1 on a match.
*/
static inline int check_signature(unsigned long io_addr,
const unsigned char *signature, int length)
{
int retval = 0;
do {
if (readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
static inline void __outb(unsigned char val, unsigned long port)
{
port = __swizzle_addr_b(port);
*(volatile u8 *)(mips_io_port_base + port) = __ioswab8(val);
}
static inline void __outw(unsigned short val, unsigned long port)
{
port = __swizzle_addr_w(port);
*(volatile u16 *)(mips_io_port_base + port) = __ioswab16(val);
}
static inline void __outl(unsigned int val, unsigned long port)
{
port = __swizzle_addr_l(port);
*(volatile u32 *)(mips_io_port_base + port) = __ioswab32(val);
}
static inline void __outb_p(unsigned char val, unsigned long port)
{
port = __swizzle_addr_b(port);
*(volatile u8 *)(mips_io_port_base + port) = __ioswab8(val);
SLOW_DOWN_IO;
}
static inline void __outw_p(unsigned short val, unsigned long port)
{
port = __swizzle_addr_w(port);
*(volatile u16 *)(mips_io_port_base + port) = __ioswab16(val);
SLOW_DOWN_IO;
}
static inline void __outl_p(unsigned int val, unsigned long port)
{
port = __swizzle_addr_l(port);
*(volatile u32 *)(mips_io_port_base + port) = __ioswab32(val);
SLOW_DOWN_IO;
}
#define outb(val, port) __outb(val, port)
#define outw(val, port) __outw(val, port)
#define outl(val, port) __outl(val, port)
#define outb_p(val, port) __outb_p(val, port)
#define outw_p(val, port) __outw_p(val, port)
#define outl_p(val, port) __outl_p(val, port)
static inline unsigned char __inb(unsigned long port)
{
port = __swizzle_addr_b(port);
return __ioswab8(*(volatile u8 *)(mips_io_port_base + port));
}
static inline unsigned short __inw(unsigned long port)
{
port = __swizzle_addr_w(port);
return __ioswab16(*(volatile u16 *)(mips_io_port_base + port));
}
static inline unsigned int __inl(unsigned long port)
{
port = __swizzle_addr_l(port);
return __ioswab32(*(volatile u32 *)(mips_io_port_base + port));
}
static inline unsigned char __inb_p(unsigned long port)
{
u8 __val;
port = __swizzle_addr_b(port);
__val = *(volatile u8 *)(mips_io_port_base + port);
SLOW_DOWN_IO;
return __ioswab8(__val);
}
static inline unsigned short __inw_p(unsigned long port)
{
u16 __val;
port = __swizzle_addr_w(port);
__val = *(volatile u16 *)(mips_io_port_base + port);
SLOW_DOWN_IO;
return __ioswab16(__val);
}
static inline unsigned int __inl_p(unsigned long port)
{
u32 __val;
port = __swizzle_addr_l(port);
__val = *(volatile u32 *)(mips_io_port_base + port);
SLOW_DOWN_IO;
return __ioswab32(__val);
}
#define inb(port) __inb(port)
#define inw(port) __inw(port)
#define inl(port) __inl(port)
#define inb_p(port) __inb_p(port)
#define inw_p(port) __inw_p(port)
#define inl_p(port) __inl_p(port)
static inline void __outsb(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
outb(*(u8 *)addr, port);
addr++;
}
}
static inline void __insb(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
*(u8 *)addr = inb(port);
addr++;
}
}
static inline void __outsw(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
outw(*(u16 *)addr, port);
addr += 2;
}
}
static inline void __insw(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
*(u16 *)addr = inw(port);
addr += 2;
}
}
static inline void __outsl(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
outl(*(u32 *)addr, port);
addr += 4;
}
}
static inline void __insl(unsigned long port, void *addr, unsigned int count)
{
while (count--) {
*(u32 *)addr = inl(port);
addr += 4;
}
}
#define outsb(port, addr, count) __outsb(port, addr, count)
#define insb(port, addr, count) __insb(port, addr, count)
#define outsw(port, addr, count) __outsw(port, addr, count)
#define insw(port, addr, count) __insw(port, addr, count)
#define outsl(port, addr, count) __outsl(port, addr, count)
#define insl(port, addr, count) __insl(port, addr, count)
/*
* The caches on some architectures aren't dma-coherent and have need to
* handle this in software. There are three types of operations that
* can be applied to dma buffers.
*
* - dma_cache_wback_inv(start, size) makes caches and coherent by
* writing the content of the caches back to memory, if necessary.
* The function also invalidates the affected part of the caches as
* necessary before DMA transfers from outside to memory.
* - dma_cache_wback(start, size) makes caches and coherent by
* writing the content of the caches back to memory, if necessary.
* The function also invalidates the affected part of the caches as
* necessary before DMA transfers from outside to memory.
* - dma_cache_inv(start, size) invalidates the affected parts of the
* caches. Dirty lines of the caches may be written back or simply
* be discarded. This operation is necessary before dma operations
* to the memory.
*/
#ifdef CONFIG_DMA_NONCOHERENT
extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
#define dma_cache_wback_inv(start, size) _dma_cache_wback_inv(start,size)
#define dma_cache_wback(start, size) _dma_cache_wback(start,size)
#define dma_cache_inv(start, size) _dma_cache_inv(start,size)
#else /* Sane hardware */
#define dma_cache_wback_inv(start,size) \
do { (void) (start); (void) (size); } while (0)
#define dma_cache_wback(start,size) \
do { (void) (start); (void) (size); } while (0)
#define dma_cache_inv(start,size) \
do { (void) (start); (void) (size); } while (0)
#endif /* CONFIG_DMA_NONCOHERENT */
/*
* Read a 32-bit register that requires a 64-bit read cycle on the bus.
* Avoid interrupt mucking, just adjust the address for 4-byte access.
* Assume the addresses are 8-byte aligned.
*/
#ifdef __MIPSEB__
#define __CSR_32_ADJUST 4
#else
#define __CSR_32_ADJUST 0
#endif
#define csr_out32(v,a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
#define csr_in32(a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
#endif /* _ASM_IO_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 96, 99, 2001 Ralf Baechle
*/
#ifndef _ASM_IOCTL_H
#define _ASM_IOCTL_H
/*
* The original linux ioctl numbering scheme was just a general
* "anything goes" setup, where more or less random numbers were
* assigned. Sorry, I was clueless when I started out on this.
*
* On the alpha, we'll try to clean it up a bit, using a more sane
* ioctl numbering, and also trying to be compatible with OSF/1 in
* the process. I'd like to clean it up for the i386 as well, but
* it's so painful recognizing both the new and the old numbers..
*
* The same applies for for the MIPS ABI; in fact even the macros
* from Linux/Alpha fit almost perfectly.
*/
#define _IOC_NRBITS 8
#define _IOC_TYPEBITS 8
#define _IOC_SIZEBITS 13
#define _IOC_DIRBITS 3
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
#define _IOC_NRSHIFT 0
#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
/*
* We to additionally limit parameters to a maximum 255 bytes.
*/
#define _IOC_SLMASK 0xff
/*
* Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
* And this turns out useful to catch old ioctl numbers in header
* files for us.
*/
#define _IOC_NONE 1U
#define _IOC_READ 2U
#define _IOC_WRITE 4U
/*
* The following are included for compatibility
*/
#define _IOC_VOID 0x20000000
#define _IOC_OUT 0x40000000
#define _IOC_IN 0x80000000
#define _IOC_INOUT (IOC_IN|IOC_OUT)
#define _IOC(dir,type,nr,size) \
(((dir) << _IOC_DIRSHIFT) | \
((type) << _IOC_TYPESHIFT) | \
((nr) << _IOC_NRSHIFT) | \
((size) << _IOC_SIZESHIFT))
/* provoke compile error for invalid uses of size argument */
extern unsigned int __invalid_size_argument_for_IOC;
#define _IOC_TYPECHECK(t) \
((sizeof(t) == sizeof(t[1]) && \
sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
sizeof(t) : __invalid_size_argument_for_IOC)
/* used to create numbers */
#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
/* used to decode them.. */
#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
/* ...and for the drivers/sound files... */
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
#endif /* _ASM_IOCTL_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995, 1996, 2001 Ralf Baechle
* Copyright (C) 2001 MIPS Technologies, Inc.
*/
#ifndef __ASM_IOCTLS_H
#define __ASM_IOCTLS_H
#include <asm/ioctl.h>
#define TCGETA 0x5401
#define TCSETA 0x5402 /* Clashes with SNDCTL_TMR_START sound ioctl */
#define TCSETAW 0x5403
#define TCSETAF 0x5404
#define TCSBRK 0x5405
#define TCXONC 0x5406
#define TCFLSH 0x5407
#define TCGETS 0x540d
#define TCSETS 0x540e
#define TCSETSW 0x540f
#define TCSETSF 0x5410
#define TIOCEXCL 0x740d /* set exclusive use of tty */
#define TIOCNXCL 0x740e /* reset exclusive use of tty */
#define TIOCOUTQ 0x7472 /* output queue size */
#define TIOCSTI 0x5472 /* simulate terminal input */
#define TIOCMGET 0x741d /* get all modem bits */
#define TIOCMBIS 0x741b /* bis modem bits */
#define TIOCMBIC 0x741c /* bic modem bits */
#define TIOCMSET 0x741a /* set all modem bits */
#define TIOCPKT 0x5470 /* pty: set/clear packet mode */
#define TIOCPKT_DATA 0x00 /* data packet */
#define TIOCPKT_FLUSHREAD 0x01 /* flush packet */
#define TIOCPKT_FLUSHWRITE 0x02 /* flush packet */
#define TIOCPKT_STOP 0x04 /* stop output */
#define TIOCPKT_START 0x08 /* start output */
#define TIOCPKT_NOSTOP 0x10 /* no more ^S, ^Q */
#define TIOCPKT_DOSTOP 0x20 /* now do ^S ^Q */
/* #define TIOCPKT_IOCTL 0x40 state change of pty driver */
#define TIOCSWINSZ _IOW('t', 103, struct winsize) /* set window size */
#define TIOCGWINSZ _IOR('t', 104, struct winsize) /* get window size */
#define TIOCNOTTY 0x5471 /* void tty association */
#define TIOCSETD 0x7401
#define TIOCGETD 0x7400
#define FIOCLEX 0x6601
#define FIONCLEX 0x6602
#define FIOASYNC 0x667d
#define FIONBIO 0x667e
#define FIOQSIZE 0x667f
#define TIOCGLTC 0x7474 /* get special local chars */
#define TIOCSLTC 0x7475 /* set special local chars */
#define TIOCSPGRP _IOW('t', 118, int) /* set pgrp of tty */
#define TIOCGPGRP _IOR('t', 119, int) /* get pgrp of tty */
#define TIOCCONS _IOW('t', 120, int) /* become virtual console */
#define FIONREAD 0x467f
#define TIOCINQ FIONREAD
#define TIOCGETP 0x7408
#define TIOCSETP 0x7409
#define TIOCSETN 0x740a /* TIOCSETP wo flush */
/* #define TIOCSETA _IOW('t', 20, struct termios) set termios struct */
/* #define TIOCSETAW _IOW('t', 21, struct termios) drain output, set */
/* #define TIOCSETAF _IOW('t', 22, struct termios) drn out, fls in, set */
/* #define TIOCGETD _IOR('t', 26, int) get line discipline */
/* #define TIOCSETD _IOW('t', 27, int) set line discipline */
/* 127-124 compat */
#define TIOCSBRK 0x5427 /* BSD compatibility */
#define TIOCCBRK 0x5428 /* BSD compatibility */
#define TIOCGSID 0x7416 /* Return the session ID of FD */
#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
/* I hope the range from 0x5480 on is free ... */
#define TIOCSCTTY 0x5480 /* become controlling tty */
#define TIOCGSOFTCAR 0x5481
#define TIOCSSOFTCAR 0x5482
#define TIOCLINUX 0x5483
#define TIOCGSERIAL 0x5484
#define TIOCSSERIAL 0x5485
#define TCSBRKP 0x5486 /* Needed for POSIX tcsendbreak() */
#define TIOCSERCONFIG 0x5488
#define TIOCSERGWILD 0x5489
#define TIOCSERSWILD 0x548a
#define TIOCGLCKTRMIOS 0x548b
#define TIOCSLCKTRMIOS 0x548c
#define TIOCSERGSTRUCT 0x548d /* For debugging only */
#define TIOCSERGETLSR 0x548e /* Get line status register */
#define TIOCSERGETMULTI 0x548f /* Get multiport config */
#define TIOCSERSETMULTI 0x5490 /* Set multiport config */
#define TIOCMIWAIT 0x5491 /* wait for a change on serial input line(s) */
#define TIOCGICOUNT 0x5492 /* read serial port inline interrupt counts */
#define TIOCGHAYESESP 0x5493 /* Get Hayes ESP configuration */
#define TIOCSHAYESESP 0x5494 /* Set Hayes ESP configuration */
#endif /* __ASM_IOCTLS_H */

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/*
* Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory
* Engine)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Harald Koerfgen
*/
#ifndef __ASM_CRIME_H__
#define __ASM_CRIME_H__
/*
* Address map
*/
#define CRIME_BASE 0x14000000 /* physical */
#undef BIT
#define BIT(x) (1UL << (x))
struct sgi_crime {
volatile unsigned long id;
#define CRIME_ID_MASK 0xff
#define CRIME_ID_IDBITS 0xf0
#define CRIME_ID_IDVALUE 0xa0
#define CRIME_ID_REV 0x0f
#define CRIME_REV_PETTY 0x00
#define CRIME_REV_11 0x11
#define CRIME_REV_13 0x13
#define CRIME_REV_14 0x14
volatile unsigned long control;
#define CRIME_CONTROL_MASK 0x3fff
#define CRIME_CONTROL_TRITON_SYSADC 0x2000
#define CRIME_CONTROL_CRIME_SYSADC 0x1000
#define CRIME_CONTROL_HARD_RESET 0x0800
#define CRIME_CONTROL_SOFT_RESET 0x0400
#define CRIME_CONTROL_DOG_ENA 0x0200
#define CRIME_CONTROL_ENDIANESS 0x0100
#define CRIME_CONTROL_ENDIAN_BIG 0x0100
#define CRIME_CONTROL_ENDIAN_LITTLE 0x0000
#define CRIME_CONTROL_CQUEUE_HWM 0x000f
#define CRIME_CONTROL_CQUEUE_SHFT 0
#define CRIME_CONTROL_WBUF_HWM 0x00f0
#define CRIME_CONTROL_WBUF_SHFT 8
volatile unsigned long istat;
volatile unsigned long imask;
volatile unsigned long soft_int;
volatile unsigned long hard_int;
#define MACE_VID_IN1_INT BIT(0)
#define MACE_VID_IN2_INT BIT(1)
#define MACE_VID_OUT_INT BIT(2)
#define MACE_ETHERNET_INT BIT(3)
#define MACE_SUPERIO_INT BIT(4)
#define MACE_MISC_INT BIT(5)
#define MACE_AUDIO_INT BIT(6)
#define MACE_PCI_BRIDGE_INT BIT(7)
#define MACEPCI_SCSI0_INT BIT(8)
#define MACEPCI_SCSI1_INT BIT(9)
#define MACEPCI_SLOT0_INT BIT(10)
#define MACEPCI_SLOT1_INT BIT(11)
#define MACEPCI_SLOT2_INT BIT(12)
#define MACEPCI_SHARED0_INT BIT(13)
#define MACEPCI_SHARED1_INT BIT(14)
#define MACEPCI_SHARED2_INT BIT(15)
#define CRIME_GBE0_INT BIT(16)
#define CRIME_GBE1_INT BIT(17)
#define CRIME_GBE2_INT BIT(18)
#define CRIME_GBE3_INT BIT(19)
#define CRIME_CPUERR_INT BIT(20)
#define CRIME_MEMERR_INT BIT(21)
#define CRIME_RE_EMPTY_E_INT BIT(22)
#define CRIME_RE_FULL_E_INT BIT(23)
#define CRIME_RE_IDLE_E_INT BIT(24)
#define CRIME_RE_EMPTY_L_INT BIT(25)
#define CRIME_RE_FULL_L_INT BIT(26)
#define CRIME_RE_IDLE_L_INT BIT(27)
#define CRIME_SOFT0_INT BIT(28)
#define CRIME_SOFT1_INT BIT(29)
#define CRIME_SOFT2_INT BIT(30)
#define CRIME_SYSCORERR_INT CRIME_SOFT2_INT
#define CRIME_VICE_INT BIT(31)
/* Masks for deciding who handles the interrupt */
#define CRIME_MACE_INT_MASK 0x8f
#define CRIME_MACEISA_INT_MASK 0x70
#define CRIME_MACEPCI_INT_MASK 0xff00
#define CRIME_CRIME_INT_MASK 0xffff0000
volatile unsigned long watchdog;
#define CRIME_DOG_POWER_ON_RESET 0x00010000
#define CRIME_DOG_WARM_RESET 0x00080000
#define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
#define CRIME_DOG_VALUE 0x00007fff
volatile unsigned long timer;
#define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */
#define CRIME_NS_PER_TICK 15 /* for delay_calibrate */
volatile unsigned long cpu_error_addr;
#define CRIME_CPU_ERROR_ADDR_MASK 0x3ffffffff
volatile unsigned long cpu_error_stat;
#define CRIME_CPU_ERROR_MASK 0x7 /* cpu error stat is 3 bits */
#define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4
#define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2
#define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1
unsigned long _pad0[54];
volatile unsigned long mc_ctrl;
volatile unsigned long bank_ctrl[8];
#define CRIME_MEM_BANK_CONTROL_MASK 0x11f /* 9 bits 7:5 reserved */
#define CRIME_MEM_BANK_CONTROL_ADDR 0x01f
#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100
#define CRIME_MAXBANKS 8
volatile unsigned long mem_ref_counter;
#define CRIME_MEM_REF_COUNTER_MASK 0x3ff /* 10bit */
volatile unsigned long mem_error_stat;
#define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */
#define CRIME_MEM_ERROR_MACE_ID 0x0000007f
#define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080
#define CRIME_MEM_ERROR_RE_ID 0x00007f00
#define CRIME_MEM_ERROR_RE_ACCESS 0x00008000
#define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000
#define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000
#define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000
#define CRIME_MEM_ERROR_RESERVED 0x00080000
#define CRIME_MEM_ERROR_SOFT_ERR 0x00100000
#define CRIME_MEM_ERROR_HARD_ERR 0x00200000
#define CRIME_MEM_ERROR_MULTIPLE 0x00400000
#define CRIME_MEM_ERROR_ECC 0x01800000
#define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000
#define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000
#define CRIME_MEM_ERROR_INV 0x0e000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
volatile unsigned long mem_error_addr;
#define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff
volatile unsigned long mem_ecc_syn;
#define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff
volatile unsigned long mem_ecc_chk;
#define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff
volatile unsigned long mem_ecc_repl;
#define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff
};
extern struct sgi_crime *crime;
#endif /* __ASM_CRIME_H__ */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Harald Koerfgen
*/
#ifndef __ASM_IP32_INTS_H
#define __ASM_IP32_INTS_H
/*
* This list reflects the assignment of interrupt numbers to
* interrupting events. Order is fairly irrelevant to handling
* priority. This differs from irix.
*/
/* CPU */
#define IP32_R4K_TIMER_IRQ 0
/* MACE */
#define MACE_VID_IN1_IRQ 1
#define MACE_VID_IN2_IRQ 2
#define MACE_VID_OUT_IRQ 3
#define MACE_ETHERNET_IRQ 4
/* SUPERIO, MISC, and AUDIO are MACEISA */
#define MACE_PCI_BRIDGE_IRQ 8
/* MACEPCI */
#define MACEPCI_SCSI0_IRQ 9
#define MACEPCI_SCSI1_IRQ 10
#define MACEPCI_SLOT0_IRQ 11
#define MACEPCI_SLOT1_IRQ 12
#define MACEPCI_SLOT2_IRQ 13
#define MACEPCI_SHARED0_IRQ 14
#define MACEPCI_SHARED1_IRQ 15
#define MACEPCI_SHARED2_IRQ 16
/* CRIME */
#define CRIME_GBE0_IRQ 17
#define CRIME_GBE1_IRQ 18
#define CRIME_GBE2_IRQ 19
#define CRIME_GBE3_IRQ 20
#define CRIME_CPUERR_IRQ 21
#define CRIME_MEMERR_IRQ 22
#define CRIME_RE_EMPTY_E_IRQ 23
#define CRIME_RE_FULL_E_IRQ 24
#define CRIME_RE_IDLE_E_IRQ 25
#define CRIME_RE_EMPTY_L_IRQ 26
#define CRIME_RE_FULL_L_IRQ 27
#define CRIME_RE_IDLE_L_IRQ 28
#define CRIME_SOFT0_IRQ 29
#define CRIME_SOFT1_IRQ 30
#define CRIME_SOFT2_IRQ 31
#define CRIME_SYSCORERR_IRQ CRIME_SOFT2_IRQ
#define CRIME_VICE_IRQ 32
/* MACEISA */
#define MACEISA_AUDIO_SW_IRQ 33
#define MACEISA_AUDIO_SC_IRQ 34
#define MACEISA_AUDIO1_DMAT_IRQ 35
#define MACEISA_AUDIO1_OF_IRQ 36
#define MACEISA_AUDIO2_DMAT_IRQ 37
#define MACEISA_AUDIO2_MERR_IRQ 38
#define MACEISA_AUDIO3_DMAT_IRQ 39
#define MACEISA_AUDIO3_MERR_IRQ 40
#define MACEISA_RTC_IRQ 41
#define MACEISA_KEYB_IRQ 42
/* MACEISA_KEYB_POLL is not an IRQ */
#define MACEISA_MOUSE_IRQ 44
/* MACEISA_MOUSE_POLL is not an IRQ */
#define MACEISA_TIMER0_IRQ 46
#define MACEISA_TIMER1_IRQ 47
#define MACEISA_TIMER2_IRQ 48
#define MACEISA_PARALLEL_IRQ 49
#define MACEISA_PAR_CTXA_IRQ 50
#define MACEISA_PAR_CTXB_IRQ 51
#define MACEISA_PAR_MERR_IRQ 52
#define MACEISA_SERIAL1_IRQ 53
#define MACEISA_SERIAL1_TDMAT_IRQ 54
#define MACEISA_SERIAL1_TDMAPR_IRQ 55
#define MACEISA_SERIAL1_TDMAME_IRQ 56
#define MACEISA_SERIAL1_RDMAT_IRQ 57
#define MACEISA_SERIAL1_RDMAOR_IRQ 58
#define MACEISA_SERIAL2_IRQ 59
#define MACEISA_SERIAL2_TDMAT_IRQ 60
#define MACEISA_SERIAL2_TDMAPR_IRQ 61
#define MACEISA_SERIAL2_TDMAME_IRQ 62
#define MACEISA_SERIAL2_RDMAT_IRQ 63
#define MACEISA_SERIAL2_RDMAOR_IRQ 64
#define IP32_IRQ_MAX MACEISA_SERIAL2_RDMAOR_IRQ
#endif /* __ASM_IP32_INTS_H */

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/*
* Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000 Harald Koerfgen
* Copyright (C) 2004 Ladislav Michl
*/
#ifndef __ASM_MACE_H__
#define __ASM_MACE_H__
/*
* Address map
*/
#define MACE_BASE 0x1f000000 /* physical */
#undef BIT
#define BIT(x) (1UL << (x))
/*
* PCI interface
*/
struct mace_pci {
volatile unsigned int error_addr;
volatile unsigned int error;
#define MACEPCI_ERROR_MASTER_ABORT BIT(31)
#define MACEPCI_ERROR_TARGET_ABORT BIT(30)
#define MACEPCI_ERROR_DATA_PARITY_ERR BIT(29)
#define MACEPCI_ERROR_RETRY_ERR BIT(28)
#define MACEPCI_ERROR_ILLEGAL_CMD BIT(27)
#define MACEPCI_ERROR_SYSTEM_ERR BIT(26)
#define MACEPCI_ERROR_INTERRUPT_TEST BIT(25)
#define MACEPCI_ERROR_PARITY_ERR BIT(24)
#define MACEPCI_ERROR_OVERRUN BIT(23)
#define MACEPCI_ERROR_RSVD BIT(22)
#define MACEPCI_ERROR_MEMORY_ADDR BIT(21)
#define MACEPCI_ERROR_CONFIG_ADDR BIT(20)
#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID BIT(19)
#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID BIT(18)
#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID BIT(17)
#define MACEPCI_ERROR_RETRY_ADDR_VALID BIT(16)
#define MACEPCI_ERROR_SIG_TABORT BIT(4)
#define MACEPCI_ERROR_DEVSEL_MASK 0xc0
#define MACEPCI_ERROR_DEVSEL_FAST 0
#define MACEPCI_ERROR_DEVSEL_MED 0x40
#define MACEPCI_ERROR_DEVSEL_SLOW 0x80
#define MACEPCI_ERROR_FBB BIT(1)
#define MACEPCI_ERROR_66MHZ BIT(0)
volatile unsigned int control;
#define MACEPCI_CONTROL_INT(x) BIT(x)
#define MACEPCI_CONTROL_INT_MASK 0xff
#define MACEPCI_CONTROL_SERR_ENA BIT(8)
#define MACEPCI_CONTROL_ARB_N6 BIT(9)
#define MACEPCI_CONTROL_PARITY_ERR BIT(10)
#define MACEPCI_CONTROL_MRMRA_ENA BIT(11)
#define MACEPCI_CONTROL_ARB_N3 BIT(12)
#define MACEPCI_CONTROL_ARB_N4 BIT(13)
#define MACEPCI_CONTROL_ARB_N5 BIT(14)
#define MACEPCI_CONTROL_PARK_LIU BIT(15)
#define MACEPCI_CONTROL_INV_INT(x) BIT(16+x)
#define MACEPCI_CONTROL_INV_INT_MASK 0x00ff0000
#define MACEPCI_CONTROL_OVERRUN_INT BIT(24)
#define MACEPCI_CONTROL_PARITY_INT BIT(25)
#define MACEPCI_CONTROL_SERR_INT BIT(26)
#define MACEPCI_CONTROL_IT_INT BIT(27)
#define MACEPCI_CONTROL_RE_INT BIT(28)
#define MACEPCI_CONTROL_DPED_INT BIT(29)
#define MACEPCI_CONTROL_TAR_INT BIT(30)
#define MACEPCI_CONTROL_MAR_INT BIT(31)
volatile unsigned int rev;
unsigned int _pad[0xcf8/4 - 4];
volatile unsigned int config_addr;
union {
volatile unsigned char b[4];
volatile unsigned short w[2];
volatile unsigned int l;
} config_data;
};
#define MACEPCI_LOW_MEMORY 0x1a000000
#define MACEPCI_LOW_IO 0x18000000
#define MACEPCI_SWAPPED_VIEW 0
#define MACEPCI_NATIVE_VIEW 0x40000000
#define MACEPCI_IO 0x80000000
#define MACEPCI_HI_MEMORY 0x280000000
#define MACEPCI_HI_IO 0x100000000
/*
* Video interface
*/
struct mace_video {
unsigned long xxx; /* later... */
};
/*
* Ethernet interface
*/
struct mace_ethernet {
volatile unsigned long mac_ctrl;
volatile unsigned long int_stat;
volatile unsigned long dma_ctrl;
volatile unsigned long timer;
volatile unsigned long tx_int_al;
volatile unsigned long rx_int_al;
volatile unsigned long tx_info;
volatile unsigned long tx_info_al;
volatile unsigned long rx_buff;
volatile unsigned long rx_buff_al1;
volatile unsigned long rx_buff_al2;
volatile unsigned long diag;
volatile unsigned long phy_data;
volatile unsigned long phy_regs;
volatile unsigned long phy_trans_go;
volatile unsigned long backoff_seed;
/*===================================*/
volatile unsigned long imq_reserved[4];
volatile unsigned long mac_addr;
volatile unsigned long mac_addr2;
volatile unsigned long mcast_filter;
volatile unsigned long tx_ring_base;
/* Following are read-only registers for debugging */
volatile unsigned long tx_pkt1_hdr;
volatile unsigned long tx_pkt1_ptr[3];
volatile unsigned long tx_pkt2_hdr;
volatile unsigned long tx_pkt2_ptr[3];
/*===================================*/
volatile unsigned long rx_fifo;
};
/*
* Peripherals
*/
/* Audio registers */
struct mace_audio {
volatile unsigned long control;
volatile unsigned long codec_control; /* codec status control */
volatile unsigned long codec_mask; /* codec status input mask */
volatile unsigned long codec_read; /* codec status read data */
struct {
volatile unsigned long control; /* channel control */
volatile unsigned long read_ptr; /* channel read pointer */
volatile unsigned long write_ptr; /* channel write pointer */
volatile unsigned long depth; /* channel depth */
} chan[3];
};
/* ISA Control and DMA registers */
struct mace_isactrl {
volatile unsigned long ringbase;
#define MACEISA_RINGBUFFERS_SIZE (8 * 4096)
volatile unsigned long misc;
#define MACEISA_FLASH_WE BIT(0) /* 1=> Enable FLASH writes */
#define MACEISA_PWD_CLEAR BIT(1) /* 1=> PWD CLEAR jumper detected */
#define MACEISA_NIC_DEASSERT BIT(2)
#define MACEISA_NIC_DATA BIT(3)
#define MACEISA_LED_RED BIT(4) /* 0=> Illuminate red LED */
#define MACEISA_LED_GREEN BIT(5) /* 0=> Illuminate green LED */
#define MACEISA_DP_RAM_ENABLE BIT(6)
volatile unsigned long istat;
volatile unsigned long imask;
#define MACEISA_AUDIO_SW_INT BIT(0)
#define MACEISA_AUDIO_SC_INT BIT(1)
#define MACEISA_AUDIO1_DMAT_INT BIT(2)
#define MACEISA_AUDIO1_OF_INT BIT(3)
#define MACEISA_AUDIO2_DMAT_INT BIT(4)
#define MACEISA_AUDIO2_MERR_INT BIT(5)
#define MACEISA_AUDIO3_DMAT_INT BIT(6)
#define MACEISA_AUDIO3_MERR_INT BIT(7)
#define MACEISA_RTC_INT BIT(8)
#define MACEISA_KEYB_INT BIT(9)
#define MACEISA_KEYB_POLL_INT BIT(10)
#define MACEISA_MOUSE_INT BIT(11)
#define MACEISA_MOUSE_POLL_INT BIT(12)
#define MACEISA_TIMER0_INT BIT(13)
#define MACEISA_TIMER1_INT BIT(14)
#define MACEISA_TIMER2_INT BIT(15)
#define MACEISA_PARALLEL_INT BIT(16)
#define MACEISA_PAR_CTXA_INT BIT(17)
#define MACEISA_PAR_CTXB_INT BIT(18)
#define MACEISA_PAR_MERR_INT BIT(19)
#define MACEISA_SERIAL1_INT BIT(20)
#define MACEISA_SERIAL1_TDMAT_INT BIT(21)
#define MACEISA_SERIAL1_TDMAPR_INT BIT(22)
#define MACEISA_SERIAL1_TDMAME_INT BIT(23)
#define MACEISA_SERIAL1_RDMAT_INT BIT(24)
#define MACEISA_SERIAL1_RDMAOR_INT BIT(25)
#define MACEISA_SERIAL2_INT BIT(26)
#define MACEISA_SERIAL2_TDMAT_INT BIT(27)
#define MACEISA_SERIAL2_TDMAPR_INT BIT(28)
#define MACEISA_SERIAL2_TDMAME_INT BIT(29)
#define MACEISA_SERIAL2_RDMAT_INT BIT(30)
#define MACEISA_SERIAL2_RDMAOR_INT BIT(31)
volatile unsigned long _pad[0x2000/8 - 4];
volatile unsigned long dp_ram[0x400];
};
/* Keyboard & Mouse registers
* -> drivers/input/serio/maceps2.c */
struct mace_ps2port {
volatile unsigned long tx;
volatile unsigned long rx;
volatile unsigned long control;
volatile unsigned long status;
};
struct mace_ps2 {
struct mace_ps2port keyb;
struct mace_ps2port mouse;
};
/* I2C registers
* -> drivers/i2c/algos/i2c-algo-sgi.c */
struct mace_i2c {
volatile unsigned long config;
#define MACEI2C_RESET BIT(0)
#define MACEI2C_FAST BIT(1)
#define MACEI2C_DATA_OVERRIDE BIT(2)
#define MACEI2C_CLOCK_OVERRIDE BIT(3)
#define MACEI2C_DATA_STATUS BIT(4)
#define MACEI2C_CLOCK_STATUS BIT(5)
volatile unsigned long control;
volatile unsigned long data;
};
/* Timer registers */
typedef union {
volatile unsigned long ust_msc;
struct reg {
volatile unsigned int ust;
volatile unsigned int msc;
} reg;
} timer_reg;
struct mace_timers {
volatile unsigned long ust;
#define MACE_UST_PERIOD_NS 960
volatile unsigned long compare1;
volatile unsigned long compare2;
volatile unsigned long compare3;
timer_reg audio_in;
timer_reg audio_out1;
timer_reg audio_out2;
timer_reg video_in1;
timer_reg video_in2;
timer_reg video_out;
};
struct mace_perif {
struct mace_audio audio;
char _pad0[0x10000 - sizeof(struct mace_audio)];
struct mace_isactrl ctrl;
char _pad1[0x10000 - sizeof(struct mace_isactrl)];
struct mace_ps2 ps2;
char _pad2[0x10000 - sizeof(struct mace_ps2)];
struct mace_i2c i2c;
char _pad3[0x10000 - sizeof(struct mace_i2c)];
struct mace_timers timers;
char _pad4[0x10000 - sizeof(struct mace_timers)];
};
/*
* ISA peripherals
*/
/* Parallel port */
struct mace_parallel { /* later... */
};
struct mace_ecp1284 { /* later... */
};
/* Serial port */
struct mace_serial {
volatile unsigned long xxx; /* later... */
};
struct mace_isa {
struct mace_parallel parallel;
char _pad1[0x8000 - sizeof(struct mace_parallel)];
struct mace_ecp1284 ecp1284;
char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
struct mace_serial serial1;
char _pad3[0x8000 - sizeof(struct mace_serial)];
struct mace_serial serial2;
char _pad4[0x8000 - sizeof(struct mace_serial)];
volatile unsigned char rtc[0x10000];
};
struct sgi_mace {
char _reserved[0x80000];
struct mace_pci pci;
char _pad0[0x80000 - sizeof(struct mace_pci)];
struct mace_video video_in1;
char _pad1[0x80000 - sizeof(struct mace_video)];
struct mace_video video_in2;
char _pad2[0x80000 - sizeof(struct mace_video)];
struct mace_video video_out;
char _pad3[0x80000 - sizeof(struct mace_video)];
struct mace_ethernet eth;
char _pad4[0x80000 - sizeof(struct mace_ethernet)];
struct mace_perif perif;
char _pad5[0x80000 - sizeof(struct mace_perif)];
struct mace_isa isa;
char _pad6[0x80000 - sizeof(struct mace_isa)];
};
extern struct sgi_mace *mace;
#endif /* __ASM_MACE_H__ */

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/*
* machine.h -- Machine/group probing for ip32
*
* Copyright (C) 2001 Keith M Wesolowski
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef _ASM_IP32_MACHINE_H
#define _ASM_IP32_MACHINE_H
#include <linux/config.h>
#ifdef CONFIG_SGI_IP32
#define SGI_MACH_O2 0x3201
#endif /* CONFIG_SGI_IP32 */
#endif /* _ASM_SGI_MACHINE_H */

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#ifndef _ASM_IPC_H
#define _ASM_IPC_H
/*
* These are used to wrap system calls on MIPS.
*
* See arch/mips/kernel/sysmips.c for ugly details..
* FIXME: split up into ordinary syscalls ...
*/
struct ipc_kludge {
struct msgbuf *msgp;
long msgtyp;
};
#define SEMOP 1
#define SEMGET 2
#define SEMCTL 3
#define SEMTIMEDOP 4
#define MSGSND 11
#define MSGRCV 12
#define MSGGET 13
#define MSGCTL 14
#define SHMAT 21
#define SHMDT 22
#define SHMGET 23
#define SHMCTL 24
/* Used by the DIPC package, try and avoid reusing it */
#define DIPC 25
#define IPCCALL(version,op) ((version)<<16 | (op))
#endif /* _ASM_IPC_H */

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#ifndef _ASM_IPCBUF_H
#define _ASM_IPCBUF_H
/*
* The ipc64_perm structure for alpha architecture.
* Note extra padding because this structure is passed back and forth
* between kernel and user space.
*
* Pad space is left for:
* - 32-bit seq
* - 2 miscellaneous 64-bit values
*/
struct ipc64_perm
{
__kernel_key_t key;
__kernel_uid_t uid;
__kernel_gid_t gid;
__kernel_uid_t cuid;
__kernel_gid_t cgid;
__kernel_mode_t mode;
unsigned short seq;
unsigned short __pad1;
unsigned long __unused1;
unsigned long __unused2;
};
#endif /* _ASM_IPCBUF_H */

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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
* Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
*/
#ifndef _ASM_IRQ_H
#define _ASM_IRQ_H
#include <linux/config.h>
#include <linux/linkage.h>
#include <irq.h>
#ifdef CONFIG_I8259
static inline int irq_canonicalize(int irq)
{
return ((irq == 2) ? 9 : irq);
}
#else
#define irq_canonicalize(irq) (irq) /* Sane hardware, sane code ... */
#endif
struct pt_regs;
#ifdef CONFIG_PREEMPT
extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs);
#else
/*
* do_IRQ handles all normal device IRQ's (the special
* SMP cross-CPU interrupts have their own specific
* handlers).
*
* Ideally there should be away to get this into kernel/irq/handle.c to
* avoid the overhead of a call for just a tiny function ...
*/
#define do_IRQ(irq, regs) \
do { \
irq_enter(); \
__do_IRQ((irq), (regs)); \
irq_exit(); \
} while (0)
#endif
extern void arch_init_irq(void);
struct irqaction;
int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
#endif /* _ASM_IRQ_H */

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/*
* include/asm-mips/irq_cpu.h
*
* MIPS CPU interrupt definitions.
*
* Copyright (C) 2002 Maciej W. Rozycki
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_IRQ_CPU_H
#define _ASM_IRQ_CPU_H
extern void mips_cpu_irq_init(int irq_base);
extern void rm7k_cpu_irq_init(int irq_base);
#endif /* _ASM_IRQ_CPU_H */

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/*
* Various ISA level dependent constants.
* Most of the following constants reflect the different layout
* of Coprocessor 0 registers.
*
* Copyright (c) 1998 Harald Koerfgen
*/
#include <linux/config.h>
#ifndef __ASM_ISADEP_H
#define __ASM_ISADEP_H
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
/*
* R2000 or R3000
*/
/*
* kernel or user mode? (CP0_STATUS)
*/
#define KU_MASK 0x08
#define KU_USER 0x08
#define KU_KERN 0x00
#else
/*
* kernel or user mode?
*/
#define KU_MASK 0x18
#define KU_USER 0x10
#define KU_KERN 0x00
#endif
#endif /* __ASM_ISADEP_H */

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/*
*
* BRIEF MODULE DESCRIPTION
* IT8172 system controller defines.
*
* Copyright 2000 MontaVista Software Inc.
* Author: MontaVista Software, Inc.
* ppopov@mvista.com or source@mvista.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __IT8172__H__
#define __IT8172__H__
#include <asm/addrspace.h>
#define IT8172_BASE 0x18000000
#define IT8172_PCI_IO_BASE 0x14000000
#define IT8172_PCI_MEM_BASE 0x10000000
// System registers offsets from IT8172_BASE
#define IT_CMFPCR 0x0
#define IT_DSRR 0x2
#define IT_PCDCR 0x4
#define IT_SPLLCR 0x6
#define IT_CIDR 0x10
#define IT_CRNR 0x12
#define IT_CPUTR 0x14
#define IT_CTCR 0x16
#define IT_SDPR 0xF0
// Power management register offset from IT8172_PCI_IO_BASE
// Power Management Device Standby Register
#define IT_PM_DSR 0x15800
#define IT_PM_DSR_TMR0SB 0x0001
#define IT_PM_DSR_TMR1SB 0x0002
#define IT_PM_DSR_CIR0SB 0x0004
#define IT_PM_DSR_CIR1SB 0x0008
#define IT_PM_DSR_SCR0SB 0x0010
#define IT_PM_DSR_SCR1SB 0x0020
#define IT_PM_DSR_PPSB 0x0040
#define IT_PM_DSR_I2CSB 0x0080
#define IT_PM_DSR_UARTSB 0x0100
#define IT_PM_DSR_IDESB 0x0200
#define IT_PM_DSR_ACSB 0x0400
#define IT_PM_DSR_M68KSB 0x0800
// Power Management PCI Device Software Reset Register
#define IT_PM_PCISR 0x15802
#define IT_PM_PCISR_IDESR 0x0001
#define IT_PM_PCISR_CDMASR 0x0002
#define IT_PM_PCISR_USBSR 0x0004
#define IT_PM_PCISR_DMASR 0x0008
#define IT_PM_PCISR_ACSR 0x0010
#define IT_PM_PCISR_MEMSR 0x0020
#define IT_PM_PCISR_68KSR 0x0040
// PCI Configuration address and data register offsets
// from IT8172_BASE
#define IT_CONFADDR 0x4000
#define IT_BUSNUM_SHF 16
#define IT_DEVNUM_SHF 11
#define IT_FUNCNUM_SHF 8
#define IT_REGNUM_SHF 2
#define IT_CONFDATA 0x4004
// PCI configuration header common register offsets
#define IT_VID 0x00
#define IT_DID 0x02
#define IT_PCICMD 0x04
#define IT_PCISTS 0x06
#define IT_RID 0x08
#define IT_CLASSC 0x09
#define IT_HEADT 0x0E
#define IT_SERIRQC 0x49
// PCI to Internal/LPC Bus Bridge configuration header register offset
#define IT_P2I_BCR 0x4C
#define IT_P2I_D0IOSC 0x50
#define IT_P2I_D1IOSC 0x54
#define IT_P2I_D2IOSC 0x58
#define IT_P2I_D3IOSC 0x5C
#define IT_P2I_D4IOSC 0x60
#define IT_P2I_D5IOSC 0x64
#define IT_P2I_D6IOSC 0x68
#define IT_P2I_D7IOSC 0x6C
#define IT_P2I_D8IOSC 0x70
#define IT_P2I_D9IOSC 0x74
#define IT_P2I_D10IOSC 0x78
#define IT_P2I_D11IOSC 0x7C
// Memory controller register offsets from IT8172_BASE
#define IT_MC_SDRMR 0x1000
#define IT_MC_SDRTR 0x1004
#define IT_MC_MCR 0x1008
#define IT_MC_SDTYPE 0x100C
#define IT_MC_WPBA 0x1010
#define IT_MC_WPTA 0x1014
#define IT_MC_HATR 0x1018
#define IT_MC_PCICR 0x101C
// Flash/ROM control register offsets from IT8172_BASE
#define IT_FC_BRCR 0x2000
#define IT_FC_FCR 0x2004
#define IT_FC_DCR 0x2008
// M68K interface bridge configuration header register offset
#define IT_M68K_MBCSR 0x54
#define IT_M68K_TMR 0x58
#define IT_M68K_BCR 0x5C
#define IT_M68K_BSR 0x5D
#define IT_M68K_DTR 0x5F
// Register offset from IT8172_PCI_IO_BASE
// These registers are accessible through 8172 PCI IO window.
// INTC
#define IT_INTC_BASE 0x10000
#define IT_INTC_LBDNIRR 0x10000
#define IT_INTC_LBDNIMR 0x10002
#define IT_INTC_LBDNITR 0x10004
#define IT_INTC_LBDNIAR 0x10006
#define IT_INTC_LPCNIRR 0x10010
#define IT_INTC_LPCNIMR 0x10012
#define IT_INTC_LPCNITR 0x10014
#define IT_INTC_LPCNIAR 0x10016
#define IT_INTC_PDNIRR 0x10020
#define IT_INTC_PDNIMR 0x10022
#define IT_INTC_PDNITR 0x10024
#define IT_INTC_PDNIAR 0x10026
#define IT_INTC_UMNIRR 0x10030
#define IT_INTC_UMNITR 0x10034
#define IT_INTC_UMNIAR 0x10036
#define IT_INTC_TYPER 0x107FE
// IT8172 PCI device number
#define IT_C2P_DEVICE 0
#define IT_AUDIO_DEVICE 1
#define IT_DMAC_DEVICE 1
#define IT_CDMAC_DEVICE 1
#define IT_USB_DEVICE 1
#define IT_P2I_DEVICE 1
#define IT_IDE_DEVICE 1
#define IT_M68K_DEVICE 1
// IT8172 PCI function number
#define IT_C2P_FUNCION 0
#define IT_AUDIO_FUNCTION 0
#define IT_DMAC_FUNCTION 1
#define IT_CDMAC_FUNCTION 2
#define IT_USB_FUNCTION 3
#define IT_P2I_FUNCTION 4
#define IT_IDE_FUNCTION 5
#define IT_M68K_FUNCTION 6
// IT8172 GPIO
#define IT_GPADR 0x13800
#define IT_GPBDR 0x13808
#define IT_GPCDR 0x13810
#define IT_GPACR 0x13802
#define IT_GPBCR 0x1380A
#define IT_GPCCR 0x13812
#define IT_GPAICR 0x13804
#define IT_GPBICR 0x1380C
#define IT_GPCICR 0x13814
#define IT_GPAISR 0x13806
#define IT_GPBISR 0x1380E
#define IT_GPCISR 0x13816
#define IT_GCR 0x13818
// IT8172 RTC
#define IT_RTC_BASE 0x14800
#define IT_RTC_CENTURY 0x14808
#define IT_RTC_RIR0 0x00
#define IT_RTC_RTR0 0x01
#define IT_RTC_RIR1 0x02
#define IT_RTC_RTR1 0x03
#define IT_RTC_RIR2 0x04
#define IT_RTC_RTR2 0x05
#define IT_RTC_RCTR 0x08
#define IT_RTC_RA 0x0A
#define IT_RTC_RB 0x0B
#define IT_RTC_RC 0x0C
#define IT_RTC_RD 0x0D
#define RTC_SEC_INDEX 0x00
#define RTC_MIN_INDEX 0x02
#define RTC_HOUR_INDEX 0x04
#define RTC_DAY_INDEX 0x06
#define RTC_DATE_INDEX 0x07
#define RTC_MONTH_INDEX 0x08
#define RTC_YEAR_INDEX 0x09
// IT8172 internal device registers
#define IT_TIMER_BASE 0x10800
#define IT_CIR0_BASE 0x11000
#define IT_UART_BASE 0x11800
#define IT_SCR0_BASE 0x12000
#define IT_SCR1_BASE 0x12800
#define IT_PP_BASE 0x13000
#define IT_I2C_BASE 0x14000
#define IT_CIR1_BASE 0x15000
// IT8172 Smart Card Reader offsets from IT_SCR*_BASE
#define IT_SCR_SFR 0x08
#define IT_SCR_SCDR 0x09
// IT8172 IT_SCR_SFR bit definition & mask
#define IT_SCR_SFR_GATE_UART 0x40
#define IT_SCR_SFR_GATE_UART_BIT 6
#define IT_SCR_SFR_GATE_UART_OFF 0
#define IT_SCR_SFR_GATE_UART_ON 1
#define IT_SCR_SFR_FET_CHARGE 0x30
#define IT_SCR_SFR_FET_CHARGE_BIT 4
#define IT_SCR_SFR_FET_CHARGE_3_3_US 3
#define IT_SCR_SFR_FET_CHARGE_13_US 2
#define IT_SCR_SFR_FET_CHARGE_53_US 1
#define IT_SCR_SFR_FET_CHARGE_213_US 0
#define IT_SCR_SFR_CARD_FREQ 0x0C
#define IT_SCR_SFR_CARD_FREQ_BIT 2
#define IT_SCR_SFR_CARD_FREQ_STOP 3
#define IT_SCR_SFR_CARD_FREQ_3_5_MHZ 0
#define IT_SCR_SFR_CARD_FREQ_7_1_MHZ 2
#define IT_SCR_SFR_CARD_FREQ_96_DIV_MHZ 1
#define IT_SCR_SFR_FET_ACTIVE 0x02
#define IT_SCR_SFR_FET_ACTIVE_BIT 1
#define IT_SCR_SFR_FET_ACTIVE_INVERT 0
#define IT_SCR_SFR_FET_ACTIVE_NONINVERT 1
#define IT_SCR_SFR_ENABLE 0x01
#define IT_SCR_SFR_ENABLE_BIT 0
#define IT_SCR_SFR_ENABLE_OFF 0
#define IT_SCR_SFR_ENABLE_ON 1
// IT8172 IT_SCR_SCDR bit definition & mask
#define IT_SCR_SCDR_RESET_MODE 0x80
#define IT_SCR_SCDR_RESET_MODE_BIT 7
#define IT_SCR_SCDR_RESET_MODE_ASYNC 0
#define IT_SCR_SCDR_RESET_MODE_SYNC 1
#define IT_SCR_SCDR_DIVISOR 0x7F
#define IT_SCR_SCDR_DIVISOR_BIT 0
#define IT_SCR_SCDR_DIVISOR_STOP_VAL_1 0x00
#define IT_SCR_SCDR_DIVISOR_STOP_VAL_2 0x01
#define IT_SCR_SCDR_DIVISOR_STOP_VAL_3 0x7F
// IT8172 DMA
#define IT_DMAC_BASE 0x16000
#define IT_DMAC_BCAR0 0x00
#define IT_DMAC_BCAR1 0x04
#define IT_DMAC_BCAR2 0x08
#define IT_DMAC_BCAR3 0x0C
#define IT_DMAC_BCCR0 0x02
#define IT_DMAC_BCCR1 0x06
#define IT_DMAC_BCCR2 0x0a
#define IT_DMAC_BCCR3 0x0e
#define IT_DMAC_CR 0x10
#define IT_DMAC_SR 0x12
#define IT_DMAC_ESR 0x13
#define IT_DMAC_RQR 0x14
#define IT_DMAC_MR 0x16
#define IT_DMAC_EMR 0x17
#define IT_DMAC_MKR 0x18
#define IT_DMAC_PAR0 0x20
#define IT_DMAC_PAR1 0x22
#define IT_DMAC_PAR2 0x24
#define IT_DMAC_PAR3 0x26
// IT8172 IDE
#define IT_IDE_BASE 0x17800
#define IT_IDE_STATUS 0x1F7
// IT8172 Audio Controller
#define IT_AC_BASE 0x17000
#define IT_AC_PCMOV 0x00
#define IT_AC_FMOV 0x02
#define IT_AC_I2SV 0x04
#define IT_AC_DRSS 0x06
#define IT_AC_PCC 0x08
#define IT_AC_PCDL 0x0A
#define IT_AC_PCB1STA 0x0C
#define IT_AC_PCB2STA 0x10
#define IT_AC_CAPCC 0x14
#define IT_AC_CAPCDL 0x16
#define IT_AC_CAPB1STA 0x18
#define IT_AC_CAPB2STA 0x1C
#define IT_AC_CODECC 0x22
#define IT_AC_I2SMC 0x24
#define IT_AC_VS 0x26
#define IT_AC_SRCS 0x28
#define IT_AC_CIRCP 0x2A
#define IT_AC_CIRDP 0x2C
#define IT_AC_TM 0x4A
#define IT_AC_PFDP 0x4C
#define IT_AC_GC 0x54
#define IT_AC_IMC 0x56
#define IT_AC_ISC 0x5B
#define IT_AC_OPL3SR 0x68
#define IT_AC_OPL3DWDR 0x69
#define IT_AC_OPL3AB1W 0x6A
#define IT_AC_OPL3DW 0x6B
#define IT_AC_BPDC 0x70
// IT8172 Timer
#define IT_TIMER_BASE 0x10800
#define TIMER_TCVR0 0x00
#define TIMER_TRVR0 0x02
#define TIMER_TCR0 0x04
#define TIMER_TIRR 0x06
#define TIMER_TCVR1 0x08
#define TIMER_TRVR1 0x0A
#define TIMER_TCR1 0x0C
#define TIMER_TIDR 0x0E
#define IT_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs)) = data
#define IT_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_BASE+ofs))
#define IT_IO_WRITE(ofs, data) *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
#define IT_IO_READ(ofs, data) data = *(volatile u32 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
#define IT_IO_WRITE16(ofs, data) *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs)) = data
#define IT_IO_READ16(ofs, data) data = *(volatile u16 *)KSEG1ADDR((IT8172_PCI_IO_BASE+ofs))
#endif

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