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(2006-08-06) rescue-bootcd

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This commit is contained in:
Valeriano A.R.
2006-08-06 00:00:00 +02:00
parent 2f796b816a
commit decb062d20
21091 changed files with 7076462 additions and 0 deletions
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10
extra/linux-2.6.10/include/asm-ppc/8253pit.h Normal file
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/*
* 8253/8254 Programmable Interval Timer
*/
#ifndef _8253PIT_H
#define _8253PIT_H
#define PIT_TICK_RATE 1193182UL
#endif

564
extra/linux-2.6.10/include/asm-ppc/8xx_immap.h Normal file
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/*
* MPC8xx Internal Memory Map
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* The I/O on the MPC860 is comprised of blocks of special registers
* and the dual port ram for the Communication Processor Module.
* Within this space are functional units such as the SIU, memory
* controller, system timers, and other control functions. It is
* a combination that I found difficult to separate into logical
* functional files.....but anyone else is welcome to try. -- Dan
*/
#ifdef __KERNEL__
#ifndef __IMMAP_8XX__
#define __IMMAP_8XX__
/* System configuration registers.
*/
typedef struct sys_conf {
uint sc_siumcr;
uint sc_sypcr;
uint sc_swt;
char res1[2];
ushort sc_swsr;
uint sc_sipend;
uint sc_simask;
uint sc_siel;
uint sc_sivec;
uint sc_tesr;
char res2[0xc];
uint sc_sdcr;
char res3[0x4c];
} sysconf8xx_t;
/* PCMCIA configuration registers.
*/
typedef struct pcmcia_conf {
uint pcmc_pbr0;
uint pcmc_por0;
uint pcmc_pbr1;
uint pcmc_por1;
uint pcmc_pbr2;
uint pcmc_por2;
uint pcmc_pbr3;
uint pcmc_por3;
uint pcmc_pbr4;
uint pcmc_por4;
uint pcmc_pbr5;
uint pcmc_por5;
uint pcmc_pbr6;
uint pcmc_por6;
uint pcmc_pbr7;
uint pcmc_por7;
char res1[0x20];
uint pcmc_pgcra;
uint pcmc_pgcrb;
uint pcmc_pscr;
char res2[4];
uint pcmc_pipr;
char res3[4];
uint pcmc_per;
char res4[4];
} pcmconf8xx_t;
/* Memory controller registers.
*/
typedef struct mem_ctlr {
uint memc_br0;
uint memc_or0;
uint memc_br1;
uint memc_or1;
uint memc_br2;
uint memc_or2;
uint memc_br3;
uint memc_or3;
uint memc_br4;
uint memc_or4;
uint memc_br5;
uint memc_or5;
uint memc_br6;
uint memc_or6;
uint memc_br7;
uint memc_or7;
char res1[0x24];
uint memc_mar;
uint memc_mcr;
char res2[4];
uint memc_mamr;
uint memc_mbmr;
ushort memc_mstat;
ushort memc_mptpr;
uint memc_mdr;
char res3[0x80];
} memctl8xx_t;
/*-----------------------------------------------------------------------
* BR - Memory Controler: Base Register 16-9
*/
#define BR_BA_MSK 0xffff8000 /* Base Address Mask */
#define BR_AT_MSK 0x00007000 /* Address Type Mask */
#define BR_PS_MSK 0x00000c00 /* Port Size Mask */
#define BR_PS_32 0x00000000 /* 32 bit port size */
#define BR_PS_16 0x00000800 /* 16 bit port size */
#define BR_PS_8 0x00000400 /* 8 bit port size */
#define BR_PARE 0x00000200 /* Parity Enable */
#define BR_WP 0x00000100 /* Write Protect */
#define BR_MS_MSK 0x000000c0 /* Machine Select Mask */
#define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
#define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
#define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
#define BR_V 0x00000001 /* Bank Valid */
/*-----------------------------------------------------------------------
* OR - Memory Controler: Option Register 16-11
*/
#define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
#define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
#define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */
/* Address Multiplex */
#define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */
#define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
#define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
#define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
#define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
#define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
#define OR_BI 0x00000100 /* Burst inhibit */
#define OR_SCY_MSK 0x000000f0 /* Cycle Lenght in Clocks */
#define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
#define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
#define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
#define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
#define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
#define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
#define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
#define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
#define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
#define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
#define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
#define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
#define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
#define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
#define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
#define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
#define OR_SETA 0x00000008 /* External Transfer Acknowledge */
#define OR_TRLX 0x00000004 /* Timing Relaxed */
#define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
/* System Integration Timers.
*/
typedef struct sys_int_timers {
ushort sit_tbscr;
char res0[0x02];
uint sit_tbreff0;
uint sit_tbreff1;
char res1[0x14];
ushort sit_rtcsc;
char res2[0x02];
uint sit_rtc;
uint sit_rtsec;
uint sit_rtcal;
char res3[0x10];
ushort sit_piscr;
char res4[2];
uint sit_pitc;
uint sit_pitr;
char res5[0x34];
} sit8xx_t;
#define TBSCR_TBIRQ_MASK ((ushort)0xff00)
#define TBSCR_REFA ((ushort)0x0080)
#define TBSCR_REFB ((ushort)0x0040)
#define TBSCR_REFAE ((ushort)0x0008)
#define TBSCR_REFBE ((ushort)0x0004)
#define TBSCR_TBF ((ushort)0x0002)
#define TBSCR_TBE ((ushort)0x0001)
#define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
#define RTCSC_SEC ((ushort)0x0080)
#define RTCSC_ALR ((ushort)0x0040)
#define RTCSC_38K ((ushort)0x0010)
#define RTCSC_SIE ((ushort)0x0008)
#define RTCSC_ALE ((ushort)0x0004)
#define RTCSC_RTF ((ushort)0x0002)
#define RTCSC_RTE ((ushort)0x0001)
#define PISCR_PIRQ_MASK ((ushort)0xff00)
#define PISCR_PS ((ushort)0x0080)
#define PISCR_PIE ((ushort)0x0004)
#define PISCR_PTF ((ushort)0x0002)
#define PISCR_PTE ((ushort)0x0001)
/* Clocks and Reset.
*/
typedef struct clk_and_reset {
uint car_sccr;
uint car_plprcr;
uint car_rsr;
char res[0x74]; /* Reserved area */
} car8xx_t;
/* System Integration Timers keys.
*/
typedef struct sitk {
uint sitk_tbscrk;
uint sitk_tbreff0k;
uint sitk_tbreff1k;
uint sitk_tbk;
char res1[0x10];
uint sitk_rtcsck;
uint sitk_rtck;
uint sitk_rtseck;
uint sitk_rtcalk;
char res2[0x10];
uint sitk_piscrk;
uint sitk_pitck;
char res3[0x38];
} sitk8xx_t;
/* Clocks and reset keys.
*/
typedef struct cark {
uint cark_sccrk;
uint cark_plprcrk;
uint cark_rsrk;
char res[0x474];
} cark8xx_t;
/* The key to unlock registers maintained by keep-alive power.
*/
#define KAPWR_KEY ((unsigned int)0x55ccaa33)
/* Video interface. MPC823 Only.
*/
typedef struct vid823 {
ushort vid_vccr;
ushort res1;
u_char vid_vsr;
u_char res2;
u_char vid_vcmr;
u_char res3;
uint vid_vbcb;
uint res4;
uint vid_vfcr0;
uint vid_vfaa0;
uint vid_vfba0;
uint vid_vfcr1;
uint vid_vfaa1;
uint vid_vfba1;
u_char res5[0x18];
} vid823_t;
/* LCD interface. 823 Only.
*/
typedef struct lcd {
uint lcd_lccr;
uint lcd_lchcr;
uint lcd_lcvcr;
char res1[4];
uint lcd_lcfaa;
uint lcd_lcfba;
char lcd_lcsr;
char res2[0x7];
} lcd823_t;
/* I2C
*/
typedef struct i2c {
u_char i2c_i2mod;
char res1[3];
u_char i2c_i2add;
char res2[3];
u_char i2c_i2brg;
char res3[3];
u_char i2c_i2com;
char res4[3];
u_char i2c_i2cer;
char res5[3];
u_char i2c_i2cmr;
char res6[0x8b];
} i2c8xx_t;
/* DMA control/status registers.
*/
typedef struct sdma_csr {
char res1[4];
uint sdma_sdar;
u_char sdma_sdsr;
char res3[3];
u_char sdma_sdmr;
char res4[3];
u_char sdma_idsr1;
char res5[3];
u_char sdma_idmr1;
char res6[3];
u_char sdma_idsr2;
char res7[3];
u_char sdma_idmr2;
char res8[0x13];
} sdma8xx_t;
/* Communication Processor Module Interrupt Controller.
*/
typedef struct cpm_ic {
ushort cpic_civr;
char res[0xe];
uint cpic_cicr;
uint cpic_cipr;
uint cpic_cimr;
uint cpic_cisr;
} cpic8xx_t;
/* Input/Output Port control/status registers.
*/
typedef struct io_port {
ushort iop_padir;
ushort iop_papar;
ushort iop_paodr;
ushort iop_padat;
char res1[8];
ushort iop_pcdir;
ushort iop_pcpar;
ushort iop_pcso;
ushort iop_pcdat;
ushort iop_pcint;
char res2[6];
ushort iop_pddir;
ushort iop_pdpar;
char res3[2];
ushort iop_pddat;
uint utmode;
char res4[4];
} iop8xx_t;
/* Communication Processor Module Timers
*/
typedef struct cpm_timers {
ushort cpmt_tgcr;
char res1[0xe];
ushort cpmt_tmr1;
ushort cpmt_tmr2;
ushort cpmt_trr1;
ushort cpmt_trr2;
ushort cpmt_tcr1;
ushort cpmt_tcr2;
ushort cpmt_tcn1;
ushort cpmt_tcn2;
ushort cpmt_tmr3;
ushort cpmt_tmr4;
ushort cpmt_trr3;
ushort cpmt_trr4;
ushort cpmt_tcr3;
ushort cpmt_tcr4;
ushort cpmt_tcn3;
ushort cpmt_tcn4;
ushort cpmt_ter1;
ushort cpmt_ter2;
ushort cpmt_ter3;
ushort cpmt_ter4;
char res2[8];
} cpmtimer8xx_t;
/* Finally, the Communication Processor stuff.....
*/
typedef struct scc { /* Serial communication channels */
uint scc_gsmrl;
uint scc_gsmrh;
ushort scc_psmr;
char res1[2];
ushort scc_todr;
ushort scc_dsr;
ushort scc_scce;
char res2[2];
ushort scc_sccm;
char res3;
u_char scc_sccs;
char res4[8];
} scc_t;
typedef struct smc { /* Serial management channels */
char res1[2];
ushort smc_smcmr;
char res2[2];
u_char smc_smce;
char res3[3];
u_char smc_smcm;
char res4[5];
} smc_t;
/* MPC860T Fast Ethernet Controller. It isn't part of the CPM, but
* it fits within the address space.
*/
typedef struct fec {
uint fec_addr_low; /* lower 32 bits of station address */
ushort fec_addr_high; /* upper 16 bits of station address */
ushort res1; /* reserved */
uint fec_hash_table_high; /* upper 32-bits of hash table */
uint fec_hash_table_low; /* lower 32-bits of hash table */
uint fec_r_des_start; /* beginning of Rx descriptor ring */
uint fec_x_des_start; /* beginning of Tx descriptor ring */
uint fec_r_buff_size; /* Rx buffer size */
uint res2[9]; /* reserved */
uint fec_ecntrl; /* ethernet control register */
uint fec_ievent; /* interrupt event register */
uint fec_imask; /* interrupt mask register */
uint fec_ivec; /* interrupt level and vector status */
uint fec_r_des_active; /* Rx ring updated flag */
uint fec_x_des_active; /* Tx ring updated flag */
uint res3[10]; /* reserved */
uint fec_mii_data; /* MII data register */
uint fec_mii_speed; /* MII speed control register */
uint res4[17]; /* reserved */
uint fec_r_bound; /* end of RAM (read-only) */
uint fec_r_fstart; /* Rx FIFO start address */
uint res5[6]; /* reserved */
uint fec_x_fstart; /* Tx FIFO start address */
uint res6[17]; /* reserved */
uint fec_fun_code; /* fec SDMA function code */
uint res7[3]; /* reserved */
uint fec_r_cntrl; /* Rx control register */
uint fec_r_hash; /* Rx hash register */
uint res8[14]; /* reserved */
uint fec_x_cntrl; /* Tx control register */
uint res9[0x1e]; /* reserved */
} fec_t;
/* The FEC and LCD color map share the same address space....
* I guess we will never see an 823T :-).
*/
union fec_lcd {
fec_t fl_un_fec;
u_char fl_un_cmap[0x200];
};
typedef struct comm_proc {
/* General control and status registers.
*/
ushort cp_cpcr;
u_char res1[2];
ushort cp_rccr;
u_char res2;
u_char cp_rmds;
u_char res3[4];
ushort cp_cpmcr1;
ushort cp_cpmcr2;
ushort cp_cpmcr3;
ushort cp_cpmcr4;
u_char res4[2];
ushort cp_rter;
u_char res5[2];
ushort cp_rtmr;
u_char res6[0x14];
/* Baud rate generators.
*/
uint cp_brgc1;
uint cp_brgc2;
uint cp_brgc3;
uint cp_brgc4;
/* Serial Communication Channels.
*/
scc_t cp_scc[4];
/* Serial Management Channels.
*/
smc_t cp_smc[2];
/* Serial Peripheral Interface.
*/
ushort cp_spmode;
u_char res7[4];
u_char cp_spie;
u_char res8[3];
u_char cp_spim;
u_char res9[2];
u_char cp_spcom;
u_char res10[2];
/* Parallel Interface Port.
*/
u_char res11[2];
ushort cp_pipc;
u_char res12[2];
ushort cp_ptpr;
uint cp_pbdir;
uint cp_pbpar;
u_char res13[2];
ushort cp_pbodr;
uint cp_pbdat;
/* Port E - MPC87x/88x only.
*/
uint cp_pedir;
uint cp_pepar;
uint cp_peso;
uint cp_peodr;
uint cp_pedat;
/* Communications Processor Timing Register -
Contains RMII Timing for the FECs on MPC87x/88x only.
*/
uint cp_cptr;
/* Serial Interface and Time Slot Assignment.
*/
uint cp_simode;
u_char cp_sigmr;
u_char res15;
u_char cp_sistr;
u_char cp_sicmr;
u_char res16[4];
uint cp_sicr;
uint cp_sirp;
u_char res17[0xc];
/* 256 bytes of MPC823 video controller RAM array.
*/
u_char cp_vcram[0x100];
u_char cp_siram[0x200];
/* The fast ethernet controller is not really part of the CPM,
* but it resides in the address space.
* The LCD color map is also here.
*/
union fec_lcd fl_un;
#define cp_fec fl_un.fl_un_fec
#define lcd_cmap fl_un.fl_un_cmap
char res18[0xE00];
/* The DUET family has a second FEC here */
fec_t cp_fec2;
#define cp_fec1 cp_fec /* consistency macro */
/* Dual Ported RAM follows.
* There are many different formats for this memory area
* depending upon the devices used and options chosen.
* Some processors don't have all of it populated.
*/
u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
u_char cp_dparam[0x400]; /* Parameter RAM */
} cpm8xx_t;
/* Internal memory map.
*/
typedef struct immap {
sysconf8xx_t im_siu_conf; /* SIU Configuration */
pcmconf8xx_t im_pcmcia; /* PCMCIA Configuration */
memctl8xx_t im_memctl; /* Memory Controller */
sit8xx_t im_sit; /* System integration timers */
car8xx_t im_clkrst; /* Clocks and reset */
sitk8xx_t im_sitk; /* Sys int timer keys */
cark8xx_t im_clkrstk; /* Clocks and reset keys */
vid823_t im_vid; /* Video (823 only) */
lcd823_t im_lcd; /* LCD (823 only) */
i2c8xx_t im_i2c; /* I2C control/status */
sdma8xx_t im_sdma; /* SDMA control/status */
cpic8xx_t im_cpic; /* CPM Interrupt Controller */
iop8xx_t im_ioport; /* IO Port control/status */
cpmtimer8xx_t im_cpmtimer; /* CPM timers */
cpm8xx_t im_cpm; /* Communication processor */
} immap_t;
#endif /* __IMMAP_8XX__ */
#endif /* __KERNEL__ */

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extra/linux-2.6.10/include/asm-ppc/a.out.h Normal file
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#ifndef __PPC_A_OUT_H__
#define __PPC_A_OUT_H__
/* grabbed from the intel stuff */
#define STACK_TOP TASK_SIZE
struct exec
{
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
unsigned a_text; /* length of text, in bytes */
unsigned a_data; /* length of data, in bytes */
unsigned a_bss; /* length of uninitialized data area for file, in bytes */
unsigned a_syms; /* length of symbol table data in file, in bytes */
unsigned a_entry; /* start address */
unsigned a_trsize; /* length of relocation info for text, in bytes */
unsigned a_drsize; /* length of relocation info for data, in bytes */
};
#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
#endif

13
extra/linux-2.6.10/include/asm-ppc/agp.h Normal file
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#ifndef AGP_H
#define AGP_H 1
#include <asm/io.h>
/* nothing much needed here */
#define map_page_into_agp(page)
#define unmap_page_from_agp(page)
#define flush_agp_mappings()
#define flush_agp_cache() mb()
#endif

17
extra/linux-2.6.10/include/asm-ppc/amigahw.h Normal file
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#ifdef __KERNEL__
#ifndef __ASMPPC_AMIGAHW_H
#define __ASMPPC_AMIGAHW_H
#include <linux/config.h>
#include <asm-m68k/amigahw.h>
#undef CHIP_PHYSADDR
#ifdef CONFIG_APUS_FAST_EXCEPT
#define CHIP_PHYSADDR (0x000000)
#else
#define CHIP_PHYSADDR (0x004000)
#endif
#endif /* __ASMPPC_AMIGAHW_H */
#endif /* __KERNEL__ */

133
extra/linux-2.6.10/include/asm-ppc/amigaints.h Normal file
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/*
** amigaints.h -- Amiga Linux interrupt handling structs and prototypes
**
** Copyright 1992 by Greg Harp
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created 10/2/92 by Greg Harp
*/
#ifdef __KERNEL__
#ifndef _ASMm68k_AMIGAINTS_H_
#define _ASMm68k_AMIGAINTS_H_
/*
** Amiga Interrupt sources.
**
*/
#define AUTO_IRQS (8)
#define AMI_STD_IRQS (14)
#define CIA_IRQS (5)
#define AMI_IRQS (32) /* AUTO_IRQS+AMI_STD_IRQS+2*CIA_IRQS */
/* vertical blanking interrupt */
#define IRQ_AMIGA_VERTB 0
/* copper interrupt */
#define IRQ_AMIGA_COPPER 1
/* Audio interrupts */
#define IRQ_AMIGA_AUD0 2
#define IRQ_AMIGA_AUD1 3
#define IRQ_AMIGA_AUD2 4
#define IRQ_AMIGA_AUD3 5
/* Blitter done interrupt */
#define IRQ_AMIGA_BLIT 6
/* floppy disk interrupts */
#define IRQ_AMIGA_DSKSYN 7
#define IRQ_AMIGA_DSKBLK 8
/* builtin serial port interrupts */
#define IRQ_AMIGA_RBF 9
#define IRQ_AMIGA_TBE 10
/* software interrupts */
#define IRQ_AMIGA_SOFT 11
/* interrupts from external hardware */
#define IRQ_AMIGA_PORTS 12
#define IRQ_AMIGA_EXTER 13
/* CIA interrupt sources */
#define IRQ_AMIGA_CIAA 14
#define IRQ_AMIGA_CIAA_TA 14
#define IRQ_AMIGA_CIAA_TB 15
#define IRQ_AMIGA_CIAA_ALRM 16
#define IRQ_AMIGA_CIAA_SP 17
#define IRQ_AMIGA_CIAA_FLG 18
#define IRQ_AMIGA_CIAB 19
#define IRQ_AMIGA_CIAB_TA 19
#define IRQ_AMIGA_CIAB_TB 20
#define IRQ_AMIGA_CIAB_ALRM 21
#define IRQ_AMIGA_CIAB_SP 22
#define IRQ_AMIGA_CIAB_FLG 23
/* auto-vector interrupts */
#define IRQ_AMIGA_AUTO 24
#define IRQ_AMIGA_AUTO_0 24 /* This is just a dummy */
#define IRQ_AMIGA_AUTO_1 25
#define IRQ_AMIGA_AUTO_2 26
#define IRQ_AMIGA_AUTO_3 27
#define IRQ_AMIGA_AUTO_4 28
#define IRQ_AMIGA_AUTO_5 29
#define IRQ_AMIGA_AUTO_6 30
#define IRQ_AMIGA_AUTO_7 31
#define IRQ_FLOPPY IRQ_AMIGA_DSKBLK
/* INTREQR masks */
#define IRQ1_MASK 0x0007 /* INTREQR mask for IRQ 1 */
#define IRQ2_MASK 0x0008 /* INTREQR mask for IRQ 2 */
#define IRQ3_MASK 0x0070 /* INTREQR mask for IRQ 3 */
#define IRQ4_MASK 0x0780 /* INTREQR mask for IRQ 4 */
#define IRQ5_MASK 0x1800 /* INTREQR mask for IRQ 5 */
#define IRQ6_MASK 0x2000 /* INTREQR mask for IRQ 6 */
#define IRQ7_MASK 0x4000 /* INTREQR mask for IRQ 7 */
#define IF_SETCLR 0x8000 /* set/clr bit */
#define IF_INTEN 0x4000 /* master interrupt bit in INT* registers */
#define IF_EXTER 0x2000 /* external level 6 and CIA B interrupt */
#define IF_DSKSYN 0x1000 /* disk sync interrupt */
#define IF_RBF 0x0800 /* serial receive buffer full interrupt */
#define IF_AUD3 0x0400 /* audio channel 3 done interrupt */
#define IF_AUD2 0x0200 /* audio channel 2 done interrupt */
#define IF_AUD1 0x0100 /* audio channel 1 done interrupt */
#define IF_AUD0 0x0080 /* audio channel 0 done interrupt */
#define IF_BLIT 0x0040 /* blitter done interrupt */
#define IF_VERTB 0x0020 /* vertical blanking interrupt */
#define IF_COPER 0x0010 /* copper interrupt */
#define IF_PORTS 0x0008 /* external level 2 and CIA A interrupt */
#define IF_SOFT 0x0004 /* software initiated interrupt */
#define IF_DSKBLK 0x0002 /* diskblock DMA finished */
#define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */
extern void amiga_do_irq(int irq, struct pt_regs *fp);
extern void amiga_do_irq_list(int irq, struct pt_regs *fp);
/* CIA interrupt control register bits */
#define CIA_ICR_TA 0x01
#define CIA_ICR_TB 0x02
#define CIA_ICR_ALRM 0x04
#define CIA_ICR_SP 0x08
#define CIA_ICR_FLG 0x10
#define CIA_ICR_ALL 0x1f
#define CIA_ICR_SETCLR 0x80
/* to access the interrupt control registers of CIA's use only
** these functions, they behave exactly like the amiga os routines
*/
extern struct ciabase ciaa_base, ciab_base;
extern unsigned char cia_set_irq(unsigned int irq, int set);
extern unsigned char cia_able_irq(unsigned int irq, int enable);
#endif /* asm-m68k/amigaints.h */
#endif /* __KERNEL__ */

85
extra/linux-2.6.10/include/asm-ppc/amigappc.h Normal file
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/*
** asm-ppc/amigappc.h -- This header defines some values and pointers for
** the Phase 5 PowerUp card.
**
** Copyright 1997, 1998 by Phase5, Germany.
**
** This file is subject to the terms and conditions of the GNU General Public
** License. See the file COPYING in the main directory of this archive
** for more details.
**
** Created: 7/22/97 by Jesper Skov
*/
#ifdef __KERNEL__
#ifndef _M68K_AMIGAPPC_H
#define _M68K_AMIGAPPC_H
#ifndef __ASSEMBLY__
/* #include <asm/system.h> */
#define mb() __asm__ __volatile__ ("sync" : : : "memory")
#define APUS_WRITE(_a_, _v_) \
do { \
(*((volatile unsigned char *)(_a_)) = (_v_)); \
mb(); \
} while (0)
#define APUS_READ(_a_, _v_) \
do { \
(_v_) = (*((volatile unsigned char *)(_a_))); \
mb(); \
} while (0)
#endif /* ndef __ASSEMBLY__ */
/* Maybe add a [#ifdef WANT_ZTWOBASE] condition to amigahw.h? */
#define zTwoBase (0x80000000)
#define APUS_IPL_BASE (zTwoBase + 0x00f60000)
#define APUS_REG_RESET (APUS_IPL_BASE + 0x00)
#define APUS_REG_WAITSTATE (APUS_IPL_BASE + 0x10)
#define APUS_REG_SHADOW (APUS_IPL_BASE + 0x18)
#define APUS_REG_LOCK (APUS_IPL_BASE + 0x20)
#define APUS_REG_INT (APUS_IPL_BASE + 0x28)
#define APUS_IPL_EMU (APUS_IPL_BASE + 0x30)
#define APUS_INT_LVL (APUS_IPL_BASE + 0x38)
#define REGSHADOW_SETRESET (0x80)
#define REGSHADOW_SELFRESET (0x40)
#define REGLOCK_SETRESET (0x80)
#define REGLOCK_BLACKMAGICK1 (0x40)
#define REGLOCK_BLACKMAGICK2 (0x20)
#define REGLOCK_BLACKMAGICK3 (0x10)
#define REGWAITSTATE_SETRESET (0x80)
#define REGWAITSTATE_PPCW (0x08)
#define REGWAITSTATE_PPCR (0x04)
#define REGRESET_SETRESET (0x80)
#define REGRESET_PPCRESET (0x10)
#define REGRESET_M68KRESET (0x08)
#define REGRESET_AMIGARESET (0x04)
#define REGRESET_AUXRESET (0x02)
#define REGRESET_SCSIRESET (0x01)
#define REGINT_SETRESET (0x80)
#define REGINT_ENABLEIPL (0x02)
#define REGINT_INTMASTER (0x01)
#define IPLEMU_SETRESET (0x80)
#define IPLEMU_DISABLEINT (0x40)
#define IPLEMU_IPL2 (0x20)
#define IPLEMU_IPL1 (0x10)
#define IPLEMU_IPL0 (0x08)
#define IPLEMU_PPCIPL2 (0x04)
#define IPLEMU_PPCIPL1 (0x02)
#define IPLEMU_PPCIPL0 (0x01)
#define IPLEMU_IPLMASK (IPLEMU_PPCIPL2|IPLEMU_PPCIPL1|IPLEMU_PPCIPL0)
#define INTLVL_SETRESET (0x80)
#define INTLVL_MASK (0x7f)
#endif /* _M68k_AMIGAPPC_H */
#endif /* __KERNEL__ */

1
extra/linux-2.6.10/include/asm-ppc/amigayle.h Normal file
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#include <asm-m68k/amigayle.h>

1
extra/linux-2.6.10/include/asm-ppc/amipcmcia.h Normal file
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#include <asm-m68k/amipcmcia.h>

11
extra/linux-2.6.10/include/asm-ppc/ans-lcd.h Normal file
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#ifndef _PPC_ANS_LCD_H
#define _PPC_ANS_LCD_H
#define ANSLCD_MINOR 156
#define ANSLCD_CLEAR 0x01
#define ANSLCD_SENDCTRL 0x02
#define ANSLCD_SETSHORTDELAY 0x03
#define ANSLCD_SETLONGDELAY 0x04
#endif

214
extra/linux-2.6.10/include/asm-ppc/atomic.h Normal file
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/*
* PowerPC atomic operations
*/
#ifndef _ASM_PPC_ATOMIC_H_
#define _ASM_PPC_ATOMIC_H_
typedef struct { volatile int counter; } atomic_t;
#ifdef __KERNEL__
#define ATOMIC_INIT(i) { (i) }
#define atomic_read(v) ((v)->counter)
#define atomic_set(v,i) (((v)->counter) = (i))
extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
#ifdef CONFIG_SMP
#define SMP_SYNC "sync"
#define SMP_ISYNC "\n\tisync"
#else
#define SMP_SYNC ""
#define SMP_ISYNC
#endif
/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
* The old ATOMIC_SYNC_FIX covered some but not all of this.
*/
#ifdef CONFIG_IBM405_ERR77
#define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";"
#else
#define PPC405_ERR77(ra,rb)
#endif
static __inline__ void atomic_add(int a, atomic_t *v)
{
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%3 # atomic_add\n\
add %0,%2,%0\n"
PPC405_ERR77(0,%3)
" stwcx. %0,0,%3 \n\
bne- 1b"
: "=&r" (t), "=m" (v->counter)
: "r" (a), "r" (&v->counter), "m" (v->counter)
: "cc");
}
static __inline__ int atomic_add_return(int a, atomic_t *v)
{
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%2 # atomic_add_return\n\
add %0,%1,%0\n"
PPC405_ERR77(0,%2)
" stwcx. %0,0,%2 \n\
bne- 1b"
SMP_ISYNC
: "=&r" (t)
: "r" (a), "r" (&v->counter)
: "cc", "memory");
return t;
}
#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
static __inline__ void atomic_sub(int a, atomic_t *v)
{
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%3 # atomic_sub\n\
subf %0,%2,%0\n"
PPC405_ERR77(0,%3)
" stwcx. %0,0,%3 \n\
bne- 1b"
: "=&r" (t), "=m" (v->counter)
: "r" (a), "r" (&v->counter), "m" (v->counter)
: "cc");
}
static __inline__ int atomic_sub_return(int a, atomic_t *v)
{
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%2 # atomic_sub_return\n\
subf %0,%1,%0\n"
PPC405_ERR77(0,%2)
" stwcx. %0,0,%2 \n\
bne- 1b"
SMP_ISYNC
: "=&r" (t)
: "r" (a), "r" (&v->counter)
: "cc", "memory");
return t;
}
static __inline__ void atomic_inc(atomic_t *v)
{
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%2 # atomic_inc\n\
addic %0,%0,1\n"
PPC405_ERR77(0,%2)
" stwcx. %0,0,%2 \n\
bne- 1b"
: "=&r" (t), "=m" (v->counter)
: "r" (&v->counter), "m" (v->counter)
: "cc");
}
static __inline__ int atomic_inc_return(atomic_t *v)
{
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%1 # atomic_inc_return\n\
addic %0,%0,1\n"
PPC405_ERR77(0,%1)
" stwcx. %0,0,%1 \n\
bne- 1b"
SMP_ISYNC
: "=&r" (t)
: "r" (&v->counter)
: "cc", "memory");
return t;
}
/*
* atomic_inc_and_test - increment and test
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1
* and returns true if the result is zero, or false for all
* other cases.
*/
#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
static __inline__ void atomic_dec(atomic_t *v)
{
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%2 # atomic_dec\n\
addic %0,%0,-1\n"
PPC405_ERR77(0,%2)\
" stwcx. %0,0,%2\n\
bne- 1b"
: "=&r" (t), "=m" (v->counter)
: "r" (&v->counter), "m" (v->counter)
: "cc");
}
static __inline__ int atomic_dec_return(atomic_t *v)
{
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%1 # atomic_dec_return\n\
addic %0,%0,-1\n"
PPC405_ERR77(0,%1)
" stwcx. %0,0,%1\n\
bne- 1b"
SMP_ISYNC
: "=&r" (t)
: "r" (&v->counter)
: "cc", "memory");
return t;
}
#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
/*
* Atomically test *v and decrement if it is greater than 0.
* The function returns the old value of *v minus 1.
*/
static __inline__ int atomic_dec_if_positive(atomic_t *v)
{
int t;
__asm__ __volatile__(
"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
addic. %0,%0,-1\n\
blt- 2f\n"
PPC405_ERR77(0,%1)
" stwcx. %0,0,%1\n\
bne- 1b"
SMP_ISYNC
"\n\
2:" : "=&r" (t)
: "r" (&v->counter)
: "cc", "memory");
return t;
}
#define __MB __asm__ __volatile__ (SMP_SYNC : : : "memory")
#define smp_mb__before_atomic_dec() __MB
#define smp_mb__after_atomic_dec() __MB
#define smp_mb__before_atomic_inc() __MB
#define smp_mb__after_atomic_inc() __MB
#endif /* __KERNEL__ */
#endif /* _ASM_PPC_ATOMIC_H_ */

30
extra/linux-2.6.10/include/asm-ppc/backlight.h Normal file
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/*
* Routines for handling backlight control on PowerBooks
*
* For now, implementation resides in arch/ppc/kernel/pmac_support.c
*
*/
#ifdef __KERNEL__
#ifndef __ASM_PPC_BACKLIGHT_H
#define __ASM_PPC_BACKLIGHT_H
/* Abstract values */
#define BACKLIGHT_OFF 0
#define BACKLIGHT_MIN 1
#define BACKLIGHT_MAX 0xf
struct backlight_controller {
int (*set_enable)(int enable, int level, void *data);
int (*set_level)(int level, void *data);
};
extern void register_backlight_controller(struct backlight_controller *ctrler, void *data, char *type);
extern void unregister_backlight_controller(struct backlight_controller *ctrler, void *data);
extern int set_backlight_enable(int enable);
extern int get_backlight_enable(void);
extern int set_backlight_level(int level);
extern int get_backlight_level(void);
#endif
#endif /* __KERNEL__ */

460
extra/linux-2.6.10/include/asm-ppc/bitops.h Normal file
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/*
* bitops.h: Bit string operations on the ppc
*/
#ifdef __KERNEL__
#ifndef _PPC_BITOPS_H
#define _PPC_BITOPS_H
#include <linux/config.h>
#include <linux/compiler.h>
#include <asm/byteorder.h>
#include <asm/atomic.h>
/*
* The test_and_*_bit operations are taken to imply a memory barrier
* on SMP systems.
*/
#ifdef CONFIG_SMP
#define SMP_WMB "eieio\n"
#define SMP_MB "\nsync"
#else
#define SMP_WMB
#define SMP_MB
#endif /* CONFIG_SMP */
static __inline__ void set_bit(int nr, volatile unsigned long * addr)
{
unsigned long old;
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
__asm__ __volatile__("\n\
1: lwarx %0,0,%3 \n\
or %0,%0,%2 \n"
PPC405_ERR77(0,%3)
" stwcx. %0,0,%3 \n\
bne- 1b"
: "=&r" (old), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc" );
}
/*
* non-atomic version
*/
static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
*p |= mask;
}
/*
* clear_bit doesn't imply a memory barrier
*/
#define smp_mb__before_clear_bit() smp_mb()
#define smp_mb__after_clear_bit() smp_mb()
static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
{
unsigned long old;
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
__asm__ __volatile__("\n\
1: lwarx %0,0,%3 \n\
andc %0,%0,%2 \n"
PPC405_ERR77(0,%3)
" stwcx. %0,0,%3 \n\
bne- 1b"
: "=&r" (old), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc");
}
/*
* non-atomic version
*/
static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
*p &= ~mask;
}
static __inline__ void change_bit(int nr, volatile unsigned long *addr)
{
unsigned long old;
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
__asm__ __volatile__("\n\
1: lwarx %0,0,%3 \n\
xor %0,%0,%2 \n"
PPC405_ERR77(0,%3)
" stwcx. %0,0,%3 \n\
bne- 1b"
: "=&r" (old), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc");
}
/*
* non-atomic version
*/
static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
*p ^= mask;
}
/*
* test_and_*_bit do imply a memory barrier (?)
*/
static __inline__ int test_and_set_bit(int nr, volatile unsigned long *addr)
{
unsigned int old, t;
unsigned int mask = 1 << (nr & 0x1f);
volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
__asm__ __volatile__(SMP_WMB "\n\
1: lwarx %0,0,%4 \n\
or %1,%0,%3 \n"
PPC405_ERR77(0,%4)
" stwcx. %1,0,%4 \n\
bne 1b"
SMP_MB
: "=&r" (old), "=&r" (t), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc", "memory");
return (old & mask) != 0;
}
/*
* non-atomic version
*/
static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
unsigned long old = *p;
*p = old | mask;
return (old & mask) != 0;
}
static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
{
unsigned int old, t;
unsigned int mask = 1 << (nr & 0x1f);
volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
__asm__ __volatile__(SMP_WMB "\n\
1: lwarx %0,0,%4 \n\
andc %1,%0,%3 \n"
PPC405_ERR77(0,%4)
" stwcx. %1,0,%4 \n\
bne 1b"
SMP_MB
: "=&r" (old), "=&r" (t), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc", "memory");
return (old & mask) != 0;
}
/*
* non-atomic version
*/
static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
unsigned long old = *p;
*p = old & ~mask;
return (old & mask) != 0;
}
static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
{
unsigned int old, t;
unsigned int mask = 1 << (nr & 0x1f);
volatile unsigned int *p = ((volatile unsigned int *)addr) + (nr >> 5);
__asm__ __volatile__(SMP_WMB "\n\
1: lwarx %0,0,%4 \n\
xor %1,%0,%3 \n"
PPC405_ERR77(0,%4)
" stwcx. %1,0,%4 \n\
bne 1b"
SMP_MB
: "=&r" (old), "=&r" (t), "=m" (*p)
: "r" (mask), "r" (p), "m" (*p)
: "cc", "memory");
return (old & mask) != 0;
}
/*
* non-atomic version
*/
static __inline__ int __test_and_change_bit(int nr, volatile unsigned long *addr)
{
unsigned long mask = 1 << (nr & 0x1f);
unsigned long *p = ((unsigned long *)addr) + (nr >> 5);
unsigned long old = *p;
*p = old ^ mask;
return (old & mask) != 0;
}
static __inline__ int test_bit(int nr, __const__ volatile unsigned long *addr)
{
return ((addr[nr >> 5] >> (nr & 0x1f)) & 1) != 0;
}
/* Return the bit position of the most significant 1 bit in a word */
static __inline__ int __ilog2(unsigned long x)
{
int lz;
asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
return 31 - lz;
}
static __inline__ int ffz(unsigned long x)
{
if ((x = ~x) == 0)
return 32;
return __ilog2(x & -x);
}
static inline int __ffs(unsigned long x)
{
return __ilog2(x & -x);
}
/*
* ffs: find first bit set. This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
static __inline__ int ffs(int x)
{
return __ilog2(x & -x) + 1;
}
/*
* fls: find last (most-significant) bit set.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
static __inline__ int fls(unsigned int x)
{
int lz;
asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
return 32 - lz;
}
/*
* hweightN: returns the hamming weight (i.e. the number
* of bits set) of a N-bit word
*/
#define hweight32(x) generic_hweight32(x)
#define hweight16(x) generic_hweight16(x)
#define hweight8(x) generic_hweight8(x)
/*
* Find the first bit set in a 140-bit bitmap.
* The first 100 bits are unlikely to be set.
*/
static inline int sched_find_first_bit(const unsigned long *b)
{
if (unlikely(b[0]))
return __ffs(b[0]);
if (unlikely(b[1]))
return __ffs(b[1]) + 32;
if (unlikely(b[2]))
return __ffs(b[2]) + 64;
if (b[3])
return __ffs(b[3]) + 96;
return __ffs(b[4]) + 128;
}
/**
* find_next_bit - find the next set bit in a memory region
* @addr: The address to base the search on
* @offset: The bitnumber to start searching at
* @size: The maximum size to search
*/
static __inline__ unsigned long find_next_bit(const unsigned long *addr,
unsigned long size, unsigned long offset)
{
unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
unsigned int result = offset & ~31UL;
unsigned int tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *p++;
tmp &= ~0UL << offset;
if (size < 32)
goto found_first;
if (tmp)
goto found_middle;
size -= 32;
result += 32;
}
while (size >= 32) {
if ((tmp = *p++) != 0)
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = *p;
found_first:
tmp &= ~0UL >> (32 - size);
if (tmp == 0UL) /* Are any bits set? */
return result + size; /* Nope. */
found_middle:
return result + __ffs(tmp);
}
/**
* find_first_bit - find the first set bit in a memory region
* @addr: The address to start the search at
* @size: The maximum size to search
*
* Returns the bit-number of the first set bit, not the number of the byte
* containing a bit.
*/
#define find_first_bit(addr, size) \
find_next_bit((addr), (size), 0)
/*
* This implementation of find_{first,next}_zero_bit was stolen from
* Linus' asm-alpha/bitops.h.
*/
#define find_first_zero_bit(addr, size) \
find_next_zero_bit((addr), (size), 0)
static __inline__ unsigned long find_next_zero_bit(const unsigned long *addr,
unsigned long size, unsigned long offset)
{
unsigned int * p = ((unsigned int *) addr) + (offset >> 5);
unsigned int result = offset & ~31UL;
unsigned int tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = *p++;
tmp |= ~0UL >> (32-offset);
if (size < 32)
goto found_first;
if (tmp != ~0U)
goto found_middle;
size -= 32;
result += 32;
}
while (size >= 32) {
if ((tmp = *p++) != ~0U)
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = *p;
found_first:
tmp |= ~0UL << size;
if (tmp == ~0UL) /* Are any bits zero? */
return result + size; /* Nope. */
found_middle:
return result + ffz(tmp);
}
#define ext2_set_bit(nr, addr) __test_and_set_bit((nr) ^ 0x18, (unsigned long *)(addr))
#define ext2_set_bit_atomic(lock, nr, addr) test_and_set_bit((nr) ^ 0x18, (unsigned long *)(addr))
#define ext2_clear_bit(nr, addr) __test_and_clear_bit((nr) ^ 0x18, (unsigned long *)(addr))
#define ext2_clear_bit_atomic(lock, nr, addr) test_and_clear_bit((nr) ^ 0x18, (unsigned long *)(addr))
static __inline__ int ext2_test_bit(int nr, __const__ void * addr)
{
__const__ unsigned char *ADDR = (__const__ unsigned char *) addr;
return (ADDR[nr >> 3] >> (nr & 7)) & 1;
}
/*
* This implementation of ext2_find_{first,next}_zero_bit was stolen from
* Linus' asm-alpha/bitops.h and modified for a big-endian machine.
*/
#define ext2_find_first_zero_bit(addr, size) \
ext2_find_next_zero_bit((addr), (size), 0)
static __inline__ unsigned long ext2_find_next_zero_bit(const void *addr,
unsigned long size, unsigned long offset)
{
unsigned int *p = ((unsigned int *) addr) + (offset >> 5);
unsigned int result = offset & ~31UL;
unsigned int tmp;
if (offset >= size)
return size;
size -= result;
offset &= 31UL;
if (offset) {
tmp = cpu_to_le32p(p++);
tmp |= ~0UL >> (32-offset);
if (size < 32)
goto found_first;
if (tmp != ~0U)
goto found_middle;
size -= 32;
result += 32;
}
while (size >= 32) {
if ((tmp = cpu_to_le32p(p++)) != ~0U)
goto found_middle;
result += 32;
size -= 32;
}
if (!size)
return result;
tmp = cpu_to_le32p(p);
found_first:
tmp |= ~0U << size;
if (tmp == ~0UL) /* Are any bits zero? */
return result + size; /* Nope. */
found_middle:
return result + ffz(tmp);
}
/* Bitmap functions for the minix filesystem. */
#define minix_test_and_set_bit(nr,addr) ext2_set_bit(nr,addr)
#define minix_set_bit(nr,addr) ((void)ext2_set_bit(nr,addr))
#define minix_test_and_clear_bit(nr,addr) ext2_clear_bit(nr,addr)
#define minix_test_bit(nr,addr) ext2_test_bit(nr,addr)
#define minix_find_first_zero_bit(addr,size) ext2_find_first_zero_bit(addr,size)
#endif /* _PPC_BITOPS_H */
#endif /* __KERNEL__ */

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/*
* Non-machine dependent bootinfo structure. Basic idea
* borrowed from the m68k.
*
* Copyright (C) 1999 Cort Dougan <cort@ppc.kernel.org>
*/
#ifdef __KERNEL__
#ifndef _PPC_BOOTINFO_H
#define _PPC_BOOTINFO_H
#include <linux/config.h>
#include <asm/page.h>
#if defined(CONFIG_APUS) && !defined(__BOOTER__)
#include <asm-m68k/bootinfo.h>
#else
struct bi_record {
unsigned long tag; /* tag ID */
unsigned long size; /* size of record (in bytes) */
unsigned long data[0]; /* data */
};
#define BI_FIRST 0x1010 /* first record - marker */
#define BI_LAST 0x1011 /* last record - marker */
#define BI_CMD_LINE 0x1012
#define BI_BOOTLOADER_ID 0x1013
#define BI_INITRD 0x1014
#define BI_SYSMAP 0x1015
#define BI_MACHTYPE 0x1016
#define BI_MEMSIZE 0x1017
#define BI_BOARD_INFO 0x1018
extern struct bi_record *find_bootinfo(void);
extern void bootinfo_init(struct bi_record *rec);
extern void bootinfo_append(unsigned long tag, unsigned long size, void * data);
extern void parse_bootinfo(struct bi_record *rec);
extern unsigned long boot_mem_size;
static inline struct bi_record *
bootinfo_addr(unsigned long offset)
{
return (struct bi_record *)_ALIGN((offset) + (1 << 20) - 1,
(1 << 20));
}
#endif /* CONFIG_APUS */
#endif /* _PPC_BOOTINFO_H */
#endif /* __KERNEL__ */

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/*
* This file describes the structure passed from the BootX application
* (for MacOS) when it is used to boot Linux.
*
* Written by Benjamin Herrenschmidt.
*/
#ifndef __ASM_BOOTX_H__
#define __ASM_BOOTX_H__
#ifdef macintosh
#include <Types.h>
#include "linux_type_defs.h"
#endif
#ifdef macintosh
/* All this requires PowerPC alignment */
#pragma options align=power
#endif
/* On kernel entry:
*
* r3 = 0x426f6f58 ('BooX')
* r4 = pointer to boot_infos
* r5 = NULL
*
* Data and instruction translation disabled, interrupts
* disabled, kernel loaded at physical 0x00000000 on PCI
* machines (will be different on NuBus).
*/
#define BOOT_INFO_VERSION 5
#define BOOT_INFO_COMPATIBLE_VERSION 1
/* Bit in the architecture flag mask. More to be defined in
future versions. Note that either BOOT_ARCH_PCI or
BOOT_ARCH_NUBUS is set. The other BOOT_ARCH_NUBUS_xxx are
set additionally when BOOT_ARCH_NUBUS is set.
*/
#define BOOT_ARCH_PCI 0x00000001UL
#define BOOT_ARCH_NUBUS 0x00000002UL
#define BOOT_ARCH_NUBUS_PDM 0x00000010UL
#define BOOT_ARCH_NUBUS_PERFORMA 0x00000020UL
#define BOOT_ARCH_NUBUS_POWERBOOK 0x00000040UL
/* Maximum number of ranges in phys memory map */
#define MAX_MEM_MAP_SIZE 26
/* This is the format of an element in the physical memory map. Note that
the map is optional and current BootX will only build it for pre-PCI
machines */
typedef struct boot_info_map_entry
{
__u32 physAddr; /* Physical starting address */
__u32 size; /* Size in bytes */
} boot_info_map_entry_t;
/* Here are the boot informations that are passed to the bootstrap
* Note that the kernel arguments and the device tree are appended
* at the end of this structure. */
typedef struct boot_infos
{
/* Version of this structure */
__u32 version;
/* backward compatible down to version: */
__u32 compatible_version;
/* NEW (vers. 2) this holds the current _logical_ base addr of
the frame buffer (for use by early boot message) */
__u8* logicalDisplayBase;
/* NEW (vers. 4) Apple's machine identification */
__u32 machineID;
/* NEW (vers. 4) Detected hw architecture */
__u32 architecture;
/* The device tree (internal addresses relative to the beginning of the tree,
* device tree offset relative to the beginning of this structure).
* On pre-PCI macintosh (BOOT_ARCH_PCI bit set to 0 in architecture), this
* field is 0.
*/
__u32 deviceTreeOffset; /* Device tree offset */
__u32 deviceTreeSize; /* Size of the device tree */
/* Some infos about the current MacOS display */
__u32 dispDeviceRect[4]; /* left,top,right,bottom */
__u32 dispDeviceDepth; /* (8, 16 or 32) */
__u8* dispDeviceBase; /* base address (physical) */
__u32 dispDeviceRowBytes; /* rowbytes (in bytes) */
__u32 dispDeviceColorsOffset; /* Colormap (8 bits only) or 0 (*) */
/* Optional offset in the registry to the current
* MacOS display. (Can be 0 when not detected) */
__u32 dispDeviceRegEntryOffset;
/* Optional pointer to boot ramdisk (offset from this structure) */
__u32 ramDisk;
__u32 ramDiskSize; /* size of ramdisk image */
/* Kernel command line arguments (offset from this structure) */
__u32 kernelParamsOffset;
/* ALL BELOW NEW (vers. 4) */
/* This defines the physical memory. Valid with BOOT_ARCH_NUBUS flag
(non-PCI) only. On PCI, memory is contiguous and it's size is in the
device-tree. */
boot_info_map_entry_t
physMemoryMap[MAX_MEM_MAP_SIZE]; /* Where the phys memory is */
__u32 physMemoryMapSize; /* How many entries in map */
/* The framebuffer size (optional, currently 0) */
__u32 frameBufferSize; /* Represents a max size, can be 0. */
/* NEW (vers. 5) */
/* Total params size (args + colormap + device tree + ramdisk) */
__u32 totalParamsSize;
} boot_infos_t;
/* (*) The format of the colormap is 256 * 3 * 2 bytes. Each color index is represented
* by 3 short words containing a 16 bits (unsigned) color component.
* Later versions may contain the gamma table for direct-color devices here.
*/
#define BOOTX_COLORTABLE_SIZE (256UL*3UL*2UL)
#ifdef macintosh
#pragma options align=reset
#endif
#endif

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/*
* A collection of structures, addresses, and values associated with
* the Bright Star Engineering ip-Engine board. Copied from the MBX stuff.
*
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
*/
#ifndef __MACH_BSEIP_DEFS
#define __MACH_BSEIP_DEFS
#ifndef __ASSEMBLY__
/* A Board Information structure that is given to a program when
* prom starts it up.
*/
typedef struct bd_info {
unsigned int bi_memstart; /* Memory start address */
unsigned int bi_memsize; /* Memory (end) size in bytes */
unsigned int bi_intfreq; /* Internal Freq, in Hz */
unsigned int bi_busfreq; /* Bus Freq, in Hz */
unsigned char bi_enetaddr[6];
unsigned int bi_baudrate;
} bd_t;
extern bd_t m8xx_board_info;
/* Memory map is configured by the PROM startup.
* All we need to get started is the IMMR.
*/
#define IMAP_ADDR ((uint)0xff000000)
#define IMAP_SIZE ((uint)(64 * 1024))
#define PCMCIA_MEM_ADDR ((uint)0x04000000)
#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
#endif /* !__ASSEMBLY__ */
/* We don't use the 8259.
*/
#define NR_8259_INTS 0
#endif

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/*
* Definitions for using the procedures in btext.c.
*
* Benjamin Herrenschmidt <benh@kernel.crashing.org>
*/
#ifndef __PPC_BTEXT_H
#define __PPC_BTEXT_H
#ifdef __KERNEL__
#include <asm/bootx.h>
extern void btext_clearscreen(void);
extern void btext_flushscreen(void);
extern unsigned long disp_BAT[2];
extern boot_infos_t disp_bi;
extern int boot_text_mapped;
void btext_init(boot_infos_t *bi);
void btext_welcome(void);
void btext_prepare_BAT(void);
void btext_setup_display(int width, int height, int depth, int pitch,
unsigned long address);
void map_boot_text(void);
void btext_update_display(unsigned long phys, int width, int height,
int depth, int pitch);
void btext_drawchar(char c);
void btext_drawstring(const char *str);
void btext_drawhex(unsigned long v);
#endif /* __KERNEL__ */
#endif /* __PPC_BTEXT_H */

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#ifndef _PPC_BUG_H
#define _PPC_BUG_H
struct bug_entry {
unsigned long bug_addr;
int line;
const char *file;
const char *function;
};
/*
* If this bit is set in the line number it means that the trap
* is for WARN_ON rather than BUG or BUG_ON.
*/
#define BUG_WARNING_TRAP 0x1000000
#define BUG() do { \
__asm__ __volatile__( \
"1: twi 31,0,0\n" \
".section __bug_table,\"a\"\n\t" \
" .long 1b,%0,%1,%2\n" \
".previous" \
: : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
} while (0)
#define BUG_ON(x) do { \
if (!__builtin_constant_p(x) || (x)) { \
__asm__ __volatile__( \
"1: twnei %0,0\n" \
".section __bug_table,\"a\"\n\t" \
" .long 1b,%1,%2,%3\n" \
".previous" \
: : "r" (x), "i" (__LINE__), "i" (__FILE__), \
"i" (__FUNCTION__)); \
} \
} while (0)
#define WARN_ON(x) do { \
if (!__builtin_constant_p(x) || (x)) { \
__asm__ __volatile__( \
"1: twnei %0,0\n" \
".section __bug_table,\"a\"\n\t" \
" .long 1b,%1,%2,%3\n" \
".previous" \
: : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \
"i" (__FILE__), "i" (__FUNCTION__)); \
} \
} while (0)
#define HAVE_ARCH_BUG
#define HAVE_ARCH_BUG_ON
#define HAVE_ARCH_WARN_ON
#include <asm-generic/bug.h>
#endif

6
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/*
* This file is included by 'init/main.c'
*/
extern void
check_bugs(void);

76
extra/linux-2.6.10/include/asm-ppc/byteorder.h Normal file
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#ifndef _PPC_BYTEORDER_H
#define _PPC_BYTEORDER_H
#include <asm/types.h>
#include <linux/compiler.h>
#ifdef __GNUC__
#ifdef __KERNEL__
extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
{
unsigned val;
__asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
return val;
}
extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
{
__asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
}
extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
{
unsigned val;
__asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
return val;
}
extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
{
__asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
}
static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
{
__u16 result;
__asm__("rlwimi %0,%2,8,16,23" : "=&r" (result) : "0" (value >> 8), "r" (value));
return result;
}
static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
{
__u32 result;
__asm__("rlwimi %0,%2,24,16,23" : "=&r" (result) : "0" (value>>24), "r" (value));
__asm__("rlwimi %0,%2,8,8,15" : "=&r" (result) : "0" (result), "r" (value));
__asm__("rlwimi %0,%2,24,0,7" : "=&r" (result) : "0" (result), "r" (value));
return result;
}
#define __arch__swab32(x) ___arch__swab32(x)
#define __arch__swab16(x) ___arch__swab16(x)
/* The same, but returns converted value from the location pointer by addr. */
#define __arch__swab16p(addr) ld_le16(addr)
#define __arch__swab32p(addr) ld_le32(addr)
/* The same, but do the conversion in situ, ie. put the value back to addr. */
#define __arch__swab16s(addr) st_le16(addr,*addr)
#define __arch__swab32s(addr) st_le32(addr,*addr)
#endif /* __KERNEL__ */
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
#endif
#endif /* __GNUC__ */
#include <linux/byteorder/big_endian.h>
#endif /* _PPC_BYTEORDER_H */

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/*
* include/asm-ppc/cache.h
*/
#ifdef __KERNEL__
#ifndef __ARCH_PPC_CACHE_H
#define __ARCH_PPC_CACHE_H
#include <linux/config.h>
/* bytes per L1 cache line */
#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
#define L1_CACHE_LINE_SIZE 16
#define LG_L1_CACHE_LINE_SIZE 4
#define MAX_COPY_PREFETCH 1
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_LINE_SIZE 128
#define LG_L1_CACHE_LINE_SIZE 7
#define MAX_COPY_PREFETCH 1
#else
#define L1_CACHE_LINE_SIZE 32
#define LG_L1_CACHE_LINE_SIZE 5
#define MAX_COPY_PREFETCH 4
#endif
#define L1_CACHE_BYTES L1_CACHE_LINE_SIZE
#define L1_CACHE_SHIFT LG_L1_CACHE_LINE_SIZE
#define SMP_CACHE_BYTES L1_CACHE_BYTES
#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1))
#define L1_CACHE_PAGES 8
#ifndef __ASSEMBLY__
extern void clean_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache_range(unsigned long start, unsigned long stop);
extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
extern void flush_dcache_all(void);
#endif /* __ASSEMBLY__ */
/* prep registers for L2 */
#define CACHECRBA 0x80000823 /* Cache configuration register address */
#define L2CACHE_MASK 0x03 /* Mask for 2 L2 Cache bits */
#define L2CACHE_512KB 0x00 /* 512KB */
#define L2CACHE_256KB 0x01 /* 256KB */
#define L2CACHE_1MB 0x02 /* 1MB */
#define L2CACHE_NONE 0x03 /* NONE */
#define L2CACHE_PARITY 0x08 /* Mask for L2 Cache Parity Protected bit */
#ifdef CONFIG_8xx
/* Cache control on the MPC8xx is provided through some additional
* special purpose registers.
*/
#define IC_CST 560 /* Instruction cache control/status */
#define IC_ADR 561 /* Address needed for some commands */
#define IC_DAT 562 /* Read-only data register */
#define DC_CST 568 /* Data cache control/status */
#define DC_ADR 569 /* Address needed for some commands */
#define DC_DAT 570 /* Read-only data register */
/* Commands. Only the first few are available to the instruction cache.
*/
#define IDC_ENABLE 0x02000000 /* Cache enable */
#define IDC_DISABLE 0x04000000 /* Cache disable */
#define IDC_LDLCK 0x06000000 /* Load and lock */
#define IDC_UNLINE 0x08000000 /* Unlock line */
#define IDC_UNALL 0x0a000000 /* Unlock all */
#define IDC_INVALL 0x0c000000 /* Invalidate all */
#define DC_FLINE 0x0e000000 /* Flush data cache line */
#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
#define DC_SLES 0x05000000 /* Set little endian swap mode */
#define DC_CLES 0x07000000 /* Clear little endian swap mode */
/* Status.
*/
#define IDC_ENABLED 0x80000000 /* Cache is enabled */
#define IDC_CERR1 0x00200000 /* Cache error 1 */
#define IDC_CERR2 0x00100000 /* Cache error 2 */
#define IDC_CERR3 0x00080000 /* Cache error 3 */
#define DC_DFWT 0x40000000 /* Data cache is forced write through */
#define DC_LES 0x20000000 /* Caches are little endian mode */
#endif /* CONFIG_8xx */
#endif
#endif /* __KERNEL__ */

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/*
* include/asm-ppc/cacheflush.h
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifdef __KERNEL__
#ifndef _PPC_CACHEFLUSH_H
#define _PPC_CACHEFLUSH_H
#include <linux/mm.h>
/*
* No cache flushing is required when address mappings are
* changed, because the caches on PowerPCs are physically
* addressed. -- paulus
* Also, when SMP we use the coherency (M) bit of the
* BATs and PTEs. -- Cort
*/
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_range(vma, a, b) do { } while (0)
#define flush_cache_page(vma, p) do { } while (0)
#define flush_icache_page(vma, page) do { } while (0)
#define flush_cache_vmap(start, end) do { } while (0)
#define flush_cache_vunmap(start, end) do { } while (0)
extern void flush_dcache_page(struct page *page);
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
extern void flush_icache_range(unsigned long, unsigned long);
extern void flush_icache_user_range(struct vm_area_struct *vma,
struct page *page, unsigned long addr, int len);
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { memcpy(dst, src, len); \
flush_icache_user_range(vma, page, vaddr, len); \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
extern void __flush_dcache_icache(void *page_va);
extern void __flush_dcache_icache_phys(unsigned long physaddr);
extern void flush_dcache_icache_page(struct page *page);
#endif /* _PPC_CACHEFLUSH_H */
#endif /* __KERNEL__ */

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#ifdef __KERNEL__
#ifndef _PPC_CHECKSUM_H
#define _PPC_CHECKSUM_H
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
extern unsigned int csum_partial(const unsigned char * buff, int len,
unsigned int sum);
/*
* Computes the checksum of a memory block at src, length len,
* and adds in "sum" (32-bit), while copying the block to dst.
* If an access exception occurs on src or dst, it stores -EFAULT
* to *src_err or *dst_err respectively (if that pointer is not
* NULL), and, for an error on src, zeroes the rest of dst.
*
* Like csum_partial, this must be called with even lengths,
* except for the last fragment.
*/
extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
int len, unsigned int sum,
int *src_err, int *dst_err);
#define csum_partial_copy_from_user(src, dst, len, sum, errp) \
csum_partial_copy_generic((__force void *)(src), (dst), (len), (sum), (errp), NULL)
/* FIXME: this needs to be written to really do no check -- Cort */
#define csum_partial_copy_nocheck(src, dst, len, sum) \
csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
/*
* turns a 32-bit partial checksum (e.g. from csum_partial) into a
* 1's complement 16-bit checksum.
*/
static inline unsigned int csum_fold(unsigned int sum)
{
unsigned int tmp;
/* swap the two 16-bit halves of sum */
__asm__("rlwinm %0,%1,16,0,31" : "=r" (tmp) : "r" (sum));
/* if there is a carry from adding the two 16-bit halves,
it will carry from the lower half into the upper half,
giving us the correct sum in the upper half. */
sum = ~(sum + tmp) >> 16;
return sum;
}
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
{
return csum_fold(csum_partial(buff, len, 0));
}
/*
* FIXME: I swiped this one from the sparc and made minor modifications.
* It may not be correct. -- Cort
*/
static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
unsigned long daddr,
unsigned short len,
unsigned short proto,
unsigned int sum)
{
__asm__("\n\
addc %0,%0,%1 \n\
adde %0,%0,%2 \n\
adde %0,%0,%3 \n\
addze %0,%0 \n\
"
: "=r" (sum)
: "r" (daddr), "r"(saddr), "r"((proto<<16)+len), "0"(sum));
return sum;
}
/*
* This is a version of ip_compute_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries. ihl is the number
* of 32-bit words and is always >= 5.
*/
extern unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl);
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
extern unsigned short csum_tcpudp_magic(unsigned long saddr,
unsigned long daddr,
unsigned short len,
unsigned short proto,
unsigned int sum);
#endif
#endif /* __KERNEL__ */

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/*
* MPC8xx Communication Processor Module.
* Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
*
* This file contains structures and information for the communication
* processor channels. Some CPM control and status is available
* throught the MPC8xx internal memory map. See immap.h for details.
* This file only contains what I need for the moment, not the total
* CPM capabilities. I (or someone else) will add definitions as they
* are needed. -- Dan
*
* On the MBX board, EPPC-Bug loads CPM microcode into the first 512
* bytes of the DP RAM and relocates the I2C parameter area to the
* IDMA1 space. The remaining DP RAM is available for buffer descriptors
* or other use.
*/
#ifndef __CPM_8XX__
#define __CPM_8XX__
#include <linux/config.h>
#include <asm/8xx_immap.h>
#include <asm/ptrace.h>
/* CPM Command register.
*/
#define CPM_CR_RST ((ushort)0x8000)
#define CPM_CR_OPCODE ((ushort)0x0f00)
#define CPM_CR_CHAN ((ushort)0x00f0)
#define CPM_CR_FLG ((ushort)0x0001)
/* Some commands (there are more...later)
*/
#define CPM_CR_INIT_TRX ((ushort)0x0000)
#define CPM_CR_INIT_RX ((ushort)0x0001)
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR
/* Channel numbers.
*/
#define CPM_CR_CH_SCC1 ((ushort)0x0000)
#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
#define CPM_CR_CH_SCC2 ((ushort)0x0004)
#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
#define CPM_CR_CH_TIMER CPM_CR_CH_SPI
#define CPM_CR_CH_SCC3 ((ushort)0x0008)
#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
#define CPM_CR_CH_SCC4 ((ushort)0x000c)
#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
/* The dual ported RAM is multi-functional. Some areas can be (and are
* being) used for microcode. There is an area that can only be used
* as data ram for buffer descriptors, which is all we use right now.
* Currently the first 512 and last 256 bytes are used for microcode.
*/
#define CPM_DATAONLY_BASE ((uint)0x0800)
#define CPM_DATAONLY_SIZE ((uint)0x0700)
#define CPM_DP_NOSPACE ((uint)0x7fffffff)
static inline long IS_DPERR(const uint offset)
{
return (uint)offset > (uint)-1000L;
}
/* Export the base address of the communication processor registers
* and dual port ram.
*/
extern cpm8xx_t *cpmp; /* Pointer to comm processor */
extern uint cpm_dpalloc(uint size, uint align);
extern int cpm_dpfree(uint offset);
extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
extern void cpm_dpdump(void);
extern void *cpm_dpram_addr(uint offset);
extern void cpm_setbrg(uint brg, uint rate);
extern uint m8xx_cpm_hostalloc(uint size);
extern int m8xx_cpm_hostfree(uint start);
extern void m8xx_cpm_hostdump(void);
/* Buffer descriptors used by many of the CPM protocols.
*/
typedef struct cpm_buf_desc {
ushort cbd_sc; /* Status and Control */
ushort cbd_datlen; /* Data length in buffer */
uint cbd_bufaddr; /* Buffer address in host memory */
} cbd_t;
#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
#define BD_SC_BR ((ushort)0x0020) /* Break received */
#define BD_SC_FR ((ushort)0x0010) /* Framing error */
#define BD_SC_PR ((ushort)0x0008) /* Parity error */
#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */
#define BD_SC_OV ((ushort)0x0002) /* Overrun */
#define BD_SC_UN ((ushort)0x0002) /* Underrun */
#define BD_SC_CD ((ushort)0x0001) /* ?? */
#define BD_SC_CL ((ushort)0x0001) /* Collision */
/* Parameter RAM offsets.
*/
#define PROFF_SCC1 ((uint)0x0000)
#define PROFF_IIC ((uint)0x0080)
#define PROFF_SCC2 ((uint)0x0100)
#define PROFF_SPI ((uint)0x0180)
#define PROFF_SCC3 ((uint)0x0200)
#define PROFF_SMC1 ((uint)0x0280)
#define PROFF_SCC4 ((uint)0x0300)
#define PROFF_SMC2 ((uint)0x0380)
/* Define enough so I can at least use the serial port as a UART.
* The MBX uses SMC1 as the host serial port.
*/
typedef struct smc_uart {
ushort smc_rbase; /* Rx Buffer descriptor base address */
ushort smc_tbase; /* Tx Buffer descriptor base address */
u_char smc_rfcr; /* Rx function code */
u_char smc_tfcr; /* Tx function code */
ushort smc_mrblr; /* Max receive buffer length */
uint smc_rstate; /* Internal */
uint smc_idp; /* Internal */
ushort smc_rbptr; /* Internal */
ushort smc_ibc; /* Internal */
uint smc_rxtmp; /* Internal */
uint smc_tstate; /* Internal */
uint smc_tdp; /* Internal */
ushort smc_tbptr; /* Internal */
ushort smc_tbc; /* Internal */
uint smc_txtmp; /* Internal */
ushort smc_maxidl; /* Maximum idle characters */
ushort smc_tmpidl; /* Temporary idle counter */
ushort smc_brklen; /* Last received break length */
ushort smc_brkec; /* rcv'd break condition counter */
ushort smc_brkcr; /* xmt break count register */
ushort smc_rmask; /* Temporary bit mask */
char res1[8]; /* Reserved */
ushort smc_rpbase; /* Relocation pointer */
} smc_uart_t;
/* Function code bits.
*/
#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
/* SMC uart mode register.
*/
#define SMCMR_REN ((ushort)0x0001)
#define SMCMR_TEN ((ushort)0x0002)
#define SMCMR_DM ((ushort)0x000c)
#define SMCMR_SM_GCI ((ushort)0x0000)
#define SMCMR_SM_UART ((ushort)0x0020)
#define SMCMR_SM_TRANS ((ushort)0x0030)
#define SMCMR_SM_MASK ((ushort)0x0030)
#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
#define SMCMR_REVD SMCMR_PM_EVEN
#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
#define SMCMR_BS SMCMR_PEN
#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
/* SMC2 as Centronics parallel printer. It is half duplex, in that
* it can only receive or transmit. The parameter ram values for
* each direction are either unique or properly overlap, so we can
* include them in one structure.
*/
typedef struct smc_centronics {
ushort scent_rbase;
ushort scent_tbase;
u_char scent_cfcr;
u_char scent_smask;
ushort scent_mrblr;
uint scent_rstate;
uint scent_r_ptr;
ushort scent_rbptr;
ushort scent_r_cnt;
uint scent_rtemp;
uint scent_tstate;
uint scent_t_ptr;
ushort scent_tbptr;
ushort scent_t_cnt;
uint scent_ttemp;
ushort scent_max_sl;
ushort scent_sl_cnt;
ushort scent_character1;
ushort scent_character2;
ushort scent_character3;
ushort scent_character4;
ushort scent_character5;
ushort scent_character6;
ushort scent_character7;
ushort scent_character8;
ushort scent_rccm;
ushort scent_rccr;
} smc_cent_t;
/* Centronics Status Mask Register.
*/
#define SMC_CENT_F ((u_char)0x08)
#define SMC_CENT_PE ((u_char)0x04)
#define SMC_CENT_S ((u_char)0x02)
/* SMC Event and Mask register.
*/
#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
#define SMCM_BSY ((unsigned char)0x04)
#define SMCM_TX ((unsigned char)0x02)
#define SMCM_RX ((unsigned char)0x01)
/* Baud rate generators.
*/
#define CPM_BRG_RST ((uint)0x00020000)
#define CPM_BRG_EN ((uint)0x00010000)
#define CPM_BRG_EXTC_INT ((uint)0x00000000)
#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
#define CPM_BRG_ATB ((uint)0x00002000)
#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
#define CPM_BRG_DIV16 ((uint)0x00000001)
/* SI Clock Route Register
*/
#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
/* SCCs.
*/
#define SCC_GSMRH_IRP ((uint)0x00040000)
#define SCC_GSMRH_GDE ((uint)0x00010000)
#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
#define SCC_GSMRH_REVD ((uint)0x00002000)
#define SCC_GSMRH_TRX ((uint)0x00001000)
#define SCC_GSMRH_TTX ((uint)0x00000800)
#define SCC_GSMRH_CDP ((uint)0x00000400)
#define SCC_GSMRH_CTSP ((uint)0x00000200)
#define SCC_GSMRH_CDS ((uint)0x00000100)
#define SCC_GSMRH_CTSS ((uint)0x00000080)
#define SCC_GSMRH_TFL ((uint)0x00000040)
#define SCC_GSMRH_RFW ((uint)0x00000020)
#define SCC_GSMRH_TXSY ((uint)0x00000010)
#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
#define SCC_GSMRH_RTSM ((uint)0x00000002)
#define SCC_GSMRH_RSYN ((uint)0x00000001)
#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
#define SCC_GSMRL_TCI ((uint)0x10000000)
#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
#define SCC_GSMRL_RINV ((uint)0x02000000)
#define SCC_GSMRL_TINV ((uint)0x01000000)
#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
#define SCC_GSMRL_TEND ((uint)0x00040000)
#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
#define SCC_GSMRL_ENR ((uint)0x00000020)
#define SCC_GSMRL_ENT ((uint)0x00000010)
#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
#define SCC_TODR_TOD ((ushort)0x8000)
/* SCC Event and Mask register.
*/
#define SCCM_TXE ((unsigned char)0x10)
#define SCCM_BSY ((unsigned char)0x04)
#define SCCM_TX ((unsigned char)0x02)
#define SCCM_RX ((unsigned char)0x01)
typedef struct scc_param {
ushort scc_rbase; /* Rx Buffer descriptor base address */
ushort scc_tbase; /* Tx Buffer descriptor base address */
u_char scc_rfcr; /* Rx function code */
u_char scc_tfcr; /* Tx function code */
ushort scc_mrblr; /* Max receive buffer length */
uint scc_rstate; /* Internal */
uint scc_idp; /* Internal */
ushort scc_rbptr; /* Internal */
ushort scc_ibc; /* Internal */
uint scc_rxtmp; /* Internal */
uint scc_tstate; /* Internal */
uint scc_tdp; /* Internal */
ushort scc_tbptr; /* Internal */
ushort scc_tbc; /* Internal */
uint scc_txtmp; /* Internal */
uint scc_rcrc; /* Internal */
uint scc_tcrc; /* Internal */
} sccp_t;
/* Function code bits.
*/
#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
/* CPM Ethernet through SCCx.
*/
typedef struct scc_enet {
sccp_t sen_genscc;
uint sen_cpres; /* Preset CRC */
uint sen_cmask; /* Constant mask for CRC */
uint sen_crcec; /* CRC Error counter */
uint sen_alec; /* alignment error counter */
uint sen_disfc; /* discard frame counter */
ushort sen_pads; /* Tx short frame pad character */
ushort sen_retlim; /* Retry limit threshold */
ushort sen_retcnt; /* Retry limit counter */
ushort sen_maxflr; /* maximum frame length register */
ushort sen_minflr; /* minimum frame length register */
ushort sen_maxd1; /* maximum DMA1 length */
ushort sen_maxd2; /* maximum DMA2 length */
ushort sen_maxd; /* Rx max DMA */
ushort sen_dmacnt; /* Rx DMA counter */
ushort sen_maxb; /* Max BD byte count */
ushort sen_gaddr1; /* Group address filter */
ushort sen_gaddr2;
ushort sen_gaddr3;
ushort sen_gaddr4;
uint sen_tbuf0data0; /* Save area 0 - current frame */
uint sen_tbuf0data1; /* Save area 1 - current frame */
uint sen_tbuf0rba; /* Internal */
uint sen_tbuf0crc; /* Internal */
ushort sen_tbuf0bcnt; /* Internal */
ushort sen_paddrh; /* physical address (MSB) */
ushort sen_paddrm;
ushort sen_paddrl; /* physical address (LSB) */
ushort sen_pper; /* persistence */
ushort sen_rfbdptr; /* Rx first BD pointer */
ushort sen_tfbdptr; /* Tx first BD pointer */
ushort sen_tlbdptr; /* Tx last BD pointer */
uint sen_tbuf1data0; /* Save area 0 - current frame */
uint sen_tbuf1data1; /* Save area 1 - current frame */
uint sen_tbuf1rba; /* Internal */
uint sen_tbuf1crc; /* Internal */
ushort sen_tbuf1bcnt; /* Internal */
ushort sen_txlen; /* Tx Frame length counter */
ushort sen_iaddr1; /* Individual address filter */
ushort sen_iaddr2;
ushort sen_iaddr3;
ushort sen_iaddr4;
ushort sen_boffcnt; /* Backoff counter */
/* NOTE: Some versions of the manual have the following items
* incorrectly documented. Below is the proper order.
*/
ushort sen_taddrh; /* temp address (MSB) */
ushort sen_taddrm;
ushort sen_taddrl; /* temp address (LSB) */
} scc_enet_t;
/* SCC Event register as used by Ethernet.
*/
#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
/* SCC Mode Register (PMSR) as used by Ethernet.
*/
#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
/* Buffer descriptor control/status used by Ethernet receive.
*/
#define BD_ENET_RX_EMPTY ((ushort)0x8000)
#define BD_ENET_RX_WRAP ((ushort)0x2000)
#define BD_ENET_RX_INTR ((ushort)0x1000)
#define BD_ENET_RX_LAST ((ushort)0x0800)
#define BD_ENET_RX_FIRST ((ushort)0x0400)
#define BD_ENET_RX_MISS ((ushort)0x0100)
#define BD_ENET_RX_LG ((ushort)0x0020)
#define BD_ENET_RX_NO ((ushort)0x0010)
#define BD_ENET_RX_SH ((ushort)0x0008)
#define BD_ENET_RX_CR ((ushort)0x0004)
#define BD_ENET_RX_OV ((ushort)0x0002)
#define BD_ENET_RX_CL ((ushort)0x0001)
#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */
#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */
#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
/* Buffer descriptor control/status used by Ethernet transmit.
*/
#define BD_ENET_TX_READY ((ushort)0x8000)
#define BD_ENET_TX_PAD ((ushort)0x4000)
#define BD_ENET_TX_WRAP ((ushort)0x2000)
#define BD_ENET_TX_INTR ((ushort)0x1000)
#define BD_ENET_TX_LAST ((ushort)0x0800)
#define BD_ENET_TX_TC ((ushort)0x0400)
#define BD_ENET_TX_DEF ((ushort)0x0200)
#define BD_ENET_TX_HB ((ushort)0x0100)
#define BD_ENET_TX_LC ((ushort)0x0080)
#define BD_ENET_TX_RL ((ushort)0x0040)
#define BD_ENET_TX_RCMASK ((ushort)0x003c)
#define BD_ENET_TX_UN ((ushort)0x0002)
#define BD_ENET_TX_CSL ((ushort)0x0001)
#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
/* SCC as UART
*/
typedef struct scc_uart {
sccp_t scc_genscc;
char res1[8]; /* Reserved */
ushort scc_maxidl; /* Maximum idle chars */
ushort scc_idlc; /* temp idle counter */
ushort scc_brkcr; /* Break count register */
ushort scc_parec; /* receive parity error counter */
ushort scc_frmec; /* receive framing error counter */
ushort scc_nosec; /* receive noise counter */
ushort scc_brkec; /* receive break condition counter */
ushort scc_brkln; /* last received break length */
ushort scc_uaddr1; /* UART address character 1 */
ushort scc_uaddr2; /* UART address character 2 */
ushort scc_rtemp; /* Temp storage */
ushort scc_toseq; /* Transmit out of sequence char */
ushort scc_char1; /* control character 1 */
ushort scc_char2; /* control character 2 */
ushort scc_char3; /* control character 3 */
ushort scc_char4; /* control character 4 */
ushort scc_char5; /* control character 5 */
ushort scc_char6; /* control character 6 */
ushort scc_char7; /* control character 7 */
ushort scc_char8; /* control character 8 */
ushort scc_rccm; /* receive control character mask */
ushort scc_rccr; /* receive control character register */
ushort scc_rlbc; /* receive last break character */
} scc_uart_t;
/* SCC Event and Mask registers when it is used as a UART.
*/
#define UART_SCCM_GLR ((ushort)0x1000)
#define UART_SCCM_GLT ((ushort)0x0800)
#define UART_SCCM_AB ((ushort)0x0200)
#define UART_SCCM_IDL ((ushort)0x0100)
#define UART_SCCM_GRA ((ushort)0x0080)
#define UART_SCCM_BRKE ((ushort)0x0040)
#define UART_SCCM_BRKS ((ushort)0x0020)
#define UART_SCCM_CCR ((ushort)0x0008)
#define UART_SCCM_BSY ((ushort)0x0004)
#define UART_SCCM_TX ((ushort)0x0002)
#define UART_SCCM_RX ((ushort)0x0001)
/* The SCC PMSR when used as a UART.
*/
#define SCU_PSMR_FLC ((ushort)0x8000)
#define SCU_PSMR_SL ((ushort)0x4000)
#define SCU_PSMR_CL ((ushort)0x3000)
#define SCU_PSMR_UM ((ushort)0x0c00)
#define SCU_PSMR_FRZ ((ushort)0x0200)
#define SCU_PSMR_RZS ((ushort)0x0100)
#define SCU_PSMR_SYN ((ushort)0x0080)
#define SCU_PSMR_DRT ((ushort)0x0040)
#define SCU_PSMR_PEN ((ushort)0x0010)
#define SCU_PSMR_RPM ((ushort)0x000c)
#define SCU_PSMR_REVP ((ushort)0x0008)
#define SCU_PSMR_TPM ((ushort)0x0003)
#define SCU_PSMR_TEVP ((ushort)0x0002)
/* CPM Transparent mode SCC.
*/
typedef struct scc_trans {
sccp_t st_genscc;
uint st_cpres; /* Preset CRC */
uint st_cmask; /* Constant mask for CRC */
} scc_trans_t;
#define BD_SCC_TX_LAST ((ushort)0x0800)
/* IIC parameter RAM.
*/
typedef struct iic {
ushort iic_rbase; /* Rx Buffer descriptor base address */
ushort iic_tbase; /* Tx Buffer descriptor base address */
u_char iic_rfcr; /* Rx function code */
u_char iic_tfcr; /* Tx function code */
ushort iic_mrblr; /* Max receive buffer length */
uint iic_rstate; /* Internal */
uint iic_rdp; /* Internal */
ushort iic_rbptr; /* Internal */
ushort iic_rbc; /* Internal */
uint iic_rxtmp; /* Internal */
uint iic_tstate; /* Internal */
uint iic_tdp; /* Internal */
ushort iic_tbptr; /* Internal */
ushort iic_tbc; /* Internal */
uint iic_txtmp; /* Internal */
char res1[4]; /* Reserved */
ushort iic_rpbase; /* Relocation pointer */
char res2[2]; /* Reserved */
} iic_t;
#define BD_IIC_START ((ushort)0x0400)
/* SPI parameter RAM.
*/
typedef struct spi {
ushort spi_rbase; /* Rx Buffer descriptor base address */
ushort spi_tbase; /* Tx Buffer descriptor base address */
u_char spi_rfcr; /* Rx function code */
u_char spi_tfcr; /* Tx function code */
ushort spi_mrblr; /* Max receive buffer length */
uint spi_rstate; /* Internal */
uint spi_rdp; /* Internal */
ushort spi_rbptr; /* Internal */
ushort spi_rbc; /* Internal */
uint spi_rxtmp; /* Internal */
uint spi_tstate; /* Internal */
uint spi_tdp; /* Internal */
ushort spi_tbptr; /* Internal */
ushort spi_tbc; /* Internal */
uint spi_txtmp; /* Internal */
uint spi_res;
ushort spi_rpbase; /* Relocation pointer */
ushort spi_res2;
} spi_t;
/* SPI Mode register.
*/
#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
#define SPMODE_EN ((ushort)0x0100) /* Enable */
#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */
#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */
#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */
#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
/* SPIE fields */
#define SPIE_MME 0x20
#define SPIE_TXE 0x10
#define SPIE_BSY 0x04
#define SPIE_TXB 0x02
#define SPIE_RXB 0x01
/*
* RISC Controller Configuration Register definitons
*/
#define RCCR_TIME 0x8000 /* RISC Timer Enable */
#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
/* RISC Timer Parameter RAM offset */
#define PROFF_RTMR ((uint)0x01B0)
typedef struct risc_timer_pram {
unsigned short tm_base; /* RISC Timer Table Base Address */
unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */
unsigned short r_tmr; /* RISC Timer Mode Register */
unsigned short r_tmv; /* RISC Timer Valid Register */
unsigned long tm_cmd; /* RISC Timer Command Register */
unsigned long tm_cnt; /* RISC Timer Internal Count */
} rt_pram_t;
/* Bits in RISC Timer Command Register */
#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
/* CPM interrupts. There are nearly 32 interrupts generated by CPM
* channels or devices. All of these are presented to the PPC core
* as a single interrupt. The CPM interrupt handler dispatches its
* own handlers, in a similar fashion to the PPC core handler. We
* use the table as defined in the manuals (i.e. no special high
* priority and SCC1 == SCCa, etc...).
*/
#define CPMVEC_NR 32
#define CPMVEC_PIO_PC15 ((ushort)0x1f)
#define CPMVEC_SCC1 ((ushort)0x1e)
#define CPMVEC_SCC2 ((ushort)0x1d)
#define CPMVEC_SCC3 ((ushort)0x1c)
#define CPMVEC_SCC4 ((ushort)0x1b)
#define CPMVEC_PIO_PC14 ((ushort)0x1a)
#define CPMVEC_TIMER1 ((ushort)0x19)
#define CPMVEC_PIO_PC13 ((ushort)0x18)
#define CPMVEC_PIO_PC12 ((ushort)0x17)
#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
#define CPMVEC_IDMA1 ((ushort)0x15)
#define CPMVEC_IDMA2 ((ushort)0x14)
#define CPMVEC_TIMER2 ((ushort)0x12)
#define CPMVEC_RISCTIMER ((ushort)0x11)
#define CPMVEC_I2C ((ushort)0x10)
#define CPMVEC_PIO_PC11 ((ushort)0x0f)
#define CPMVEC_PIO_PC10 ((ushort)0x0e)
#define CPMVEC_TIMER3 ((ushort)0x0c)
#define CPMVEC_PIO_PC9 ((ushort)0x0b)
#define CPMVEC_PIO_PC8 ((ushort)0x0a)
#define CPMVEC_PIO_PC7 ((ushort)0x09)
#define CPMVEC_TIMER4 ((ushort)0x07)
#define CPMVEC_PIO_PC6 ((ushort)0x06)
#define CPMVEC_SPI ((ushort)0x05)
#define CPMVEC_SMC1 ((ushort)0x04)
#define CPMVEC_SMC2 ((ushort)0x03)
#define CPMVEC_PIO_PC5 ((ushort)0x02)
#define CPMVEC_PIO_PC4 ((ushort)0x01)
#define CPMVEC_ERROR ((ushort)0x00)
/* CPM interrupt configuration vector.
*/
#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
#define CICR_IEN ((uint)0x00000080) /* Int. enable */
#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
extern void cpm_install_handler(int vec,
void (*handler)(void *, struct pt_regs *regs), void *dev_id);
extern void cpm_free_handler(int vec);
#endif /* __CPM_8XX__ */

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/*
* include/asm-ppc/cputable.h
*
* Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef __ASM_PPC_CPUTABLE_H
#define __ASM_PPC_CPUTABLE_H
/* Exposed to userland CPU features */
#define PPC_FEATURE_32 0x80000000
#define PPC_FEATURE_64 0x40000000
#define PPC_FEATURE_601_INSTR 0x20000000
#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
#define PPC_FEATURE_HAS_FPU 0x08000000
#define PPC_FEATURE_HAS_MMU 0x04000000
#define PPC_FEATURE_HAS_4xxMAC 0x02000000
#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
#define PPC_FEATURE_HAS_SPE 0x00800000
#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
/* This structure can grow, it's real size is used by head.S code
* via the mkdefs mecanism.
*/
struct cpu_spec;
typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
struct cpu_spec {
/* CPU is matched via (PVR & pvr_mask) == pvr_value */
unsigned int pvr_mask;
unsigned int pvr_value;
char *cpu_name;
unsigned int cpu_features; /* Kernel features */
unsigned int cpu_user_features; /* Userland features */
/* cache line sizes */
unsigned int icache_bsize;
unsigned int dcache_bsize;
/* number of performance monitor counters */
unsigned int num_pmcs;
/* this is called to initialize various CPU bits like L1 cache,
* BHT, SPD, etc... from head.S before branching to identify_machine
*/
cpu_setup_t cpu_setup;
};
extern struct cpu_spec cpu_specs[];
extern struct cpu_spec *cur_cpu_spec[];
#endif /* __ASSEMBLY__ */
/* CPU kernel features */
#define CPU_FTR_SPLIT_ID_CACHE 0x00000001
#define CPU_FTR_L2CR 0x00000002
#define CPU_FTR_SPEC7450 0x00000004
#define CPU_FTR_ALTIVEC 0x00000008
#define CPU_FTR_TAU 0x00000010
#define CPU_FTR_CAN_DOZE 0x00000020
#define CPU_FTR_USE_TB 0x00000040
#define CPU_FTR_604_PERF_MON 0x00000080
#define CPU_FTR_601 0x00000100
#define CPU_FTR_HPTE_TABLE 0x00000200
#define CPU_FTR_CAN_NAP 0x00000400
#define CPU_FTR_L3CR 0x00000800
#define CPU_FTR_L3_DISABLE_NAP 0x00001000
#define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000
#define CPU_FTR_DUAL_PLL_750FX 0x00004000
#define CPU_FTR_NO_DPM 0x00008000
#define CPU_FTR_HAS_HIGH_BATS 0x00010000
#define CPU_FTR_NEED_COHERENT 0x00020000
#define CPU_FTR_NO_BTIC 0x00040000
#ifdef __ASSEMBLY__
#define BEGIN_FTR_SECTION 98:
#define END_FTR_SECTION(msk, val) \
99: \
.section __ftr_fixup,"a"; \
.align 2; \
.long msk; \
.long val; \
.long 98b; \
.long 99b; \
.previous
#else
#define BEGIN_FTR_SECTION "98:\n"
#define END_FTR_SECTION(msk, val) \
"99:\n" \
" .section __ftr_fixup,\"a\";\n" \
" .align 2;\n" \
" .long "#msk";\n" \
" .long "#val";\n" \
" .long 98b;\n" \
" .long 99b;\n" \
" .previous\n"
#endif /* __ASSEMBLY__ */
#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
#endif /* __ASM_PPC_CPUTABLE_H */
#endif /* __KERNEL__ */

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#ifdef __KERNEL__
#ifndef _PPC_CURRENT_H
#define _PPC_CURRENT_H
/*
* We keep `current' in r2 for speed.
*/
register struct task_struct *current asm ("r2");
#endif /* !(_PPC_CURRENT_H) */
#endif /* __KERNEL__ */

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/*
* Definitions for using the Apple Descriptor-Based DMA controller
* in Power Macintosh computers.
*
* Copyright (C) 1996 Paul Mackerras.
*/
#ifdef __KERNEL__
#ifndef _ASM_DBDMA_H_
#define _ASM_DBDMA_H_
/*
* DBDMA control/status registers. All little-endian.
*/
struct dbdma_regs {
unsigned int control; /* lets you change bits in status */
unsigned int status; /* DMA and device status bits (see below) */
unsigned int cmdptr_hi; /* upper 32 bits of command address */
unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */
unsigned int intr_sel; /* select interrupt condition bit */
unsigned int br_sel; /* select branch condition bit */
unsigned int wait_sel; /* select wait condition bit */
unsigned int xfer_mode;
unsigned int data2ptr_hi;
unsigned int data2ptr;
unsigned int res1;
unsigned int address_hi;
unsigned int br_addr_hi;
unsigned int res2[3];
};
/* Bits in control and status registers */
#define RUN 0x8000
#define PAUSE 0x4000
#define FLUSH 0x2000
#define WAKE 0x1000
#define DEAD 0x0800
#define ACTIVE 0x0400
#define BT 0x0100
#define DEVSTAT 0x00ff
/*
* DBDMA command structure. These fields are all little-endian!
*/
struct dbdma_cmd {
unsigned short req_count; /* requested byte transfer count */
unsigned short command; /* command word (has bit-fields) */
unsigned int phy_addr; /* physical data address */
unsigned int cmd_dep; /* command-dependent field */
unsigned short res_count; /* residual count after completion */
unsigned short xfer_status; /* transfer status */
};
/* DBDMA command values in command field */
#define OUTPUT_MORE 0 /* transfer memory data to stream */
#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
#define INPUT_MORE 0x2000 /* transfer stream data to memory */
#define INPUT_LAST 0x3000 /* ditto, expect end marker */
#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
#define DBDMA_NOP 0x6000 /* do nothing */
#define DBDMA_STOP 0x7000 /* suspend processing */
/* Key values in command field */
#define KEY_STREAM0 0 /* usual data stream */
#define KEY_STREAM1 0x100 /* control/status stream */
#define KEY_STREAM2 0x200 /* device-dependent stream */
#define KEY_STREAM3 0x300 /* device-dependent stream */
#define KEY_REGS 0x500 /* device register space */
#define KEY_SYSTEM 0x600 /* system memory-mapped space */
#define KEY_DEVICE 0x700 /* device memory-mapped space */
/* Interrupt control values in command field */
#define INTR_NEVER 0 /* don't interrupt */
#define INTR_IFSET 0x10 /* intr if condition bit is 1 */
#define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
#define INTR_ALWAYS 0x30 /* always interrupt */
/* Branch control values in command field */
#define BR_NEVER 0 /* don't branch */
#define BR_IFSET 0x4 /* branch if condition bit is 1 */
#define BR_IFCLR 0x8 /* branch if condition bit is 0 */
#define BR_ALWAYS 0xc /* always branch */
/* Wait control values in command field */
#define WAIT_NEVER 0 /* don't wait */
#define WAIT_IFSET 1 /* wait if condition bit is 1 */
#define WAIT_IFCLR 2 /* wait if condition bit is 0 */
#define WAIT_ALWAYS 3 /* always wait */
/* Align an address for a DBDMA command structure */
#define DBDMA_ALIGN(x) (((unsigned)(x) + sizeof(struct dbdma_cmd) - 1) \
& -sizeof(struct dbdma_cmd))
/* Useful macros */
#define DBDMA_DO_STOP(regs) do { \
out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
; \
} while(0)
#endif /* _ASM_DBDMA_H_ */
#endif /* __KERNEL__ */

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#ifdef __KERNEL__
#ifndef _PPC_DELAY_H
#define _PPC_DELAY_H
#include <asm/param.h>
/*
* Copyright 1996, Paul Mackerras.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
extern unsigned long loops_per_jiffy;
extern void __delay(unsigned int loops);
/*
* Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so
* loops = (4294 * usecs * loops_per_jiffy * HZ) / 2^32.
*
* The mulhwu instruction gives us loops = (a * b) / 2^32.
* We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226
* because this lets us support a wide range of HZ and
* loops_per_jiffy values without either a or b overflowing 2^32.
* Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and
* loops_per_jiffy <= (2^32 - 1) / 226 = 19004280
* (which corresponds to ~3800 bogomips at HZ = 100).
* -- paulus
*/
#define __MAX_UDELAY (226050910UL/HZ) /* maximum udelay argument */
#define __MAX_NDELAY (4294967295UL/HZ) /* maximum ndelay argument */
extern __inline__ void __udelay(unsigned int x)
{
unsigned int loops;
__asm__("mulhwu %0,%1,%2" : "=r" (loops) :
"r" (x), "r" (loops_per_jiffy * 226));
__delay(loops);
}
extern __inline__ void __ndelay(unsigned int x)
{
unsigned int loops;
__asm__("mulhwu %0,%1,%2" : "=r" (loops) :
"r" (x), "r" (loops_per_jiffy * 5));
__delay(loops);
}
extern void __bad_udelay(void); /* deliberately undefined */
extern void __bad_ndelay(void); /* deliberately undefined */
#define udelay(n) (__builtin_constant_p(n)? \
((n) > __MAX_UDELAY? __bad_udelay(): __udelay((n) * (19 * HZ))) : \
__udelay((n) * (19 * HZ)))
#define ndelay(n) (__builtin_constant_p(n)? \
((n) > __MAX_NDELAY? __bad_ndelay(): __ndelay((n) * HZ)) : \
__ndelay((n) * HZ))
#endif /* defined(_PPC_DELAY_H) */
#endif /* __KERNEL__ */

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#include <asm-generic/div64.h>

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/*
* This is based on both include/asm-sh/dma-mapping.h and
* include/asm-ppc/pci.h
*/
#ifndef __ASM_PPC_DMA_MAPPING_H
#define __ASM_PPC_DMA_MAPPING_H
#include <linux/config.h>
/* need struct page definitions */
#include <linux/mm.h>
#include <asm/scatterlist.h>
#include <asm/io.h>
#ifdef CONFIG_NOT_COHERENT_CACHE
/*
* DMA-consistent mapping functions for PowerPCs that don't support
* cache snooping. These allocate/free a region of uncached mapped
* memory space for use with DMA devices. Alternatively, you could
* allocate the space "normally" and use the cache management functions
* to ensure it is consistent.
*/
extern void *__dma_alloc_coherent(size_t size, dma_addr_t *handle, int gfp);
extern void __dma_free_coherent(size_t size, void *vaddr);
extern void __dma_sync(void *vaddr, size_t size, int direction);
extern void __dma_sync_page(struct page *page, unsigned long offset,
size_t size, int direction);
#define dma_cache_inv(_start,_size) \
invalidate_dcache_range(_start, (_start + _size))
#define dma_cache_wback(_start,_size) \
clean_dcache_range(_start, (_start + _size))
#define dma_cache_wback_inv(_start,_size) \
flush_dcache_range(_start, (_start + _size))
#else /* ! CONFIG_NOT_COHERENT_CACHE */
/*
* Cache coherent cores.
*/
#define dma_cache_inv(_start,_size) do { } while (0)
#define dma_cache_wback(_start,_size) do { } while (0)
#define dma_cache_wback_inv(_start,_size) do { } while (0)
#define __dma_alloc_coherent(gfp, size, handle) NULL
#define __dma_free_coherent(size, addr) do { } while (0)
#define __dma_sync(addr, size, rw) do { } while (0)
#define __dma_sync_page(pg, off, sz, rw) do { } while (0)
#endif /* ! CONFIG_NOT_COHERENT_CACHE */
#define dma_supported(dev, mask) (1)
static inline int dma_set_mask(struct device *dev, u64 dma_mask)
{
if (!dev->dma_mask || !dma_supported(dev, mask))
return -EIO;
*dev->dma_mask = dma_mask;
return 0;
}
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t * dma_handle, int gfp)
{
#ifdef CONFIG_NOT_COHERENT_CACHE
return __dma_alloc_coherent(size, dma_handle, gfp);
#else
void *ret;
/* ignore region specifiers */
gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
if (dev == NULL || dev->coherent_dma_mask < 0xffffffff)
gfp |= GFP_DMA;
ret = (void *)__get_free_pages(gfp, get_order(size));
if (ret != NULL) {
memset(ret, 0, size);
*dma_handle = virt_to_bus(ret);
}
return ret;
#endif
}
static inline void
dma_free_coherent(struct device *dev, size_t size, void *vaddr,
dma_addr_t dma_handle)
{
#ifdef CONFIG_NOT_COHERENT_CACHE
__dma_free_coherent(size, vaddr);
#else
free_pages((unsigned long)vaddr, get_order(size));
#endif
}
static inline dma_addr_t
dma_map_single(struct device *dev, void *ptr, size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
__dma_sync(ptr, size, direction);
return virt_to_bus(ptr);
}
/* We do nothing. */
#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
static inline dma_addr_t
dma_map_page(struct device *dev, struct page *page,
unsigned long offset, size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
__dma_sync_page(page, offset, size, direction);
return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset;
}
/* We do nothing. */
#define dma_unmap_page(dev, handle, size, dir) do { } while (0)
static inline int
dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
enum dma_data_direction direction)
{
int i;
BUG_ON(direction == DMA_NONE);
for (i = 0; i < nents; i++, sg++) {
BUG_ON(!sg->page);
__dma_sync_page(sg->page, sg->offset, sg->length, direction);
sg->dma_address = page_to_bus(sg->page) + sg->offset;
}
return nents;
}
/* We don't do anything here. */
#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
static inline void
dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
__dma_sync(bus_to_virt(dma_handle), size, direction);
}
static inline void
dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
size_t size,
enum dma_data_direction direction)
{
BUG_ON(direction == DMA_NONE);
__dma_sync(bus_to_virt(dma_handle), size, direction);
}
static inline void
dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents,
enum dma_data_direction direction)
{
int i;
BUG_ON(direction == DMA_NONE);
for (i = 0; i < nents; i++, sg++)
__dma_sync_page(sg->page, sg->offset, sg->length, direction);
}
static inline void
dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents,
enum dma_data_direction direction)
{
int i;
BUG_ON(direction == DMA_NONE);
for (i = 0; i < nents; i++, sg++)
__dma_sync_page(sg->page, sg->offset, sg->length, direction);
}
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
#ifdef CONFIG_NOT_COHERENT_CACHE
#define dma_is_consistent(d) (0)
#else
#define dma_is_consistent(d) (1)
#endif
static inline int dma_get_cache_alignment(void)
{
/*
* Each processor family will define its own L1_CACHE_SHIFT,
* L1_CACHE_BYTES wraps to this, so this is always safe.
*/
return L1_CACHE_BYTES;
}
static inline void
dma_sync_single_range_for_cpu(struct device *dev, dma_addr_t dma_handle,
unsigned long offset, size_t size,
enum dma_data_direction direction)
{
/* just sync everything for now */
dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
}
static inline void
dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
unsigned long offset, size_t size,
enum dma_data_direction direction)
{
/* just sync everything for now */
dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
}
static inline void dma_cache_sync(void *vaddr, size_t size,
enum dma_data_direction direction)
{
__dma_sync(vaddr, size, (int)direction);
}
static inline int dma_mapping_error(dma_addr_t dma_addr)
{
return 0;
}
#endif /* __ASM_PPC_DMA_MAPPING_H */

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/*
* include/asm-ppc/dma.h: Defines for using and allocating dma channels.
* Written by Hennus Bergman, 1992.
* High DMA channel support & info by Hannu Savolainen
* and John Boyd, Nov. 1992.
* Changes for ppc sound by Christoph Nadig
*/
#ifdef __KERNEL__
#include <linux/config.h>
#include <asm/io.h>
#include <linux/spinlock.h>
#include <asm/system.h>
/*
* Note: Adapted for PowerPC by Gary Thomas
* Modified by Cort Dougan <cort@cs.nmt.edu>
*
* None of this really applies for Power Macintoshes. There is
* basically just enough here to get kernel/dma.c to compile.
*
* There may be some comments or restrictions made here which are
* not valid for the PReP platform. Take what you read
* with a grain of salt.
*/
#ifndef _ASM_DMA_H
#define _ASM_DMA_H
#ifndef MAX_DMA_CHANNELS
#define MAX_DMA_CHANNELS 8
#endif
/* The maximum address that we can perform a DMA transfer to on this platform */
/* Doesn't really apply... */
#define MAX_DMA_ADDRESS 0xFFFFFFFF
/* in arch/ppc/kernel/setup.c -- Cort */
extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
extern unsigned long ISA_DMA_THRESHOLD;
#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
#define dma_outb outb_p
#else
#define dma_outb outb
#endif
#define dma_inb inb
/*
* NOTES about DMA transfers:
*
* controller 1: channels 0-3, byte operations, ports 00-1F
* controller 2: channels 4-7, word operations, ports C0-DF
*
* - ALL registers are 8 bits only, regardless of transfer size
* - channel 4 is not used - cascades 1 into 2.
* - channels 0-3 are byte - addresses/counts are for physical bytes
* - channels 5-7 are word - addresses/counts are for physical words
* - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
* - transfer count loaded to registers is 1 less than actual count
* - controller 2 offsets are all even (2x offsets for controller 1)
* - page registers for 5-7 don't use data bit 0, represent 128K pages
* - page registers for 0-3 use bit 0, represent 64K pages
*
* On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
* On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
* Note that addresses loaded into registers must be _physical_ addresses,
* not logical addresses (which may differ if paging is active).
*
* Address mapping for channels 0-3:
*
* A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* P7 ... P0 A7 ... A0 A7 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Address mapping for channels 5-7:
*
* A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
* | ... | \ \ ... \ \ \ ... \ \
* | ... | \ \ ... \ \ \ ... \ (not used)
* | ... | \ \ ... \ \ \ ... \
* P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
* and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
* the hardware level, so odd-byte transfers aren't possible).
*
* Transfer count (_not # bytes_) is limited to 64K, represented as actual
* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
* and up to 128K bytes may be transferred on channels 5-7 in one operation.
*
*/
/* see prep_setup_arch() for detailed informations */
#if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_PPC_PREP)
extern long ppc_cs4232_dma, ppc_cs4232_dma2;
#define SND_DMA1 ppc_cs4232_dma
#define SND_DMA2 ppc_cs4232_dma2
#else
#define SND_DMA1 -1
#define SND_DMA2 -1
#endif
/* 8237 DMA controllers */
#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
/* DMA controller registers */
#define DMA1_CMD_REG 0x08 /* command register (w) */
#define DMA1_STAT_REG 0x08 /* status register (r) */
#define DMA1_REQ_REG 0x09 /* request register (w) */
#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
#define DMA1_MODE_REG 0x0B /* mode register (w) */
#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
#define DMA2_CMD_REG 0xD0 /* command register (w) */
#define DMA2_STAT_REG 0xD0 /* status register (r) */
#define DMA2_REQ_REG 0xD2 /* request register (w) */
#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
#define DMA2_MODE_REG 0xD6 /* mode register (w) */
#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
#define DMA_ADDR_0 0x00 /* DMA address registers */
#define DMA_ADDR_1 0x02
#define DMA_ADDR_2 0x04
#define DMA_ADDR_3 0x06
#define DMA_ADDR_4 0xC0
#define DMA_ADDR_5 0xC4
#define DMA_ADDR_6 0xC8
#define DMA_ADDR_7 0xCC
#define DMA_CNT_0 0x01 /* DMA count registers */
#define DMA_CNT_1 0x03
#define DMA_CNT_2 0x05
#define DMA_CNT_3 0x07
#define DMA_CNT_4 0xC2
#define DMA_CNT_5 0xC6
#define DMA_CNT_6 0xCA
#define DMA_CNT_7 0xCE
#define DMA_LO_PAGE_0 0x87 /* DMA page registers */
#define DMA_LO_PAGE_1 0x83
#define DMA_LO_PAGE_2 0x81
#define DMA_LO_PAGE_3 0x82
#define DMA_LO_PAGE_5 0x8B
#define DMA_LO_PAGE_6 0x89
#define DMA_LO_PAGE_7 0x8A
#define DMA_HI_PAGE_0 0x487 /* DMA page registers */
#define DMA_HI_PAGE_1 0x483
#define DMA_HI_PAGE_2 0x481
#define DMA_HI_PAGE_3 0x482
#define DMA_HI_PAGE_5 0x48B
#define DMA_HI_PAGE_6 0x489
#define DMA_HI_PAGE_7 0x48A
#define DMA1_EXT_REG 0x40B
#define DMA2_EXT_REG 0x4D6
#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
#define DMA_AUTOINIT 0x10
extern spinlock_t dma_spin_lock;
static __inline__ unsigned long claim_dma_lock(void)
{
unsigned long flags;
spin_lock_irqsave(&dma_spin_lock, flags);
return flags;
}
static __inline__ void release_dma_lock(unsigned long flags)
{
spin_unlock_irqrestore(&dma_spin_lock, flags);
}
/* enable/disable a specific DMA channel */
static __inline__ void enable_dma(unsigned int dmanr)
{
unsigned char ucDmaCmd=0x00;
if (dmanr != 4) {
dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
}
if (dmanr <= 3) {
dma_outb(dmanr, DMA1_MASK_REG);
dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
} else
dma_outb(dmanr & 3, DMA2_MASK_REG);
}
static __inline__ void disable_dma(unsigned int dmanr)
{
if (dmanr <= 3)
dma_outb(dmanr | 4, DMA1_MASK_REG);
else
dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
}
/* Clear the 'DMA Pointer Flip Flop'.
* Write 0 for LSB/MSB, 1 for MSB/LSB access.
* Use this once to initialize the FF to a known state.
* After that, keep track of it. :-)
* --- In order to do that, the DMA routines below should ---
* --- only be used while interrupts are disabled! ---
*/
static __inline__ void clear_dma_ff(unsigned int dmanr)
{
if (dmanr <= 3)
dma_outb(0, DMA1_CLEAR_FF_REG);
else
dma_outb(0, DMA2_CLEAR_FF_REG);
}
/* set mode (above) for a specific DMA channel */
static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
{
if (dmanr <= 3)
dma_outb(mode | dmanr, DMA1_MODE_REG);
else
dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
}
/* Set only the page register bits of the transfer address.
* This is used for successive transfers when we know the contents of
* the lower 16 bits of the DMA current address register, but a 64k boundary
* may have been crossed.
*/
static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
{
switch(dmanr) {
case 0:
dma_outb(pagenr, DMA_LO_PAGE_0);
dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
break;
case 1:
dma_outb(pagenr, DMA_LO_PAGE_1);
dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
break;
case 2:
dma_outb(pagenr, DMA_LO_PAGE_2);
dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
break;
case 3:
dma_outb(pagenr, DMA_LO_PAGE_3);
dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
break;
case 5:
if (SND_DMA1 == 5 || SND_DMA2 == 5)
dma_outb(pagenr, DMA_LO_PAGE_5);
else
dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
break;
case 6:
if (SND_DMA1 == 6 || SND_DMA2 == 6)
dma_outb(pagenr, DMA_LO_PAGE_6);
else
dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
break;
case 7:
if (SND_DMA1 == 7 || SND_DMA2 == 7)
dma_outb(pagenr, DMA_LO_PAGE_7);
else
dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
break;
}
}
/* Set transfer address & page bits for specific DMA channel.
* Assumes dma flipflop is clear.
*/
static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
{
if (dmanr <= 3) {
dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE );
dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
} else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE );
dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) +
IO_DMA2_BASE);
dma_outb((dmanr & 3), DMA2_EXT_REG);
} else {
dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
}
set_dma_page(dmanr, phys >> 16);
}
/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
* a specific DMA channel.
* You must ensure the parameters are valid.
* NOTE: from a manual: "the number of transfers is one more
* than the initial word count"! This is taken into account.
* Assumes dma flip-flop is clear.
* NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
*/
static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
{
count--;
if (dmanr <= 3) {
dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 +
IO_DMA1_BASE);
} else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
dma_outb( count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
dma_outb( (count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 +
IO_DMA2_BASE);
} else {
dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 +
IO_DMA2_BASE);
dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 +
IO_DMA2_BASE);
}
}
/* Get DMA residue count. After a DMA transfer, this
* should return zero. Reading this while a DMA transfer is
* still in progress will return unpredictable results.
* If called before the channel has been used, it may return 1.
* Otherwise, it returns the number of _bytes_ left to transfer.
*
* Assumes DMA flip-flop is clear.
*/
static __inline__ int get_dma_residue(unsigned int dmanr)
{
unsigned int io_port = (dmanr <= 3) ?
((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
: ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
/* using short to get 16-bit wrap around */
unsigned short count;
count = 1 + dma_inb(io_port);
count += dma_inb(io_port) << 8;
return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
? count : (count<<1);
}
/* These are in kernel/dma.c: */
/* reserve a DMA channel */
extern int request_dma(unsigned int dmanr, const char * device_id);
/* release it again */
extern void free_dma(unsigned int dmanr);
#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy (0)
#endif
#endif /* _ASM_DMA_H */
#endif /* __KERNEL__ */

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#ifndef __PPC_ELF_H
#define __PPC_ELF_H
/*
* ELF register definitions..
*/
#include <asm/types.h>
#include <asm/ptrace.h>
#include <asm/cputable.h>
/* PowerPC relocations defined by the ABIs */
#define R_PPC_NONE 0
#define R_PPC_ADDR32 1 /* 32bit absolute address */
#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
#define R_PPC_ADDR16 3 /* 16bit absolute address */
#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
#define R_PPC_ADDR14_BRTAKEN 8
#define R_PPC_ADDR14_BRNTAKEN 9
#define R_PPC_REL24 10 /* PC relative 26 bit */
#define R_PPC_REL14 11 /* PC relative 16 bit */
#define R_PPC_REL14_BRTAKEN 12
#define R_PPC_REL14_BRNTAKEN 13
#define R_PPC_GOT16 14
#define R_PPC_GOT16_LO 15
#define R_PPC_GOT16_HI 16
#define R_PPC_GOT16_HA 17
#define R_PPC_PLTREL24 18
#define R_PPC_COPY 19
#define R_PPC_GLOB_DAT 20
#define R_PPC_JMP_SLOT 21
#define R_PPC_RELATIVE 22
#define R_PPC_LOCAL24PC 23
#define R_PPC_UADDR32 24
#define R_PPC_UADDR16 25
#define R_PPC_REL32 26
#define R_PPC_PLT32 27
#define R_PPC_PLTREL32 28
#define R_PPC_PLT16_LO 29
#define R_PPC_PLT16_HI 30
#define R_PPC_PLT16_HA 31
#define R_PPC_SDAREL16 32
#define R_PPC_SECTOFF 33
#define R_PPC_SECTOFF_LO 34
#define R_PPC_SECTOFF_HI 35
#define R_PPC_SECTOFF_HA 36
/* Keep this the last entry. */
#define R_PPC_NUM 37
#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
#define ELF_NFPREG 33 /* includes fpscr */
#define ELF_NVRREG 33 /* includes vscr */
#define ELF_NEVRREG 34 /* includes acc (as 2) */
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_ARCH EM_PPC
#define ELF_CLASS ELFCLASS32
#define ELF_DATA ELFDATA2MSB
/* General registers */
typedef unsigned long elf_greg_t;
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
/* Floating point registers */
typedef double elf_fpreg_t;
typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
/* Altivec registers */
typedef __vector128 elf_vrreg_t;
typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
#ifdef __KERNEL__
struct task_struct;
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ((x)->e_machine == EM_PPC)
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#define ELF_ET_DYN_BASE (0x08000000)
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
#define ELF_CORE_COPY_REGS(gregs, regs) \
memcpy((gregs), (regs), sizeof(struct pt_regs)); \
memset((char *)(gregs) + sizeof(struct pt_regs), 0, \
sizeof(elf_gregset_t) - sizeof(struct pt_regs));
#define ELF_CORE_COPY_TASK_REGS(t, elfregs) \
((t)->thread.regs? \
({ ELF_CORE_COPY_REGS((elfregs), (t)->thread.regs); 1; }): 0)
extern int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpu);
#define ELF_CORE_COPY_FPREGS(t, fpu) dump_task_fpu((t), (fpu))
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. This could be done in userspace,
but it's not easy, and we've already done it here. */
#define ELF_HWCAP (cur_cpu_spec[0]->cpu_user_features)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo.
For the moment, we have only optimizations for the Intel generations,
but that could change... */
#define ELF_PLATFORM (NULL)
#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
/*
* We need to put in some extra aux table entries to tell glibc what
* the cache block size is, so it can use the dcbz instruction safely.
*/
#define AT_DCACHEBSIZE 19
#define AT_ICACHEBSIZE 20
#define AT_UCACHEBSIZE 21
/* A special ignored type value for PPC, for glibc compatibility. */
#define AT_IGNOREPPC 22
extern int dcache_bsize;
extern int icache_bsize;
extern int ucache_bsize;
/*
* The requirements here are:
* - keep the final alignment of sp (sp & 0xf)
* - make sure the 32-bit value at the first 16 byte aligned position of
* AUXV is greater than 16 for glibc compatibility.
* AT_IGNOREPPC is used for that.
* - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
* even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
*/
#define ARCH_DLINFO \
do { \
/* Handle glibc compatibility. */ \
NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
/* Cache size items */ \
NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
} while (0)
#endif /* __KERNEL__ */
#endif

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#ifndef _PPC_ERRNO_H
#define _PPC_ERRNO_H
#include <asm-generic/errno.h>
#undef EDEADLOCK
#define EDEADLOCK 58 /* File locking deadlock error */
#define _LAST_ERRNO 516
#endif

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#ifndef _PPC_FCNTL_H
#define _PPC_FCNTL_H
/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
located on an ext2 file system */
#define O_ACCMODE 0003
#define O_RDONLY 00
#define O_WRONLY 01
#define O_RDWR 02
#define O_CREAT 0100 /* not fcntl */
#define O_EXCL 0200 /* not fcntl */
#define O_NOCTTY 0400 /* not fcntl */
#define O_TRUNC 01000 /* not fcntl */
#define O_APPEND 02000
#define O_NONBLOCK 04000
#define O_NDELAY O_NONBLOCK
#define O_SYNC 010000
#define FASYNC 020000 /* fcntl, for BSD compatibility */
#define O_DIRECTORY 040000 /* must be a directory */
#define O_NOFOLLOW 0100000 /* don't follow links */
#define O_LARGEFILE 0200000
#define O_DIRECT 0400000 /* direct disk access hint */
#define O_NOATIME 01000000
#define F_DUPFD 0 /* dup */
#define F_GETFD 1 /* get close_on_exec */
#define F_SETFD 2 /* set/clear close_on_exec */
#define F_GETFL 3 /* get file->f_flags */
#define F_SETFL 4 /* set file->f_flags */
#define F_GETLK 5
#define F_SETLK 6
#define F_SETLKW 7
#define F_SETOWN 8 /* for sockets. */
#define F_GETOWN 9 /* for sockets. */
#define F_SETSIG 10 /* for sockets. */
#define F_GETSIG 11 /* for sockets. */
#define F_GETLK64 12 /* using 'struct flock64' */
#define F_SETLK64 13
#define F_SETLKW64 14
/* for F_[GET|SET]FL */
#define FD_CLOEXEC 1 /* actually anything with low bit set goes */
/* for posix fcntl() and lockf() */
#define F_RDLCK 0
#define F_WRLCK 1
#define F_UNLCK 2
/* for old implementation of bsd flock () */
#define F_EXLCK 4 /* or 3 */
#define F_SHLCK 8 /* or 4 */
/* for leases */
#define F_INPROGRESS 16
/* operations for bsd flock(), also used by the kernel implementation */
#define LOCK_SH 1 /* shared lock */
#define LOCK_EX 2 /* exclusive lock */
#define LOCK_NB 4 /* or'd with one of the above to prevent
blocking */
#define LOCK_UN 8 /* remove lock */
#define LOCK_MAND 32 /* This is a mandatory flock */
#define LOCK_READ 64 /* ... Which allows concurrent read operations */
#define LOCK_WRITE 128 /* ... Which allows concurrent write operations */
#define LOCK_RW 192 /* ... Which allows concurrent read & write ops */
#ifdef __KERNEL__
#define F_POSIX 1
#define F_FLOCK 2
#define F_BROKEN 4 /* broken flock() emulation */
#endif /* __KERNEL__ */
struct flock {
short l_type;
short l_whence;
off_t l_start;
off_t l_len;
pid_t l_pid;
};
struct flock64 {
short l_type;
short l_whence;
loff_t l_start;
loff_t l_len;
pid_t l_pid;
};
#define F_LINUX_SPECIFIC_BASE 1024
#endif

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/*
* Architecture specific parts of the Floppy driver
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1995
*/
#ifdef __KERNEL__
#ifndef __ASM_PPC_FLOPPY_H
#define __ASM_PPC_FLOPPY_H
#define fd_inb(port) inb_p(port)
#define fd_outb(value,port) outb_p(value,port)
#define fd_enable_dma() enable_dma(FLOPPY_DMA)
#define fd_disable_dma() disable_dma(FLOPPY_DMA)
#define fd_request_dma() request_dma(FLOPPY_DMA,"floppy")
#define fd_free_dma() free_dma(FLOPPY_DMA)
#define fd_clear_dma_ff() clear_dma_ff(FLOPPY_DMA)
#define fd_set_dma_mode(mode) set_dma_mode(FLOPPY_DMA,mode)
#define fd_set_dma_addr(addr) set_dma_addr(FLOPPY_DMA,(unsigned int)virt_to_bus(addr))
#define fd_set_dma_count(count) set_dma_count(FLOPPY_DMA,count)
#define fd_enable_irq() enable_irq(FLOPPY_IRQ)
#define fd_disable_irq() disable_irq(FLOPPY_IRQ)
#define fd_cacheflush(addr,size) /* nothing */
#define fd_request_irq() request_irq(FLOPPY_IRQ, floppy_interrupt, \
SA_INTERRUPT|SA_SAMPLE_RANDOM, \
"floppy", NULL)
#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL);
__inline__ void virtual_dma_init(void)
{
/* Nothing to do on PowerPC */
}
static int FDC1 = 0x3f0;
static int FDC2 = -1;
/*
* Again, the CMOS information not available
*/
#define FLOPPY0_TYPE 6
#define FLOPPY1_TYPE 0
#define N_FDC 2 /* Don't change this! */
#define N_DRIVE 8
#define FLOPPY_MOTOR_MASK 0xf0
/*
* The PowerPC has no problems with floppy DMA crossing 64k borders.
*/
#define CROSS_64KB(a,s) (0)
#endif /* __ASM_PPC_FLOPPY_H */
#define EXTRA_FLOPPY_PARAMS
#endif /* __KERNEL__ */

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/*
* include/asm-ppc/fsl_ocp.h
*
* Definitions for the on-chip peripherals on Freescale PPC processors
*
* Maintainer: Kumar Gala (kumar.gala@freescale.com)
*
* Copyright 2004 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifdef __KERNEL__
#ifndef __ASM_FS_OCP_H__
#define __ASM_FS_OCP_H__
/* A table of information for supporting the Gianfar Ethernet Controller
* This helps identify which enet controller we are dealing with,
* and what type of enet controller it is
*/
struct ocp_gfar_data {
uint interruptTransmit;
uint interruptError;
uint interruptReceive;
uint interruptPHY;
uint flags;
uint phyid;
uint phyregidx;
unsigned char mac_addr[6];
};
/* Flags in the flags field */
#define GFAR_HAS_COALESCE 0x20
#define GFAR_HAS_RMON 0x10
#define GFAR_HAS_MULTI_INTR 0x08
#define GFAR_FIRM_SET_MACADDR 0x04
#define GFAR_HAS_PHY_INTR 0x02 /* if not set use a timer */
#define GFAR_HAS_GIGABIT 0x01
/* Data structure for I2C support. Just contains a couple flags
* to distinguish various I2C implementations*/
struct ocp_fs_i2c_data {
uint flags;
};
/* Flags for I2C */
#define FS_I2C_SEPARATE_DFSRR 0x02
#define FS_I2C_CLOCK_5200 0x01
#endif /* __ASM_FS_OCP_H__ */
#endif /* __KERNEL__ */

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/*
* include/asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions
*
* Copyright (C) 1997 Geert Uytterhoeven
*
* This file is based on the following documentation:
*
* The VAS96011/12 Chipset, Data Book, Edition 1.0
* VLSI Technology, Inc.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef _ASMPPC_GG2_H
#define _ASMPPC_GG2_H
/*
* Memory Map (CHRP mode)
*/
#define GG2_PCI_MEM_BASE 0xc0000000 /* Peripheral memory space */
#define GG2_ISA_MEM_BASE 0xf7000000 /* Peripheral memory alias */
#define GG2_ISA_IO_BASE 0xf8000000 /* Peripheral I/O space */
#define GG2_PCI_CONFIG_BASE 0xfec00000 /* PCI configuration space */
#define GG2_INT_ACK_SPECIAL 0xfec80000 /* Interrupt acknowledge and */
/* special PCI cycles */
#define GG2_ROM_BASE0 0xff000000 /* ROM bank 0 */
#define GG2_ROM_BASE1 0xff800000 /* ROM bank 1 */
/*
* GG2 specific PCI Registers
*/
extern unsigned long gg2_pci_config_base; /* kernel virtual address */
#define GG2_PCI_BUSNO 0x40 /* Bus number */
#define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */
#define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */
#define GG2_PCI_PPC_CTRL 0x50 /* PowerPC interface control register */
#define GG2_PCI_ADDR_MAP 0x5c /* Address map */
#define GG2_PCI_PCI_CTRL 0x60 /* PCI interface control register */
#define GG2_PCI_ROM_CTRL 0x70 /* ROM interface control register */
#define GG2_PCI_ROM_TIME 0x74 /* ROM timing */
#define GG2_PCI_CC_CTRL 0x80 /* Cache controller control register */
#define GG2_PCI_DRAM_BANK0 0x90 /* Control register for DRAM bank #0 */
#define GG2_PCI_DRAM_BANK1 0x94 /* Control register for DRAM bank #1 */
#define GG2_PCI_DRAM_BANK2 0x98 /* Control register for DRAM bank #2 */
#define GG2_PCI_DRAM_BANK3 0x9c /* Control register for DRAM bank #3 */
#define GG2_PCI_DRAM_BANK4 0xa0 /* Control register for DRAM bank #4 */
#define GG2_PCI_DRAM_BANK5 0xa4 /* Control register for DRAM bank #5 */
#define GG2_PCI_DRAM_TIME0 0xb0 /* Timing parameters set #0 */
#define GG2_PCI_DRAM_TIME1 0xb4 /* Timing parameters set #1 */
#define GG2_PCI_DRAM_CTRL 0xc0 /* DRAM control */
#define GG2_PCI_ERR_CTRL 0xd0 /* Error control register */
#define GG2_PCI_ERR_STATUS 0xd4 /* Error status register */
/* Cleared when read */
#endif /* _ASMPPC_GG2_H */

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/*
* include/asm-ppc/gt64260.h
*
* Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines.
*
* Author: Mark A. Greer <mgreer@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_GT64260_H
#define __ASMPPC_GT64260_H
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/pci.h>
#include <linux/slab.h>
#include <asm/byteorder.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/machdep.h>
#include <asm/pci-bridge.h>
#include <asm/gt64260_defs.h>
extern u32 gt64260_base;
extern u32 gt64260_irq_base; /* We handle the next 96 IRQs from here */
extern u32 gt64260_revision;
extern u8 gt64260_pci_exclude_bridge;
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
/* IRQs defined by the 64260 */
#define GT64260_IRQ_MPSC0 40
#define GT64260_IRQ_MPSC1 42
#define GT64260_IRQ_SDMA 36
/*
* Define a default physical memory map to be set up on the bridge.
* Also define a struct to pass that info from board-specific routines to
* GT64260 generic set up routines. By passing this info in, the board
* support developer can modify it at will.
*/
/*
* This is the default memory map:
* CPU PCI
* --- ---
* PCI 0 I/O: 0xfa000000-0xfaffffff 0x00000000-0x00ffffff
* PCI 1 I/O: 0xfb000000-0xfbffffff 0x01000000-0x01ffffff
* PCI 0 MEM: 0x80000000-0x8fffffff 0x80000000-0x8fffffff
* PCI 1 MEM: 0x90000000-0x9fffffff 0x90000000-0x9fffffff
*/
/* Default physical memory map for the GT64260 bridge */
/*
* PCI Bus 0 Definitions
*/
#define GT64260_PCI_0_IO_SIZE 0x01000000U
#define GT64260_PCI_0_MEM_SIZE 0x10000000U
/* Processor Physical addresses */
#define GT64260_PCI_0_IO_START_PROC 0xfa000000U
#define GT64260_PCI_0_IO_END_PROC (GT64260_PCI_0_IO_START_PROC + \
GT64260_PCI_0_IO_SIZE - 1)
/* PCI 0 addresses */
#define GT64260_PCI_0_IO_START 0x00000000U
#define GT64260_PCI_0_IO_END (GT64260_PCI_0_IO_START + \
GT64260_PCI_0_IO_SIZE - 1)
/* Processor Physical addresses */
#define GT64260_PCI_0_MEM_START_PROC 0x80000000U
#define GT64260_PCI_0_MEM_END_PROC (GT64260_PCI_0_MEM_START_PROC + \
GT64260_PCI_0_MEM_SIZE - 1)
/* PCI 0 addresses */
#define GT64260_PCI_0_MEM_START 0x80000000U
#define GT64260_PCI_0_MEM_END (GT64260_PCI_0_MEM_START + \
GT64260_PCI_0_MEM_SIZE - 1)
/*
* PCI Bus 1 Definitions
*/
#define GT64260_PCI_1_IO_SIZE 0x01000000U
#define GT64260_PCI_1_MEM_SIZE 0x10000000U
/* PCI 1 addresses */
#define GT64260_PCI_1_IO_START 0x01000000U
#define GT64260_PCI_1_IO_END (GT64260_PCI_1_IO_START + \
GT64260_PCI_1_IO_SIZE - 1)
/* Processor Physical addresses */
#define GT64260_PCI_1_IO_START_PROC 0xfb000000U
#define GT64260_PCI_1_IO_END_PROC (GT64260_PCI_1_IO_START_PROC + \
GT64260_PCI_1_IO_SIZE - 1)
/* PCI 1 addresses */
#define GT64260_PCI_1_MEM_START 0x90000000U
#define GT64260_PCI_1_MEM_END (GT64260_PCI_1_MEM_START + \
GT64260_PCI_1_MEM_SIZE - 1)
/* Processor Physical addresses */
#define GT64260_PCI_1_MEM_START_PROC 0x90000000U
#define GT64260_PCI_1_MEM_END_PROC (GT64260_PCI_1_MEM_START_PROC + \
GT64260_PCI_1_MEM_SIZE - 1)
/* Define struct to pass mem-map info into gt64260_common.c code */
typedef struct {
struct pci_controller *hose_a;
struct pci_controller *hose_b;
u32 mem_size;
u32 pci_0_io_start_proc;
u32 pci_0_io_start_pci;
u32 pci_0_io_size;
u32 pci_0_io_swap;
u32 pci_0_mem_start_proc;
u32 pci_0_mem_start_pci_hi;
u32 pci_0_mem_start_pci_lo;
u32 pci_0_mem_size;
u32 pci_0_mem_swap;
u32 pci_1_io_start_proc;
u32 pci_1_io_start_pci;
u32 pci_1_io_size;
u32 pci_1_io_swap;
u32 pci_1_mem_start_proc;
u32 pci_1_mem_start_pci_hi;
u32 pci_1_mem_start_pci_lo;
u32 pci_1_mem_size;
u32 pci_1_mem_swap;
} gt64260_bridge_info_t;
#define GT64260_BRIDGE_INFO_DEFAULT(ip, ms) { \
(ip)->mem_size = (ms); \
\
(ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC; \
(ip)->pci_0_io_start_pci = GT64260_PCI_0_IO_START; \
(ip)->pci_0_io_size = GT64260_PCI_0_IO_SIZE; \
(ip)->pci_0_io_swap = GT64260_CPU_PCI_SWAP_NONE; \
\
(ip)->pci_0_mem_start_proc = GT64260_PCI_0_MEM_START_PROC; \
(ip)->pci_0_mem_start_pci_hi = 0x00000000; \
(ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START; \
(ip)->pci_0_mem_size = GT64260_PCI_0_MEM_SIZE; \
(ip)->pci_0_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \
\
(ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC; \
(ip)->pci_1_io_start_pci = GT64260_PCI_1_IO_START; \
(ip)->pci_1_io_size = GT64260_PCI_1_IO_SIZE; \
(ip)->pci_1_io_swap = GT64260_CPU_PCI_SWAP_NONE; \
\
(ip)->pci_1_mem_start_proc = GT64260_PCI_1_MEM_START_PROC; \
(ip)->pci_1_mem_start_pci_hi = 0x00000000; \
(ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START; \
(ip)->pci_1_mem_size = GT64260_PCI_1_MEM_SIZE; \
(ip)->pci_1_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \
}
/*
*****************************************************************************
*
* I/O macros to access the 64260's registers
*
*****************************************************************************
*/
extern inline uint32_t gt_read(uint32_t offs){
return (in_le32((volatile uint *)(gt64260_base + offs)));
}
extern inline void gt_write(uint32_t offs, uint32_t d){
out_le32((volatile uint *)(gt64260_base + offs), d);
}
#if 0 /* paranoid SMP version */
extern inline void gt_modify(u32 offs, u32 data, u32 mask) \
{
uint32_t reg;
spin_lock(&gt64260_lock);
reg = gt_read(offs) & (~mask); /* zero any bits we care about*/
reg |= data & mask; /* set bits from the data */
gt_write(offs, reg);
spin_unlock(&gt64260_lock);
}
#else
extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask)
{
uint32_t reg;
reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/
reg |= (data) & (mask); /* set bits from the data */
gt_write(offs, reg);
}
#endif
#define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits)
#define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits)
/*
*****************************************************************************
*
* Function Prototypes
*
*****************************************************************************
*/
int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info,
int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char)));
int gt64260_bridge_init(gt64260_bridge_info_t *info);
int gt64260_cpu_scs_set_window(u32 window,
u32 base_addr,
u32 size);
int gt64260_cpu_cs_set_window(u32 window,
u32 base_addr,
u32 size);
int gt64260_cpu_boot_set_window(u32 base_addr,
u32 size);
int gt64260_cpu_set_pci_io_window(u32 pci_bus,
u32 cpu_base_addr,
u32 pci_base_addr,
u32 size,
u32 swap);
int gt64260_cpu_set_pci_mem_window(u32 pci_bus,
u32 window,
u32 cpu_base_addr,
u32 pci_base_addr_hi,
u32 pci_base_addr_lo,
u32 size,
u32 swap_64bit);
int gt64260_cpu_prot_set_window(u32 window,
u32 base_addr,
u32 size,
u32 access_bits);
int gt64260_cpu_snoop_set_window(u32 window,
u32 base_addr,
u32 size,
u32 snoop_type);
void gt64260_cpu_disable_all_windows(void);
int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits);
int gt64260_pci_slave_scs_set_window(struct pci_controller *hose,
u32 window,
u32 pci_base_addr,
u32 cpu_base_addr,
u32 size);
int gt64260_pci_slave_cs_set_window(struct pci_controller *hose,
u32 window,
u32 pci_base_addr,
u32 cpu_base_addr,
u32 size);
int gt64260_pci_slave_boot_set_window(struct pci_controller *hose,
u32 pci_base_addr,
u32 cpu_base_addr,
u32 size);
int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose,
u32 window,
u32 pci_base_addr,
u32 other_bus_base_addr,
u32 size);
int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose,
u32 pci_base_addr,
u32 other_bus_base_addr,
u32 size);
int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose,
u32 window,
u32 pci_base_addr_hi,
u32 pci_base_addr_lo,
u32 cpu_base_addr,
u32 size);
int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose,
u32 window,
u32 pci_base_addr_hi,
u32 pci_base_addr_lo,
u32 cpu_base_addr,
u32 size);
int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose,
u32 pci_base_addr_hi,
u32 pci_base_addr_lo,
u32 cpu_base_addr,
u32 size);
int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose,
u32 window,
u32 pci_base_addr_hi,
u32 pci_base_addr_lo,
u32 other_bus_base_addr,
u32 size);
int gt64260_pci_acc_cntl_set_window(u32 pci_bus,
u32 window,
u32 base_addr_hi,
u32 base_addr_lo,
u32 size,
u32 features);
int gt64260_pci_snoop_set_window(u32 pci_bus,
u32 window,
u32 base_addr_hi,
u32 base_addr_lo,
u32 size,
u32 snoop_type);
int gt64260_set_base(u32 new_base);
int gt64260_get_base(u32 *base);
int gt64260_pci_exclude_device(u8 bus, u8 devfn);
void gt64260_init_irq(void);
int gt64260_get_irq(struct pt_regs *regs);
void gt64260_mpsc_progress(char *s, unsigned short hex);
#endif /* __ASMPPC_GT64260_H */

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#ifdef __KERNEL__
#ifndef __ASM_HARDIRQ_H
#define __ASM_HARDIRQ_H
#include <linux/config.h>
#include <linux/cache.h>
#include <linux/smp_lock.h>
#include <asm/irq.h>
/* The __last_jiffy_stamp field is needed to ensure that no decrementer
* interrupt is lost on SMP machines. Since on most CPUs it is in the same
* cache line as local_irq_count, it is cheap to access and is also used on UP
* for uniformity.
*/
typedef struct {
unsigned long __softirq_pending; /* set_bit is used on this */
unsigned int __last_jiffy_stamp;
} ____cacheline_aligned irq_cpustat_t;
#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
#define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp)
static inline void ack_bad_irq(int irq)
{
printk(KERN_CRIT "illegal vector %d received!\n", irq);
BUG();
}
#endif /* __ASM_HARDIRQ_H */
#endif /* __KERNEL__ */

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/*
* arch/ppc/kernel/harrier.h
*
* Definitions for Motorola MCG Harrier North Bridge & Memory controller
*
* Author: Dale Farnsworth
* dale.farnsworth@mvista.com
*
* Modified by: Randy Vinson
* rvinson@mvista.com
*
* Copyright 2001-2002 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __ASMPPC_HARRIER_H
#define __ASMPPC_HARRIER_H
#include <linux/types.h>
#include <asm/pci-bridge.h>
struct pci_controller;
int harrier_init(struct pci_controller *hose,
uint ppc_reg_base,
ulong processor_pci_mem_start,
ulong processor_pci_mem_end,
ulong processor_pci_io_start,
ulong processor_pci_io_end,
ulong processor_mpic_base);
unsigned long harrier_get_mem_size(uint smc_base);
int harrier_mpic_init(unsigned int pci_mem_offset);
void harrier_setup_nonmonarch(uint ppc_reg_base,
uint in0_size);
void harrier_release_eready(uint ppc_reg_base);
void harrier_wait_eready(uint ppc_reg_base);
#endif /* __ASMPPC_HARRIER_H */

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/*
* include/asm-ppc/hawk.h
*
* Support functions for MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001,2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_HAWK_H
#define __ASMPPC_HAWK_H
#include <asm/pci-bridge.h>
#include <asm/hawk_defs.h>
extern int hawk_init(struct pci_controller *hose,
unsigned int ppc_reg_base, unsigned long processor_pci_mem_start,
unsigned long processor_pci_mem_end,
unsigned long processor_pci_io_start,
unsigned long processor_pci_io_end,
unsigned long processor_mpic_base);
extern unsigned long hawk_get_mem_size(unsigned int smc_base);
extern int hawk_mpic_init(unsigned int pci_mem_offset);
#endif /* __ASMPPC_HAWK_H */

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/*
* include/asm-ppc/hawk_defs.h
*
* Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* Modified by Randy Vinson (rvinson@mvista.com)
*
* 2001-2004 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __ASMPPC_HAWK_DEFS_H
#define __ASMPPC_HAWK_DEFS_H
#include <asm/pci-bridge.h>
/*
* The Falcon/Raven and HAWK have 4 sets of registers:
* 1) PPC Registers which define the mappings from PPC bus to PCI bus,
* etc.
* 2) PCI Registers which define the mappings from PCI bus to PPC bus and the
* MPIC base address.
* 3) MPIC registers
* 4) System Memory Controller (SMC) registers.
*/
#define HAWK_PCI_CONFIG_ADDR_OFF 0x00000cf8
#define HAWK_PCI_CONFIG_DATA_OFF 0x00000cfc
#define HAWK_MPIC_SIZE 0x00040000U
#define HAWK_SMC_SIZE 0x00001000U
/*
* Define PPC register offsets.
*/
#define HAWK_PPC_XSADD0_OFF 0x40
#define HAWK_PPC_XSOFF0_OFF 0x44
#define HAWK_PPC_XSADD1_OFF 0x48
#define HAWK_PPC_XSOFF1_OFF 0x4c
#define HAWK_PPC_XSADD2_OFF 0x50
#define HAWK_PPC_XSOFF2_OFF 0x54
#define HAWK_PPC_XSADD3_OFF 0x58
#define HAWK_PPC_XSOFF3_OFF 0x5c
/*
* Define PCI register offsets.
*/
#define HAWK_PCI_PSADD0_OFF 0x80
#define HAWK_PCI_PSOFF0_OFF 0x84
#define HAWK_PCI_PSADD1_OFF 0x88
#define HAWK_PCI_PSOFF1_OFF 0x8c
#define HAWK_PCI_PSADD2_OFF 0x90
#define HAWK_PCI_PSOFF2_OFF 0x94
#define HAWK_PCI_PSADD3_OFF 0x98
#define HAWK_PCI_PSOFF3_OFF 0x9c
/*
* Define the System Memory Controller (SMC) register offsets.
*/
#define HAWK_SMC_RAM_A_SIZE_REG_OFF 0x10
#define HAWK_SMC_RAM_B_SIZE_REG_OFF 0x11
#define HAWK_SMC_RAM_C_SIZE_REG_OFF 0x12
#define HAWK_SMC_RAM_D_SIZE_REG_OFF 0x13
#define HAWK_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */
#define HAWK_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */
#define HAWK_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */
#define HAWK_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */
#define FALCON_SMC_REG_COUNT 4
#define HAWK_SMC_REG_COUNT 8
#endif /* __ASMPPC_HAWK_DEFS_H */

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#include <asm-generic/hdreg.h>

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/*
* heathrow.h: definitions for using the "Heathrow" I/O controller chip.
*
* Grabbed from Open Firmware definitions on a PowerBook G3 Series
*
* Copyright (C) 1997 Paul Mackerras.
*/
/* Front light color on Yikes/B&W G3. 32 bits */
#define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */
/* Brightness/contrast (gossamer iMac ?). 8 bits */
#define HEATHROW_BRIGHTNESS_CNTL 0x32
#define HEATHROW_CONTRAST_CNTL 0x33
/* offset from ohare base for feature control register */
#define HEATHROW_MBCR 0x34 /* Media bay control */
#define HEATHROW_FCR 0x38 /* Feature control */
#define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */
/*
* Bits in feature control register.
* Bits postfixed with a _N are in inverse logic
*/
#define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */
#define HRW_BAY_POWER_N 0x00000002
#define HRW_BAY_PCI_ENABLE 0x00000004
#define HRW_BAY_IDE_ENABLE 0x00000008
#define HRW_BAY_FLOPPY_ENABLE 0x00000010
#define HRW_IDE0_ENABLE 0x00000020
#define HRW_IDE0_RESET_N 0x00000040
#define HRW_BAY_DEV_MASK 0x0000001c
#define HRW_BAY_RESET_N 0x00000080
#define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */
#define HRW_SCC_ENABLE 0x00000200
#define HRW_MESH_ENABLE 0x00000400
#define HRW_SWIM_ENABLE 0x00000800
#define HRW_SOUND_POWER_N 0x00001000
#define HRW_SOUND_CLK_ENABLE 0x00002000
#define HRW_SCCA_IO 0x00004000
#define HRW_SCCB_IO 0x00008000
#define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */
#define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */
#define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */
#define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */
#define HRW_AUD_RUN22 0x00100000 /* ??? (1) */
#define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */
#define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */
#define HRW_IDE1_RESET_N 0x00800000 /* Media bay */
#define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */
#define HRW_RESET_SCC 0x02000000
#define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */
#define HRW_USE_MFDC 0x08000000 /* ??? (0) */
#define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */
#define HRW_BMAC_RESET 0x80000000 /* not documented in OF */
/* We OR those features at boot on desktop G3s */
#define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
/* Looks like Heathrow has some sort of GPIOs as well... */
#define HRW_GPIO_MODEM_RESET 0x6d

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/*
* highmem.h: virtual kernel memory mappings for high memory
*
* PowerPC version, stolen from the i386 version.
*
* Used in CONFIG_HIGHMEM systems for memory pages which
* are not addressable by direct kernel virtual addresses.
*
* Copyright (C) 1999 Gerhard Wichert, Siemens AG
* Gerhard.Wichert@pdb.siemens.de
*
*
* Redesigned the x86 32-bit VM architecture to deal with
* up to 16 Terrabyte physical memory. With current x86 CPUs
* we now support up to 64 Gigabytes physical RAM.
*
* Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
*/
#ifndef _ASM_HIGHMEM_H
#define _ASM_HIGHMEM_H
#ifdef __KERNEL__
#include <linux/init.h>
#include <linux/interrupt.h>
#include <asm/kmap_types.h>
#include <asm/tlbflush.h>
#include <asm/page.h>
/* undef for production */
#define HIGHMEM_DEBUG 1
extern pte_t *kmap_pte;
extern pgprot_t kmap_prot;
extern pte_t *pkmap_page_table;
extern void kmap_init(void) __init;
/*
* Right now we initialize only a single pte table. It can be extended
* easily, subsequent pte tables have to be allocated in one physical
* chunk of RAM.
*/
#define PKMAP_BASE CONFIG_HIGHMEM_START
#define LAST_PKMAP (1 << PTE_SHIFT)
#define LAST_PKMAP_MASK (LAST_PKMAP-1)
#define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT)
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
#define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL)
extern void *kmap_high(struct page *page);
extern void kunmap_high(struct page *page);
static inline void *kmap(struct page *page)
{
might_sleep();
if (page < highmem_start_page)
return page_address(page);
return kmap_high(page);
}
static inline void kunmap(struct page *page)
{
BUG_ON(in_interrupt());
if (page < highmem_start_page)
return;
kunmap_high(page);
}
/*
* The use of kmap_atomic/kunmap_atomic is discouraged - kmap/kunmap
* gives a more generic (and caching) interface. But kmap_atomic can
* be used in IRQ contexts, so in some (very limited) cases we need
* it.
*/
static inline void *kmap_atomic(struct page *page, enum km_type type)
{
unsigned int idx;
unsigned long vaddr;
/* even !CONFIG_PREEMPT needs this, for in_atomic in do_page_fault */
inc_preempt_count();
if (page < highmem_start_page)
return page_address(page);
idx = type + KM_TYPE_NR*smp_processor_id();
vaddr = KMAP_FIX_BEGIN + idx * PAGE_SIZE;
#ifdef HIGHMEM_DEBUG
BUG_ON(!pte_none(*(kmap_pte+idx)));
#endif
set_pte(kmap_pte+idx, mk_pte(page, kmap_prot));
flush_tlb_page(NULL, vaddr);
return (void*) vaddr;
}
static inline void kunmap_atomic(void *kvaddr, enum km_type type)
{
#ifdef HIGHMEM_DEBUG
unsigned long vaddr = (unsigned long) kvaddr & PAGE_MASK;
unsigned int idx = type + KM_TYPE_NR*smp_processor_id();
if (vaddr < KMAP_FIX_BEGIN) { // FIXME
dec_preempt_count();
preempt_check_resched();
return;
}
BUG_ON(vaddr != KMAP_FIX_BEGIN + idx * PAGE_SIZE);
/*
* force other mappings to Oops if they'll try to access
* this pte without first remap it
*/
pte_clear(kmap_pte+idx);
flush_tlb_page(NULL, vaddr);
#endif
dec_preempt_count();
preempt_check_resched();
}
static inline struct page *kmap_atomic_to_page(void *ptr)
{
unsigned long idx, vaddr = (unsigned long) ptr;
if (vaddr < KMAP_FIX_BEGIN)
return virt_to_page(ptr);
idx = (vaddr - KMAP_FIX_BEGIN) >> PAGE_SHIFT;
return pte_page(kmap_pte[idx]);
}
#define flush_cache_kmaps() flush_cache_all()
#endif /* __KERNEL__ */
#endif /* _ASM_HIGHMEM_H */

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/*
* Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
*/
#ifdef __KERNEL__
#ifndef _PPC_HW_IRQ_H
#define _PPC_HW_IRQ_H
#include <asm/ptrace.h>
#include <asm/reg.h>
extern void timer_interrupt(struct pt_regs *);
#define INLINE_IRQS
#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
#ifdef INLINE_IRQS
static inline void local_irq_disable(void)
{
unsigned long msr;
msr = mfmsr();
mtmsr(msr & ~MSR_EE);
__asm__ __volatile__("": : :"memory");
}
static inline void local_irq_enable(void)
{
unsigned long msr;
__asm__ __volatile__("": : :"memory");
msr = mfmsr();
mtmsr(msr | MSR_EE);
}
static inline void local_irq_save_ptr(unsigned long *flags)
{
unsigned long msr;
msr = mfmsr();
*flags = msr;
mtmsr(msr & ~MSR_EE);
__asm__ __volatile__("": : :"memory");
}
#define local_save_flags(flags) ((flags) = mfmsr())
#define local_irq_save(flags) local_irq_save_ptr(&flags)
#define local_irq_restore(flags) mtmsr(flags)
#else
extern void local_irq_enable(void);
extern void local_irq_disable(void);
extern void local_irq_restore(unsigned long);
extern void local_save_flags_ptr(unsigned long *);
#define local_save_flags(flags) local_save_flags_ptr(&flags)
#define local_irq_save(flags) ({local_save_flags(flags);local_irq_disable();})
#endif
extern void do_lost_interrupts(unsigned long);
#define mask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->disable) irq_desc[irq].handler->disable(irq);})
#define unmask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->enable) irq_desc[irq].handler->enable(irq);})
#define ack_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->ack) irq_desc[irq].handler->ack(irq);})
/* Should we handle this via lost interrupts and IPIs or should we don't care like
* we do now ? --BenH.
*/
struct hw_interrupt_type;
static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
#endif /* _PPC_HW_IRQ_H */
#endif /* __KERNEL__ */

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/*
* include/asm-ppc/hydra.h -- Mac I/O `Hydra' definitions
*
* Copyright (C) 1997 Geert Uytterhoeven
*
* This file is based on the following documentation:
*
* Macintosh Technology in the Common Hardware Reference Platform
* Apple Computer, Inc.
*
* © Copyright 1995 Apple Computer, Inc. All rights reserved.
*
* It's available online from http://chrp.apple.com/MacTech.pdf.
* You can obtain paper copies of this book from computer bookstores or by
* writing Morgan Kaufmann Publishers, Inc., 340 Pine Street, Sixth Floor, San
* Francisco, CA 94104. Reference ISBN 1-55860-393-X.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*/
#ifndef _ASMPPC_HYDRA_H
#define _ASMPPC_HYDRA_H
#ifdef __KERNEL__
struct Hydra {
/* DBDMA Controller Register Space */
char Pad1[0x30];
u_int CachePD;
u_int IDs;
u_int Feature_Control;
char Pad2[0x7fc4];
/* DBDMA Channel Register Space */
char SCSI_DMA[0x100];
char Pad3[0x300];
char SCCA_Tx_DMA[0x100];
char SCCA_Rx_DMA[0x100];
char SCCB_Tx_DMA[0x100];
char SCCB_Rx_DMA[0x100];
char Pad4[0x7800];
/* Device Register Space */
char SCSI[0x1000];
char ADB[0x1000];
char SCC_Legacy[0x1000];
char SCC[0x1000];
char Pad9[0x2000];
char VIA[0x2000];
char Pad10[0x28000];
char OpenPIC[0x40000];
};
extern volatile struct Hydra *Hydra;
/*
* Feature Control Register
*/
#define HYDRA_FC_SCC_CELL_EN 0x00000001 /* Enable SCC Clock */
#define HYDRA_FC_SCSI_CELL_EN 0x00000002 /* Enable SCSI Clock */
#define HYDRA_FC_SCCA_ENABLE 0x00000004 /* Enable SCC A Lines */
#define HYDRA_FC_SCCB_ENABLE 0x00000008 /* Enable SCC B Lines */
#define HYDRA_FC_ARB_BYPASS 0x00000010 /* Bypass Internal Arbiter */
#define HYDRA_FC_RESET_SCC 0x00000020 /* Reset SCC */
#define HYDRA_FC_MPIC_ENABLE 0x00000040 /* Enable OpenPIC */
#define HYDRA_FC_SLOW_SCC_PCLK 0x00000080 /* 1=15.6672, 0=25 MHz */
#define HYDRA_FC_MPIC_IS_MASTER 0x00000100 /* OpenPIC Master Mode */
/*
* OpenPIC Interrupt Sources
*/
#define HYDRA_INT_SIO 0
#define HYDRA_INT_SCSI_DMA 1
#define HYDRA_INT_SCCA_TX_DMA 2
#define HYDRA_INT_SCCA_RX_DMA 3
#define HYDRA_INT_SCCB_TX_DMA 4
#define HYDRA_INT_SCCB_RX_DMA 5
#define HYDRA_INT_SCSI 6
#define HYDRA_INT_SCCA 7
#define HYDRA_INT_SCCB 8
#define HYDRA_INT_VIA 9
#define HYDRA_INT_ADB 10
#define HYDRA_INT_ADB_NMI 11
#define HYDRA_INT_EXT1 12 /* PCI IRQW */
#define HYDRA_INT_EXT2 13 /* PCI IRQX */
#define HYDRA_INT_EXT3 14 /* PCI IRQY */
#define HYDRA_INT_EXT4 15 /* PCI IRQZ */
#define HYDRA_INT_EXT5 16 /* IDE Primay/Secondary */
#define HYDRA_INT_EXT6 17 /* IDE Secondary */
#define HYDRA_INT_EXT7 18 /* Power Off Request */
#define HYDRA_INT_SPARE 19
extern int hydra_init(void);
extern void macio_adb_init(void);
#endif /* __KERNEL__ */
#endif /* _ASMPPC_HYDRA_H */

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#ifndef _PPC_KERNEL_i8259_H
#define _PPC_KERNEL_i8259_H
#include <linux/irq.h>
extern struct hw_interrupt_type i8259_pic;
extern void i8259_init(long intack_addr);
extern int i8259_irq(struct pt_regs *regs);
#endif /* _PPC_KERNEL_i8259_H */

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/*
* Authors: Armin Kuster <akuster@mvista.com> and Tom Rini <trini@mvista.com>
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifdef __KERNEL__
#ifndef __ASM_IBM403_H__
#define __ASM_IBM403_H__
#include <linux/config.h>
#if defined(CONFIG_403GCX)
#define DCRN_BE_BASE 0x090
#define DCRN_DMA0_BASE 0x0C0
#define DCRN_DMA1_BASE 0x0C8
#define DCRN_DMA2_BASE 0x0D0
#define DCRN_DMA3_BASE 0x0D8
#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */
#define DCRN_DMASR_BASE 0x0E0
#define DCRN_EXIER_BASE 0x042
#define DCRN_EXISR_BASE 0x040
#define DCRN_IOCR_BASE 0x0A0
/* ------------------------------------------------------------------------- */
#endif
#ifdef DCRN_BE_BASE
#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register*/
#endif
/* DCRN_BESR */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DMES 0x40000000 /* DMA Error Status */
#define BESR_RWS 0x20000000 /* Read/Write Status */
#define BESR_ETMASK 0x1C000000 /* Error Type */
#define ET_PROT 0
#define ET_PARITY 1
#define ET_NCFG 2
#define ET_BUSERR 4
#define ET_BUSTO 6
#ifdef DCRN_CHCR_BASE
#define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */
#define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */
#endif
#define CHR1_CETE 0x00800000 /* CPU external timer enable */
#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
#ifdef DCRN_CHPSR_BASE
#define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */
#endif
#ifdef DCRN_CIC_BASE
#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */
#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */
#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */
#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */
#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */
#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */
#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */
#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */
#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */
#endif
#ifdef DCRN_CPMFR_BASE
#define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */
#endif
#ifndef CPM_AUD
#define CPM_AUD 0x00000000
#endif
#ifndef CPM_BRG
#define CPM_BRG 0x00000000
#endif
#ifndef CPM_CBS
#define CPM_CBS 0x00000000
#endif
#ifndef CPM_CPU
#define CPM_CPU 0x00000000
#endif
#ifndef CPM_DCP
#define CPM_DCP 0x00000000
#endif
#ifndef CPM_DCRX
#define CPM_DCRX 0x00000000
#endif
#ifndef CPM_DENC
#define CPM_DENC 0x00000000
#endif
#ifndef CPM_DMA
#define CPM_DMA 0x00000000
#endif
#ifndef CPM_DSCR
#define CPM_DSCR 0x00000000
#endif
#ifndef CPM_EBC
#define CPM_EBC 0x00000000
#endif
#ifndef CPM_EBIU
#define CPM_EBIU 0x00000000
#endif
#ifndef CPM_EMAC_MM
#define CPM_EMAC_MM 0x00000000
#endif
#ifndef CPM_EMAC_RM
#define CPM_EMAC_RM 0x00000000
#endif
#ifndef CPM_EMAC_TM
#define CPM_EMAC_TM 0x00000000
#endif
#ifndef CPM_GPIO0
#define CPM_GPIO0 0x00000000
#endif
#ifndef CPM_GPT
#define CPM_GPT 0x00000000
#endif
#ifndef CPM_I1284
#define CPM_I1284 0x00000000
#endif
#ifndef CPM_IIC0
#define CPM_IIC0 0x00000000
#endif
#ifndef CPM_IIC1
#define CPM_IIC1 0x00000000
#endif
#ifndef CPM_MSI
#define CPM_MSI 0x00000000
#endif
#ifndef CPM_PCI
#define CPM_PCI 0x00000000
#endif
#ifndef CPM_PLB
#define CPM_PLB 0x00000000
#endif
#ifndef CPM_SC0
#define CPM_SC0 0x00000000
#endif
#ifndef CPM_SC1
#define CPM_SC1 0x00000000
#endif
#ifndef CPM_SDRAM0
#define CPM_SDRAM0 0x00000000
#endif
#ifndef CPM_SDRAM1
#define CPM_SDRAM1 0x00000000
#endif
#ifndef CPM_TMRCLK
#define CPM_TMRCLK 0x00000000
#endif
#ifndef CPM_UART0
#define CPM_UART0 0x00000000
#endif
#ifndef CPM_UART1
#define CPM_UART1 0x00000000
#endif
#ifndef CPM_UART2
#define CPM_UART2 0x00000000
#endif
#ifndef CPM_UIC
#define CPM_UIC 0x00000000
#endif
#ifndef CPM_VID2
#define CPM_VID2 0x00000000
#endif
#ifndef CPM_XPT27
#define CPM_XPT27 0x00000000
#endif
#ifndef CPM_XPT54
#define CPM_XPT54 0x00000000
#endif
#ifdef DCRN_CPMSR_BASE
#define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */
#define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */
#endif
#ifdef DCRN_DCP0_BASE
#define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) /* Decompression Controller Address */
#define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) /* Decompression Controller Data */
#endif
#ifdef DCRN_DCRX_BASE
#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */
#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */
#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */
#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */
#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */
#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */
#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */
#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */
#endif
#ifdef DCRN_DMA0_BASE
#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control Register 0 */
#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */
#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) /* DMA Destination Address Register 0 */
#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Source Address Register 0 */
#ifdef DCRNCAP_DMA_CC
#define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) /* DMA Chained Count Register 0 */
#endif
#ifdef DCRNCAP_DMA_SG
#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 0 */
#endif
#endif
#ifdef DCRN_DMA1_BASE
#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control Register 1 */
#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */
#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) /* DMA Destination Address Register 1 */
#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */
#ifdef DCRNCAP_DMA_CC
#define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) /* DMA Chained Count Register 1 */
#endif
#ifdef DCRNCAP_DMA_SG
#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 1 */
#endif
#endif
#ifdef DCRN_DMA2_BASE
#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */
#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */
#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */
#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */
#ifdef DCRNCAP_DMA_CC
#define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */
#endif
#ifdef DCRNCAP_DMA_SG
#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */
#endif
#endif
#ifdef DCRN_DMA3_BASE
#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */
#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */
#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */
#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */
#ifdef DCRNCAP_DMA_CC
#define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */
#endif
#ifdef DCRNCAP_DMA_SG
#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */
#endif
#endif
#ifdef DCRN_DMASR_BASE
#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
#ifdef DCRNCAP_DMA_SG
#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
/* don't know if these two registers always exist if scatter/gather exists */
#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
#endif
#endif
#ifdef DCRN_EBC_BASE
#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */
#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */
#endif
#ifdef DCRN_EXIER_BASE
#define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */
#endif
#ifdef DCRN_EBIMC_BASE
#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */
#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */
#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */
#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */
#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */
#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */
#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */
#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */
#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10)/* BRC 0 */
#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11)/* BRC 1 */
#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12)/* BRC 2 */
#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13)/* BRC 3 */
#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14)/* BRC 4 */
#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15)/* BRC 5 */
#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16)/* BRC 6 */
#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17)/* BRC 7 */
#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */
#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */
#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */
#endif
#ifdef DCRN_EXISR_BASE
#define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */
#endif
#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
#ifdef DCRN_IOCR_BASE
#define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */
#endif
#define IOCR_E0TE 0x80000000
#define IOCR_E0LP 0x40000000
#define IOCR_E1TE 0x20000000
#define IOCR_E1LP 0x10000000
#define IOCR_E2TE 0x08000000
#define IOCR_E2LP 0x04000000
#define IOCR_E3TE 0x02000000
#define IOCR_E3LP 0x01000000
#define IOCR_E4TE 0x00800000
#define IOCR_E4LP 0x00400000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDO 0x00008000
#define IOCR_2XC 0x00004000
#define IOCR_ATC 0x00002000
#define IOCR_SPD 0x00001000
#define IOCR_BEM 0x00000800
#define IOCR_PTD 0x00000400
#define IOCR_ARE 0x00000080
#define IOCR_DRC 0x00000020
#define IOCR_RDM(x) (((x) & 0x3) << 3)
#define IOCR_TCS 0x00000004
#define IOCR_SCS 0x00000002
#define IOCR_SPC 0x00000001
#ifdef DCRN_MAL_BASE
#define DCRN_MALCR (DCRN_MAL_BASE + 0x0) /* MAL Configuration */
#define DCRN_MALDBR (DCRN_MAL_BASE + 0x3) /* Debug Register */
#define DCRN_MALESR (DCRN_MAL_BASE + 0x1) /* Error Status */
#define DCRN_MALIER (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */
#define DCRN_MALTXCARR (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */
#define DCRN_MALTXCASR (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */
#define DCRN_MALTXDEIR (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */
#define DCRN_MALTXEOBISR (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status */
#define DCRN_MALRXCARR (DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */
#define DCRN_MALRXCASR (DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */
#define DCRN_MALRXDEIR (DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */
#define DCRN_MALRXEOBISR (DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status */
#define DCRN_MALRXCTP0R (DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */
#define DCRN_MALTXCTP0R (DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */
#define DCRN_MALTXCTP1R (DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */
#define DCRN_MALRCBS0 (DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */
#endif
/* DCRN_MALCR */
#define MALCR_MMSR 0x80000000/* MAL Software reset */
#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
#define MALCR_PLBP_3 0x00C00000 /* highest */
#define MALCR_GA 0x00200000 /* Guarded Active Bit */
#define MALCR_OA 0x00100000 /* Ordered Active Bit */
#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
#define MALCR_PLBLT_2 0x00020000
#define MALCR_PLBLT_3 0x00010000
#define MALCR_PLBLT_4 0x00008000
#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */
#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
#define MALCR_LEA 0x00000002 /* Locked Error Active */
#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
/* DCRN_MALESR */
#define MALESR_EVB 0x80000000 /* Error Valid Bit */
#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
#define MALESR_DE 0x00100000 /* Descriptor Error */
#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
#define MALESR_OTE 0x00040000 /* OPB Timeout Error */
#define MALESR_OSE 0x00020000 /* OPB Slave Error */
#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
/* DCRN_MALIER */
#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
/* DCRN_MALTXEOBISR */
#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
#ifdef DCRN_OCM0_BASE
#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */
#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */
#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */
#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */
#endif
#ifdef DCRN_PLB0_BASE
#define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0)
#define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2)
/* doesn't exist on stb03xxx? */
#define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3)
#endif
#ifdef DCRN_PLB1_BASE
#define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0)
#define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1)
/* doesn't exist on stb03xxx? */
#define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2)
#endif
#ifdef DCRN_PLLMR_BASE
#define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */
#endif
#ifdef DCRN_POB0_BASE
#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0)
#define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2)
#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4)
#endif
#ifdef DCRN_SCCR_BASE
#define DCRN_SCCR (DCRN_SCCR_BASE + 0x0)
#endif
#ifdef DCRN_SDRAM0_BASE
#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */
#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */
#endif
#ifdef DCRN_UIC0_BASE
#define DCRN_UIC0_SR (DCRN_UIC0_BASE + 0x0)
#define DCRN_UIC0_ER (DCRN_UIC0_BASE + 0x2)
#define DCRN_UIC0_CR (DCRN_UIC0_BASE + 0x3)
#define DCRN_UIC0_PR (DCRN_UIC0_BASE + 0x4)
#define DCRN_UIC0_TR (DCRN_UIC0_BASE + 0x5)
#define DCRN_UIC0_MSR (DCRN_UIC0_BASE + 0x6)
#define DCRN_UIC0_VR (DCRN_UIC0_BASE + 0x7)
#define DCRN_UIC0_VCR (DCRN_UIC0_BASE + 0x8)
#endif
#ifdef DCRN_UIC1_BASE
#define DCRN_UIC1_SR (DCRN_UIC1_BASE + 0x0)
#define DCRN_UIC1_SRS (DCRN_UIC1_BASE + 0x1)
#define DCRN_UIC1_ER (DCRN_UIC1_BASE + 0x2)
#define DCRN_UIC1_CR (DCRN_UIC1_BASE + 0x3)
#define DCRN_UIC1_PR (DCRN_UIC1_BASE + 0x4)
#define DCRN_UIC1_TR (DCRN_UIC1_BASE + 0x5)
#define DCRN_UIC1_MSR (DCRN_UIC1_BASE + 0x6)
#define DCRN_UIC1_VR (DCRN_UIC1_BASE + 0x7)
#define DCRN_UIC1_VCR (DCRN_UIC1_BASE + 0x8)
#endif
#ifdef DCRN_SDRAM0_BASE
#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */
#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */
#endif
#ifdef DCRN_OCM0_BASE
#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */
#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */
#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */
#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */
#endif
#endif /* __ASM_IBM403_H__ */
#endif /* __KERNEL__ */

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/*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2002 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifdef __KERNEL__
#ifndef __ASM_IBM405_H__
#define __ASM_IBM405_H__
#ifdef DCRN_BE_BASE
#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */
#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register */
#endif
/* DCRN_BESR */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DMES 0x40000000 /* DMA Error Status */
#define BESR_RWS 0x20000000 /* Read/Write Status */
#define BESR_ETMASK 0x1C000000 /* Error Type */
#define ET_PROT 0
#define ET_PARITY 1
#define ET_NCFG 2
#define ET_BUSERR 4
#define ET_BUSTO 6
/* Clock and power management shifts for emacs */
#define IBM_CPM_EMMII 0 /* Shift value for MII */
#define IBM_CPM_EMRX 1 /* Shift value for recv */
#define IBM_CPM_EMTX 2 /* Shift value for MAC */
#ifdef DCRN_CHCR_BASE
#define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */
#define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */
#endif
#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */
#ifdef DCRN_CHPSR_BASE
#define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */
#endif
#ifdef DCRN_CPMFR_BASE
#define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */
#endif
#ifdef DCRN_CPMSR_BASE
#define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */
#define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */
#endif
#ifdef DCRN_DCP0_BASE
/* Decompression Controller Address */
#define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0)
/* Decompression Controller Data */
#define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1)
#else
#define DCRN_DCP0_CFGADDR 0x0
#define DCRN_DCP0_CFGDATA 0x0
#endif
#ifdef DCRN_DMA0_BASE
/* DMA Channel Control Register 0 */
#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0)
#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */
/* DMA Destination Address Register 0 */
#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2)
/* DMA Source Address Register 0 */
#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3)
#ifdef DCRNCAP_DMA_CC
/* DMA Chained Count Register 0 */
#define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4)
#endif
#ifdef DCRNCAP_DMA_SG
/* DMA Scatter/Gather Descriptor Addr 0 */
#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4)
#endif
#endif
#ifdef DCRN_DMA1_BASE
/* DMA Channel Control Register 1 */
#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0)
#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */
/* DMA Destination Address Register 1 */
#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2)
/* DMA Source Address Register 1 */
#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */
#ifdef DCRNCAP_DMA_CC
/* DMA Chained Count Register 1 */
#define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4)
#endif
#ifdef DCRNCAP_DMA_SG
/* DMA Scatter/Gather Descriptor Addr 1 */
#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4)
#endif
#endif
#ifdef DCRN_DMA2_BASE
#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */
#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */
#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */
#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */
#ifdef DCRNCAP_DMA_CC
#define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */
#endif
#ifdef DCRNCAP_DMA_SG
#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */
#endif
#endif
#ifdef DCRN_DMA3_BASE
#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */
#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */
#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */
#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */
#ifdef DCRNCAP_DMA_CC
#define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */
#endif
#ifdef DCRNCAP_DMA_SG
#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */
#endif
#endif
#ifdef DCRN_DMASR_BASE
#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
#ifdef DCRNCAP_DMA_SG
#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
/* don't know if these two registers always exist if scatter/gather exists */
#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
#endif
#endif
#ifdef DCRN_EBC_BASE
#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */
#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */
#endif
#ifdef DCRN_EXIER_BASE
#define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */
#endif
#ifdef DCRN_EXISR_BASE
#define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */
#endif
#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */
#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */
#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */
#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */
#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */
#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */
#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */
#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */
#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */
#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */
#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */
#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */
#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */
#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */
#ifdef DCRN_IOCR_BASE
#define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */
#endif
#define IOCR_E0TE 0x80000000
#define IOCR_E0LP 0x40000000
#define IOCR_E1TE 0x20000000
#define IOCR_E1LP 0x10000000
#define IOCR_E2TE 0x08000000
#define IOCR_E2LP 0x04000000
#define IOCR_E3TE 0x02000000
#define IOCR_E3LP 0x01000000
#define IOCR_E4TE 0x00800000
#define IOCR_E4LP 0x00400000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDO 0x00008000
#define IOCR_2XC 0x00004000
#define IOCR_ATC 0x00002000
#define IOCR_SPD 0x00001000
#define IOCR_BEM 0x00000800
#define IOCR_PTD 0x00000400
#define IOCR_ARE 0x00000080
#define IOCR_DRC 0x00000020
#define IOCR_RDM(x) (((x) & 0x3) << 3)
#define IOCR_TCS 0x00000004
#define IOCR_SCS 0x00000002
#define IOCR_SPC 0x00000001
#define DCRN_MALCR(base) (base + 0x0) /* MAL Configuration */
#define DCRN_MALDBR(base) ((base) + 0x3) /* Debug Register */
#define DCRN_MALESR(base) ((base) + 0x1) /* Error Status */
#define DCRN_MALIER(base) ((base) + 0x2) /* Interrupt Enable */
#define DCRN_MALTXCARR(base) ((base) + 0x5) /* TX Channed Active Reset Register */
#define DCRN_MALTXCASR(base) ((base) + 0x4) /* TX Channel Active Set Register */
#define DCRN_MALTXDEIR(base) ((base) + 0x7) /* Tx Descriptor Error Interrupt */
#define DCRN_MALTXEOBISR(base) ((base) + 0x6) /* Tx End of Buffer Interrupt Status */
#define DCRN_MALRXCARR(base) ((base) + 0x11) /* RX Channed Active Reset Register */
#define DCRN_MALRXCASR(base) ((base) + 0x10) /* RX Channel Active Set Register */
#define DCRN_MALRXDEIR(base) ((base) + 0x13) /* Rx Descriptor Error Interrupt */
#define DCRN_MALRXEOBISR(base) ((base) + 0x12) /* Rx End of Buffer Interrupt Status */
#define DCRN_MALRXCTP0R(base) ((base) + 0x40) /* Channel Rx 0 Channel Table Pointer */
#define DCRN_MALRXCTP1R(base) ((base) + 0x41) /* Channel Rx 1 Channel Table Pointer */
#define DCRN_MALTXCTP0R(base) ((base) + 0x20) /* Channel Tx 0 Channel Table Pointer */
#define DCRN_MALTXCTP1R(base) ((base) + 0x21) /* Channel Tx 1 Channel Table Pointer */
#define DCRN_MALTXCTP2R(base) ((base) + 0x22) /* Channel Tx 2 Channel Table Pointer */
#define DCRN_MALTXCTP3R(base) ((base) + 0x23) /* Channel Tx 3 Channel Table Pointer */
#define DCRN_MALRCBS0(base) ((base) + 0x60) /* Channel Rx 0 Channel Buffer Size */
#define DCRN_MALRCBS1(base) ((base) + 0x61) /* Channel Rx 1 Channel Buffer Size */
/* DCRN_MALCR */
#define MALCR_MMSR 0x80000000 /* MAL Software reset */
#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
#define MALCR_PLBP_3 0x00C00000 /* highest */
#define MALCR_GA 0x00200000 /* Guarded Active Bit */
#define MALCR_OA 0x00100000 /* Ordered Active Bit */
#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
#define MALCR_PLBLT_2 0x00020000
#define MALCR_PLBLT_3 0x00010000
#define MALCR_PLBLT_4 0x00008000
#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */
#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
#define MALCR_LEA 0x00000002 /* Locked Error Active */
#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
/* DCRN_MALESR */
#define MALESR_EVB 0x80000000 /* Error Valid Bit */
#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
#define MALESR_DE 0x00100000 /* Descriptor Error */
#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
#define MALESR_OTE 0x00040000 /* OPB Timeout Error */
#define MALESR_OSE 0x00020000 /* OPB Slave Error */
#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
/* DCRN_MALIER */
#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
/* DCRN_MALTXEOBISR */
#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
#ifdef DCRN_PLB0_BASE
#define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0)
#define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2)
/* doesn't exist on stb03xxx? */
#define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3)
#endif
#ifdef DCRN_PLB1_BASE
#define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0)
#define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1)
/* doesn't exist on stb03xxx? */
#define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2)
#endif
#ifdef DCRN_PLLMR_BASE
#define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */
#endif
#ifdef DCRN_POB0_BASE
#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0)
#define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2)
#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4)
#endif
#define DCRN_UIC_SR(base) (base + 0x0)
#define DCRN_UIC_ER(base) (base + 0x2)
#define DCRN_UIC_CR(base) (base + 0x3)
#define DCRN_UIC_PR(base) (base + 0x4)
#define DCRN_UIC_TR(base) (base + 0x5)
#define DCRN_UIC_MSR(base) (base + 0x6)
#define DCRN_UIC_VR(base) (base + 0x7)
#define DCRN_UIC_VCR(base) (base + 0x8)
#ifdef DCRN_SDRAM0_BASE
#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */
#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */
#endif
#ifdef DCRN_OCM0_BASE
#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */
#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */
#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */
#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */
#endif
#endif /* __ASM_IBM405_H__ */
#endif /* __KERNEL__ */

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/*
* include/asm-ppc/ibm44x.h
*
* PPC44x definitions
*
* Matt Porter <mporter@mvista.com>
*
* Copyright 2002-2003 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifdef __KERNEL__
#ifndef __ASM_IBM44x_H__
#define __ASM_IBM44x_H__
#include <linux/config.h>
#ifndef NR_BOARD_IRQS
#define NR_BOARD_IRQS 0
#endif
#define _IO_BASE isa_io_base
#define _ISA_MEM_BASE isa_mem_base
#define PCI_DRAM_OFFSET pci_dram_offset
/* TLB entry offset/size used for pinning kernel lowmem */
#define PPC44x_PIN_SHIFT 28
#define PPC44x_PIN_SIZE (1 << PPC44x_PIN_SHIFT)
/* Lowest TLB slot consumed by the default pinned TLBs */
#define PPC44x_LOW_SLOT 63
/*
* Standard 4GB "page" definitions
*/
#define PPC44x_IO_PAGE 0x0000000100000000ULL
#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL
/*
* 36-bit trap ranges
*/
#define PPC44x_IO_LO 0x40000000
#define PPC44x_IO_HI 0x40001000
#define PPC44x_PCICFG_LO 0x0ec00000
#define PPC44x_PCICFG_HI 0x0ec7ffff
#define PPC44x_PCIMEM_LO 0x80002000
#define PPC44x_PCIMEM_HI 0xffffffff
/*
* The "residual" board information structure the boot loader passes
* into the kernel.
*/
#ifndef __ASSEMBLY__
/*
* SPRN definitions
*/
#define SPRN_CPC0_GPIO 0xe5/BEARLRL
/*
* DCRN definitions
*/
#ifdef CONFIG_440GX
/* CPRs */
#define DCRN_CPR_CONFIG_ADDR 0xc
#define DCRN_CPR_CONFIG_DATA 0xd
#define DCRN_CPR_CLKUPD 0x0020
#define DCRN_CPR_PLLC 0x0040
#define DCRN_CPR_PLLD 0x0060
#define DCRN_CPR_PRIMAD 0x0080
#define DCRN_CPR_PRIMBD 0x00a0
#define DCRN_CPR_OPBD 0x00c0
#define DCRN_CPR_PERD 0x00e0
#define DCRN_CPR_MALD 0x0100
/* CPRs read/write helper macros */
#define CPR_READ(offset) ({\
mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
mfdcr(DCRN_CPR_CONFIG_DATA);})
#define CPR_WRITE(offset, data) ({\
mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
mtdcr(DCRN_CPR_CONFIG_DATA, data);})
/* SDRs */
#define DCRN_SDR_CONFIG_ADDR 0xe
#define DCRN_SDR_CONFIG_DATA 0xf
#define DCRN_SDR_PFC0 0x4100
#define DCRN_SDR_PFC1 0x4101
#define DCRN_SDR_PFC1_EPS 0x1c00000
#define DCRN_SDR_PFC1_EPS_SHIFT 22
#define DCRN_SDR_PFC1_RMII 0x02000000
#define DCRN_SDR_MFR 0x4300
#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */
#define DCRN_SDR_MFR_T0TXFL 0x00080000
#define DCRN_SDR_MFR_T0TXFH 0x00040000
#define DCRN_SDR_MFR_T1TXFL 0x00020000
#define DCRN_SDR_MFR_T1TXFH 0x00010000
#define DCRN_SDR_MFR_E0TXFL 0x00008000
#define DCRN_SDR_MFR_E0TXFH 0x00004000
#define DCRN_SDR_MFR_E0RXFL 0x00002000
#define DCRN_SDR_MFR_E0RXFH 0x00001000
#define DCRN_SDR_MFR_E1TXFL 0x00000800
#define DCRN_SDR_MFR_E1TXFH 0x00000400
#define DCRN_SDR_MFR_E1RXFL 0x00000200
#define DCRN_SDR_MFR_E1RXFH 0x00000100
#define DCRN_SDR_MFR_E2TXFL 0x00000080
#define DCRN_SDR_MFR_E2TXFH 0x00000040
#define DCRN_SDR_MFR_E2RXFL 0x00000020
#define DCRN_SDR_MFR_E2RXFH 0x00000010
#define DCRN_SDR_MFR_E3TXFL 0x00000008
#define DCRN_SDR_MFR_E3TXFH 0x00000004
#define DCRN_SDR_MFR_E3RXFL 0x00000002
#define DCRN_SDR_MFR_E3RXFH 0x00000001
#define DCRN_SDR_UART0 0x0120
#define DCRN_SDR_UART1 0x0121
/* SDR read/write helper macros */
#define SDR_READ(offset) ({\
mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
mfdcr(DCRN_SDR_CONFIG_DATA);})
#define SDR_WRITE(offset, data) ({\
mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
mtdcr(DCRN_SDR_CONFIG_DATA,data);})
#endif /* CONFIG_440GX */
/* Base DCRNs */
#define DCRN_DMA0_BASE 0x100
#define DCRN_DMA1_BASE 0x108
#define DCRN_DMA2_BASE 0x110
#define DCRN_DMA3_BASE 0x118
#define DCRN_DMASR_BASE 0x120
#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
#define DCRN_MAL_BASE 0x180
/* UIC */
#define DCRN_UIC0_BASE 0xc0
#define DCRN_UIC1_BASE 0xd0
#define DCRN_UIC2_BASE 0x210
#define DCRN_UICB_BASE 0x200
#define UIC0 DCRN_UIC0_BASE
#define UIC1 DCRN_UIC1_BASE
#define UIC2 DCRN_UIC2_BASE
#define UICB DCRN_UICB_BASE
#define DCRN_UIC_SR(base) (base + 0x0)
#define DCRN_UIC_ER(base) (base + 0x2)
#define DCRN_UIC_CR(base) (base + 0x3)
#define DCRN_UIC_PR(base) (base + 0x4)
#define DCRN_UIC_TR(base) (base + 0x5)
#define DCRN_UIC_MSR(base) (base + 0x6)
#define DCRN_UIC_VR(base) (base + 0x7)
#define DCRN_UIC_VCR(base) (base + 0x8)
#define UIC0_UIC1NC 30 /* UIC1 non-critical interrupt */
#define UIC0_UIC1CR 31 /* UIC1 critical interrupt */
#define UICB_UIC0NC 0x40000000
#define UICB_UIC1NC 0x10000000
#define UICB_UIC2NC 0x04000000
/* 440GP MAL DCRs */
#define DCRN_MALCR(base) (base + 0x0) /* Configuration */
#define DCRN_MALESR(base) (base + 0x1) /* Error Status */
#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */
#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */
#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */
#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */
#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */
#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */
#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */
#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */
#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */
#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */
#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */
#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */
#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
/* Compatibility DCRN's */
#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
#define MALCR_MMSR 0x80000000 /* MAL Software reset */
#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
#define MALCR_PLBP_3 0x00C00000 /* highest */
#define MALCR_GA 0x00200000 /* Guarded Active Bit */
#define MALCR_OA 0x00100000 /* Ordered Active Bit */
#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
#define MALCR_PLBLT_2 0x00020000
#define MALCR_PLBLT_3 0x00010000
#define MALCR_PLBLT_4 0x00008000
#ifdef CONFIG_440GP
#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */
#else
#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */
#endif
#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
#define MALCR_LEA 0x00000002 /* Locked Error Active */
#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
/* DCRN_MALESR */
#define MALESR_EVB 0x80000000 /* Error Valid Bit */
#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
#define MALESR_DE 0x00100000 /* Descriptor Error */
#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
#define MALESR_OTE 0x00040000 /* OPB Timeout Error */
#define MALESR_OSE 0x00020000 /* OPB Slave Error */
#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
/* DCRN_MALIER */
#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
/* DCRN_MALTXEOBISR */
#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
/* 440GP PLB Arbiter DCRs */
#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */
#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
/* 440GP Clock, PM, chip control */
#define DCRN_CPC0_SR 0x0b0
#define DCRN_CPC0_ER 0x0b1
#define DCRN_CPC0_FR 0x0b2
#define DCRN_CPC0_SYS0 0x0e0
#define DCRN_CPC0_SYS1 0x0e1
#define DCRN_CPC0_CUST0 0x0e2
#define DCRN_CPC0_CUST1 0x0e3
#define DCRN_CPC0_STRP0 0x0e4
#define DCRN_CPC0_STRP1 0x0e5
#define DCRN_CPC0_STRP2 0x0e6
#define DCRN_CPC0_STRP3 0x0e7
#define DCRN_CPC0_GPIO 0x0e8
#define DCRN_CPC0_PLB 0x0e9
#define DCRN_CPC0_CR1 0x0ea
#define DCRN_CPC0_CR0 0x0eb
#define DCRN_CPC0_MIRQ0 0x0ec
#define DCRN_CPC0_MIRQ1 0x0ed
#define DCRN_CPC0_JTAGID 0x0ef
/* 440GP DMA controller DCRs */
#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */
#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */
#define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */
#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */
#define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */
#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */
#define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */
#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */
#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */
#define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */
#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */
#define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */
#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */
#define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */
#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */
#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */
#define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */
#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */
#define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */
#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */
#define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */
#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */
#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */
#define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */
#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */
#define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */
#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */
#define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */
#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
/* 440GP DRAM controller DCRs */
#define DCRN_SDRAM0_CFGADDR 0x010
#define DCRN_SDRAM0_CFGDATA 0x011
#define SDRAM0_B0CR 0x40
#define SDRAM0_B1CR 0x44
#define SDRAM0_B2CR 0x48
#define SDRAM0_B3CR 0x4c
#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
#define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
#define SDRAM_CONFIG_SIZE_8M 0x00000001
#define SDRAM_CONFIG_SIZE_16M 0x00000002
#define SDRAM_CONFIG_SIZE_32M 0x00000003
#define SDRAM_CONFIG_SIZE_64M 0x00000004
#define SDRAM_CONFIG_SIZE_128M 0x00000005
#define SDRAM_CONFIG_SIZE_256M 0x00000006
#define SDRAM_CONFIG_SIZE_512M 0x00000007
#define PPC44x_MEM_SIZE_8M 0x00800000
#define PPC44x_MEM_SIZE_16M 0x01000000
#define PPC44x_MEM_SIZE_32M 0x02000000
#define PPC44x_MEM_SIZE_64M 0x04000000
#define PPC44x_MEM_SIZE_128M 0x08000000
#define PPC44x_MEM_SIZE_256M 0x10000000
#define PPC44x_MEM_SIZE_512M 0x20000000
#ifdef CONFIG_440GX
/* Internal SRAM Controller */
#define DCRN_SRAM0_SB0CR 0x020
#define DCRN_SRAM0_SB1CR 0x021
#define DCRN_SRAM0_SB2CR 0x022
#define DCRN_SRAM0_SB3CR 0x023
#define SRAM_SBCR_BAS0 0x80000000
#define SRAM_SBCR_BAS1 0x80010000
#define SRAM_SBCR_BAS2 0x80020000
#define SRAM_SBCR_BAS3 0x80030000
#define SRAM_SBCR_BU_MASK 0x00000180
#define SRAM_SBCR_BS_64KB 0x00000800
#define SRAM_SBCR_BU_RO 0x00000080
#define SRAM_SBCR_BU_RW 0x00000180
#define DCRN_SRAM0_BEAR 0x024
#define DCRN_SRAM0_BESR0 0x025
#define DCRN_SRAM0_BESR1 0x026
#define DCRN_SRAM0_PMEG 0x027
#define DCRN_SRAM0_CID 0x028
#define DCRN_SRAM0_REVID 0x029
#define DCRN_SRAM0_DPC 0x02a
#define SRAM_DPC_ENABLE 0x80000000
/* L2 Cache Controller */
#define DCRN_L2C0_CFG 0x030
#define L2C_CFG_L2M 0x80000000
#define L2C_CFG_ICU 0x40000000
#define L2C_CFG_DCU 0x20000000
#define L2C_CFG_DCW_MASK 0x1e000000
#define L2C_CFG_TPC 0x01000000
#define L2C_CFG_CPC 0x00800000
#define L2C_CFG_FRAN 0x00200000
#define L2C_CFG_SS_MASK 0x00180000
#define L2C_CFG_SS_256 0x00000000
#define L2C_CFG_CPIM 0x00040000
#define L2C_CFG_TPIM 0x00020000
#define L2C_CFG_LIM 0x00010000
#define L2C_CFG_PMUX_MASK 0x00007000
#define L2C_CFG_PMUX_SNP 0x00000000
#define L2C_CFG_PMUX_IF 0x00001000
#define L2C_CFG_PMUX_DF 0x00002000
#define L2C_CFG_PMUX_DS 0x00003000
#define L2C_CFG_PMIM 0x00000800
#define L2C_CFG_TPEI 0x00000400
#define L2C_CFG_CPEI 0x00000200
#define L2C_CFG_NAM 0x00000100
#define L2C_CFG_SMCM 0x00000080
#define L2C_CFG_NBRM 0x00000040
#define DCRN_L2C0_CMD 0x031
#define L2C_CMD_CLR 0x80000000
#define L2C_CMD_DIAG 0x40000000
#define L2C_CMD_INV 0x20000000
#define L2C_CMD_CCP 0x10000000
#define L2C_CMD_CTE 0x08000000
#define L2C_CMD_STRC 0x04000000
#define L2C_CMD_STPC 0x02000000
#define L2C_CMD_RPMC 0x01000000
#define L2C_CMD_HCC 0x00800000
#define DCRN_L2C0_ADDR 0x032
#define DCRN_L2C0_DATA 0x033
#define DCRN_L2C0_SR 0x034
#define L2C_SR_CC 0x80000000
#define L2C_SR_CPE 0x40000000
#define L2C_SR_TPE 0x20000000
#define L2C_SR_LRU 0x10000000
#define L2C_SR_PCS 0x08000000
#define DCRN_L2C0_REVID 0x035
#define DCRN_L2C0_SNP0 0x036
#define DCRN_L2C0_SNP1 0x037
#define L2C_SNP_BA_MASK 0xffff0000
#define L2C_SNP_SSR_MASK 0x0000f000
#define L2C_SNP_SSR_32G 0x0000f000
#define L2C_SNP_ESR 0x00000800
#endif /* CONFIG_440GX */
/*
* PCI-X definitions
*/
#define PCIX0_REG_BASE 0x20ec80000ULL
#define PCIX0_REG_SIZE 0x200
#define PCIX0_VENDID 0x000
#define PCIX0_DEVID 0x002
#define PCIX0_COMMAND 0x004
#define PCIX0_STATUS 0x006
#define PCIX0_REVID 0x008
#define PCIX0_CLS 0x009
#define PCIX0_CACHELS 0x00c
#define PCIX0_LATTIM 0x00d
#define PCIX0_HDTYPE 0x00e
#define PCIX0_BIST 0x00f
#define PCIX0_BAR0L 0x010
#define PCIX0_BAR0H 0x014
#define PCIX0_BAR1 0x018
#define PCIX0_BAR2L 0x01c
#define PCIX0_BAR2H 0x020
#define PCIX0_BAR3 0x024
#define PCIX0_CISPTR 0x028
#define PCIX0_SBSYSVID 0x02c
#define PCIX0_SBSYSID 0x02e
#define PCIX0_EROMBA 0x030
#define PCIX0_CAP 0x034
#define PCIX0_RES0 0x035
#define PCIX0_RES1 0x036
#define PCIX0_RES2 0x038
#define PCIX0_INTLN 0x03c
#define PCIX0_INTPN 0x03d
#define PCIX0_MINGNT 0x03e
#define PCIX0_MAXLTNCY 0x03f
#define PCIX0_BRDGOPT1 0x040
#define PCIX0_BRDGOPT2 0x044
#define PCIX0_ERREN 0x050
#define PCIX0_ERRSTS 0x054
#define PCIX0_PLBBESR 0x058
#define PCIX0_PLBBEARL 0x05c
#define PCIX0_PLBBEARH 0x060
#define PCIX0_POM0LAL 0x068
#define PCIX0_POM0LAH 0x06c
#define PCIX0_POM0SA 0x070
#define PCIX0_POM0PCIAL 0x074
#define PCIX0_POM0PCIAH 0x078
#define PCIX0_POM1LAL 0x07c
#define PCIX0_POM1LAH 0x080
#define PCIX0_POM1SA 0x084
#define PCIX0_POM1PCIAL 0x088
#define PCIX0_POM1PCIAH 0x08c
#define PCIX0_POM2SA 0x090
#define PCIX0_PIM0SAL 0x098
#define PCIX0_PIM0SA PCIX0_PIM0SAL
#define PCIX0_PIM0LAL 0x09c
#define PCIX0_PIM0LAH 0x0a0
#define PCIX0_PIM1SA 0x0a4
#define PCIX0_PIM1LAL 0x0a8
#define PCIX0_PIM1LAH 0x0ac
#define PCIX0_PIM2SAL 0x0b0
#define PCIX0_PIM2SA PCIX0_PIM2SAL
#define PCIX0_PIM2LAL 0x0b4
#define PCIX0_PIM2LAH 0x0b8
#define PCIX0_OMCAPID 0x0c0
#define PCIX0_OMNIPTR 0x0c1
#define PCIX0_OMMC 0x0c2
#define PCIX0_OMMA 0x0c4
#define PCIX0_OMMUA 0x0c8
#define PCIX0_OMMDATA 0x0cc
#define PCIX0_OMMEOI 0x0ce
#define PCIX0_PMCAPID 0x0d0
#define PCIX0_PMNIPTR 0x0d1
#define PCIX0_PMC 0x0d2
#define PCIX0_PMCSR 0x0d4
#define PCIX0_PMCSRBSE 0x0d6
#define PCIX0_PMDATA 0x0d7
#define PCIX0_PMSCRR 0x0d8
#define PCIX0_CAPID 0x0dc
#define PCIX0_NIPTR 0x0dd
#define PCIX0_CMD 0x0de
#define PCIX0_STS 0x0e0
#define PCIX0_IDR 0x0e4
#define PCIX0_CID 0x0e8
#define PCIX0_RID 0x0ec
#define PCIX0_PIM0SAH 0x0f8
#define PCIX0_PIM2SAH 0x0fc
#define PCIX0_MSGIL 0x100
#define PCIX0_MSGIH 0x104
#define PCIX0_MSGOL 0x108
#define PCIX0_MSGOH 0x10c
#define PCIX0_IM 0x1f8
#define IIC_OWN 0x55
#define IIC_CLOCK 50
#undef NR_UICS
#ifdef CONFIG_440GX
#define NR_UICS 3
#else
#define NR_UICS 2
#endif
#define UIC_CASCADE_MASK 0x0003 /* bits 30 & 31 */
#define BD_EMAC_ADDR(e,i) bi_enetaddr[e][i]
#include <asm/ibm4xx.h>
#endif /* __ASSEMBLY__ */
#endif /* __ASM_IBM44x_H__ */
#endif /* __KERNEL__ */

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/*
*
* Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
*
* Module name: ibm4xx.h
*
* Description:
* A generic include file which pulls in appropriate include files
* for specific board types based on configuration settings.
*
*/
#ifdef __KERNEL__
#ifndef __ASM_IBM4XX_H__
#define __ASM_IBM4XX_H__
#include <linux/config.h>
#include <asm/types.h>
#ifdef CONFIG_40x
#if defined(CONFIG_ASH)
#include <platforms/4xx/ash.h>
#endif
#if defined(CONFIG_BUBINGA)
#include <platforms/4xx/bubinga.h>
#endif
#if defined(CONFIG_CPCI405)
#include <platforms/4xx/cpci405.h>
#endif
#if defined(CONFIG_EP405)
#include <platforms/4xx/ep405.h>
#endif
#if defined(CONFIG_OAK)
#include <platforms/4xx/oak.h>
#endif
#if defined(CONFIG_REDWOOD_4)
#include <platforms/4xx/redwood.h>
#endif
#if defined(CONFIG_REDWOOD_5)
#include <platforms/4xx/redwood5.h>
#endif
#if defined(CONFIG_REDWOOD_6)
#include <platforms/4xx/redwood6.h>
#endif
#if defined(CONFIG_SYCAMORE)
#include <platforms/4xx/sycamore.h>
#endif
#if defined(CONFIG_WALNUT)
#include <platforms/4xx/walnut.h>
#endif
#if defined(CONFIG_XILINX_ML300)
#include <platforms/4xx/xilinx_ml300.h>
#endif
#ifndef __ASSEMBLY__
#ifdef CONFIG_40x
/*
* The "residual" board information structure the boot loader passes
* into the kernel.
*/
extern bd_t __res;
#endif
void ppc4xx_setup_arch(void);
void ppc4xx_map_io(void);
void ppc4xx_init_IRQ(void);
void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
unsigned long r6, unsigned long r7);
#endif
#ifndef PPC4xx_MACHINE_NAME
#define PPC4xx_MACHINE_NAME "Unidentified 4xx class"
#endif
/* IO_BASE is for PCI I/O.
* ISA not supported, just here to resolve copilation.
*/
#ifndef _IO_BASE
#define _IO_BASE 0xe8000000 /* The PCI address window */
#define _ISA_MEM_BASE 0
#define PCI_DRAM_OFFSET 0
#endif
#elif CONFIG_44x
#if defined(CONFIG_EBONY)
#include <platforms/4xx/ebony.h>
#endif
#if defined(CONFIG_OCOTEA)
#include <platforms/4xx/ocotea.h>
#endif
#ifndef __ASSEMBLY__
#ifdef CONFIG_40x
/*
* The "residual" board information structure the boot loader passes
* into the kernel.
*/
extern bd_t __res;
#endif
#endif
#endif /* CONFIG_40x */
#endif /* __ASM_IBM4XX_H__ */
#endif /* __KERNEL__ */

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/*
* ibm_ocp.h
*
* (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
* Mipsys - France
*
* Derived from work (c) Armin Kuster akuster@pacbell.net
*
* Additional support and port to 2.6 LDM/sysfs by
* Matt Porter <mporter@kernel.crashing.org>
* Copyright 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifdef __KERNEL__
#ifndef __IBM_OCP_H__
#define __IBM_OCP_H__
#include <asm/types.h>
/*
* IBM 4xx OCP system information
*/
struct ocp_sys_info_data {
int opb_bus_freq; /* OPB Bus Frequency (Hz) */
int ebc_bus_freq; /* EBC Bus Frequency (Hz) */
};
extern struct ocp_sys_info_data ocp_sys_info;
/*
* EMAC additional data and sysfs support
*
* Note about mdio_idx: When you have a zmii, it's usually
* not necessary, it covers the case of the 405EP which has
* the MDIO lines on EMAC0 only
*
* Note about phy_map: Per EMAC map of PHY ids which should
* be probed by emac_probe. Different EMACs can have
* overlapping maps.
*
* Note, this map uses inverse logic for bits:
* 0 - id should be probed
* 1 - id should be ignored
*
* Default value of 0x00000000 - will result in usual
* auto-detection logic.
*
*/
struct ocp_func_emac_data {
int rgmii_idx; /* RGMII device index or -1 */
int rgmii_mux; /* RGMII input of this EMAC */
int zmii_idx; /* ZMII device index or -1 */
int zmii_mux; /* ZMII input of this EMAC */
int mal_idx; /* MAL device index */
int mal_rx_chan; /* MAL rx channel number */
int mal_tx_chan; /* MAL tx channel number */
int wol_irq; /* WOL interrupt */
int mdio_idx; /* EMAC idx of MDIO master or -1 */
int tah_idx; /* TAH device index or -1 */
int jumbo; /* Jumbo frames capable flag */
int phy_mode; /* PHY type or configurable mode */
u8 mac_addr[6]; /* EMAC mac address */
u32 phy_map; /* EMAC phy map */
};
/* Sysfs support */
#define OCP_SYSFS_EMAC_DATA() \
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \
\
void ocp_show_emac_data(struct device *dev) \
{ \
device_create_file(dev, &dev_attr_emac_zmii_idx); \
device_create_file(dev, &dev_attr_emac_zmii_mux); \
device_create_file(dev, &dev_attr_emac_mal_idx); \
device_create_file(dev, &dev_attr_emac_mal_rx_chan); \
device_create_file(dev, &dev_attr_emac_mal_tx_chan); \
device_create_file(dev, &dev_attr_emac_wol_irq); \
device_create_file(dev, &dev_attr_emac_mdio_idx); \
}
#ifdef CONFIG_40x
/*
* Helper function to copy MAC addresses from the bd_t to OCP EMAC
* additions.
*
* The range of EMAC indices (inclusive) to be copied are the arguments.
*/
static inline void ibm_ocp_set_emac(int start, int end)
{
int i;
struct ocp_def *def;
/* Copy MAC addresses to EMAC additions */
for (i=start; i<=end; i++) {
def = ocp_get_one_device(OCP_VENDOR_IBM, OCP_FUNC_EMAC, i);
memcpy(((struct ocp_func_emac_data *)def->additions)->mac_addr,
&__res.bi_enetaddr[i],
6);
}
}
#endif
/*
* MAL additional data and sysfs support
*/
struct ocp_func_mal_data {
int num_tx_chans; /* Number of TX channels */
int num_rx_chans; /* Number of RX channels */
int txeob_irq; /* TX End Of Buffer IRQ */
int rxeob_irq; /* RX End Of Buffer IRQ */
int txde_irq; /* TX Descriptor Error IRQ */
int rxde_irq; /* RX Descriptor Error IRQ */
int serr_irq; /* MAL System Error IRQ */
};
#define OCP_SYSFS_MAL_DATA() \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_tx_chans) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, num_rx_chans) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txeob_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxeob_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, txde_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, rxde_irq) \
OCP_SYSFS_ADDTL(struct ocp_func_mal_data, "%d\n", mal, serr_irq) \
\
void ocp_show_mal_data(struct device *dev) \
{ \
device_create_file(dev, &dev_attr_mal_num_tx_chans); \
device_create_file(dev, &dev_attr_mal_num_rx_chans); \
device_create_file(dev, &dev_attr_mal_txeob_irq); \
device_create_file(dev, &dev_attr_mal_rxeob_irq); \
device_create_file(dev, &dev_attr_mal_txde_irq); \
device_create_file(dev, &dev_attr_mal_rxde_irq); \
device_create_file(dev, &dev_attr_mal_serr_irq); \
}
/*
* IIC additional data and sysfs support
*/
struct ocp_func_iic_data {
int fast_mode; /* IIC fast mode enabled */
};
#define OCP_SYSFS_IIC_DATA() \
OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \
\
void ocp_show_iic_data(struct device *dev) \
{ \
device_create_file(dev, &dev_attr_iic_fast_mode); \
}
#endif /* __IBM_OCP_H__ */
#endif /* __KERNEL__ */

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/*
* Author: Armin Kuster <akuster@mvista.com>
*
* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifdef __KERNEL__
#ifndef __ASM_IBM_OCP_PCI_H__
#define __ASM_IBM_OCP_PCI_H__
/* PCI 32 */
struct pmm_regs {
u32 la;
u32 ma;
u32 pcila;
u32 pciha;
};
typedef struct pcil0_regs {
struct pmm_regs pmm[3];
u32 ptm1ms;
u32 ptm1la;
u32 ptm2ms;
u32 ptm2la;
} pci0_t;
#endif /* __ASM_IBM_OCP_PCI_H__ */
#endif /* __KERNEL__ */

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/*
* linux/include/asm-ppc/ide.h
*
* Copyright (C) 1994-1996 Linus Torvalds & authors */
/*
* This file contains the ppc architecture specific IDE code.
*/
#ifndef __ASMPPC_IDE_H
#define __ASMPPC_IDE_H
#ifdef __KERNEL__
#include <linux/sched.h>
#include <asm/mpc8xx.h>
#ifndef MAX_HWIFS
#define MAX_HWIFS 8
#endif
#include <linux/config.h>
#include <linux/hdreg.h>
#include <linux/ioport.h>
#include <asm/io.h>
extern void __ide_mm_insw(void __iomem *port, void *addr, u32 count);
extern void __ide_mm_outsw(void __iomem *port, void *addr, u32 count);
extern void __ide_mm_insl(void __iomem *port, void *addr, u32 count);
extern void __ide_mm_outsl(void __iomem *port, void *addr, u32 count);
struct ide_machdep_calls {
int (*default_irq)(unsigned long base);
unsigned long (*default_io_base)(int index);
void (*ide_init_hwif)(hw_regs_t *hw,
unsigned long data_port,
unsigned long ctrl_port,
int *irq);
};
extern struct ide_machdep_calls ppc_ide_md;
#undef SUPPORT_SLOW_DATA_PORTS
#define SUPPORT_SLOW_DATA_PORTS 0
#define IDE_ARCH_OBSOLETE_DEFAULTS
static __inline__ int ide_default_irq(unsigned long base)
{
if (ppc_ide_md.default_irq)
return ppc_ide_md.default_irq(base);
return 0;
}
static __inline__ unsigned long ide_default_io_base(int index)
{
if (ppc_ide_md.default_io_base)
return ppc_ide_md.default_io_base(index);
return 0;
}
#define IDE_ARCH_OBSOLETE_INIT
#define ide_default_io_ctl(base) ((base) + 0x206) /* obsolete */
#ifdef CONFIG_PCI
#define ide_init_default_irq(base) (0)
#else
#define ide_init_default_irq(base) ide_default_irq(base)
#endif
#if (defined CONFIG_APUS || defined CONFIG_BLK_DEV_MPC8xx_IDE )
#define IDE_ARCH_ACK_INTR 1
#define ide_ack_intr(hwif) (hwif->hw.ack_intr ? hwif->hw.ack_intr(hwif) : 1)
#endif
#endif /* __KERNEL__ */
#endif /* __ASMPPC_IDE_H */

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/*
* include/asm-ppc/immap_85xx.h
*
* MPC85xx Internal Memory Map
*
* Maintainer: Kumar Gala <kumar.gala@freescale.com>
*
* Copyright 2004 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifdef __KERNEL__
#ifndef __ASM_IMMAP_85XX_H__
#define __ASM_IMMAP_85XX_H__
/* Eventually this should define all the IO block registers in 85xx */
/* PCI Registers */
typedef struct ccsr_pci {
uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */
uint cfg_data; /* 0x.004 - PCI Configuration Data Register */
uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
char res1[3060];
uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */
uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */
uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */
char res2[4];
uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */
char res3[12];
uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */
uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */
uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */
char res4[4];
uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */
char res5[12];
uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */
uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */
uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */
char res6[4];
uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */
char res7[12];
uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */
uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */
uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */
char res8[4];
uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */
char res9[12];
uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */
uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */
uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */
char res10[4];
uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */
char res11[268];
uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */
char res12[4];
uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */
uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */
uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */
char res13[12];
uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */
char res14[4];
uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */
uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */
uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */
char res15[12];
uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */
char res16[4];
uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */
char res17[4];
uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */
char res18[12];
uint err_dr; /* 0x.e00 - PCI Error Detect Register */
uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */
uint err_en; /* 0x.e08 - PCI Error Enable Register */
uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */
uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */
uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */
uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */
uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */
uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */
uint pci_timr; /* 0x.e24 - PCI Timer Register */
char res19[472];
} ccsr_pci_t;
/* Global Utility Registers */
typedef struct ccsr_guts {
uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
uint pordevsr; /* 0x.000c - POR I/O Device Status Register */
uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
char res1[12];
uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */
char res2[12];
uint gpiocr; /* 0x.0030 - GPIO Control Register */
char res3[12];
uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
char res4[12];
uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */
char res5[12];
uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
char res6[12];
uint devdisr; /* 0x.0070 - Device Disable Control */
char res7[12];
uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
char res8[12];
uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */
char res9[12];
uint pvr; /* 0x.00a0 - Processor Version Register */
uint svr; /* 0x.00a4 - System Version Register */
char res10[3416];
uint clkocr; /* 0x.0e00 - Clock Out Select Register */
char res11[12];
uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
char res12[12];
uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
char res13[61916];
} ccsr_guts_t;
#endif /* __ASM_IMMAP_85XX_H__ */
#endif /* __KERNEL__ */

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/*
* CPM2 Internal Memory Map
* Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
*
* The Internal Memory Map for devices with CPM2 on them. This
* is the superset of all CPM2 devices (8260, 8266, 8280, 8272,
* 8560).
*/
#ifdef __KERNEL__
#ifndef __IMMAP_CPM2__
#define __IMMAP_CPM2__
/* System configuration registers.
*/
typedef struct sys_82xx_conf {
u32 sc_siumcr;
u32 sc_sypcr;
u8 res1[6];
u16 sc_swsr;
u8 res2[20];
u32 sc_bcr;
u8 sc_ppc_acr;
u8 res3[3];
u32 sc_ppc_alrh;
u32 sc_ppc_alrl;
u8 sc_lcl_acr;
u8 res4[3];
u32 sc_lcl_alrh;
u32 sc_lcl_alrl;
u32 sc_tescr1;
u32 sc_tescr2;
u32 sc_ltescr1;
u32 sc_ltescr2;
u32 sc_pdtea;
u8 sc_pdtem;
u8 res5[3];
u32 sc_ldtea;
u8 sc_ldtem;
u8 res6[163];
} sysconf_82xx_cpm2_t;
typedef struct sys_85xx_conf {
u32 sc_cear;
u16 sc_ceer;
u16 sc_cemr;
u8 res1[70];
u32 sc_smaer;
u8 res2[4];
u32 sc_smevr;
u32 sc_smctr;
u32 sc_lmaer;
u8 res3[4];
u32 sc_lmevr;
u32 sc_lmctr;
u8 res4[144];
} sysconf_85xx_cpm2_t;
typedef union sys_conf {
sysconf_82xx_cpm2_t siu_82xx;
sysconf_85xx_cpm2_t siu_85xx;
} sysconf_cpm2_t;
/* Memory controller registers.
*/
typedef struct mem_ctlr {
u32 memc_br0;
u32 memc_or0;
u32 memc_br1;
u32 memc_or1;
u32 memc_br2;
u32 memc_or2;
u32 memc_br3;
u32 memc_or3;
u32 memc_br4;
u32 memc_or4;
u32 memc_br5;
u32 memc_or5;
u32 memc_br6;
u32 memc_or6;
u32 memc_br7;
u32 memc_or7;
u32 memc_br8;
u32 memc_or8;
u32 memc_br9;
u32 memc_or9;
u32 memc_br10;
u32 memc_or10;
u32 memc_br11;
u32 memc_or11;
u8 res1[8];
u32 memc_mar;
u8 res2[4];
u32 memc_mamr;
u32 memc_mbmr;
u32 memc_mcmr;
u8 res3[8];
u16 memc_mptpr;
u8 res4[2];
u32 memc_mdr;
u8 res5[4];
u32 memc_psdmr;
u32 memc_lsdmr;
u8 memc_purt;
u8 res6[3];
u8 memc_psrt;
u8 res7[3];
u8 memc_lurt;
u8 res8[3];
u8 memc_lsrt;
u8 res9[3];
u32 memc_immr;
u32 memc_pcibr0;
u32 memc_pcibr1;
u8 res10[16];
u32 memc_pcimsk0;
u32 memc_pcimsk1;
u8 res11[52];
} memctl_cpm2_t;
/* System Integration Timers.
*/
typedef struct sys_int_timers {
u8 res1[32];
u16 sit_tmcntsc;
u8 res2[2];
u32 sit_tmcnt;
u8 res3[4];
u32 sit_tmcntal;
u8 res4[16];
u16 sit_piscr;
u8 res5[2];
u32 sit_pitc;
u32 sit_pitr;
u8 res6[94];
u8 res7[390];
} sit_cpm2_t;
#define PISCR_PIRQ_MASK ((u16)0xff00)
#define PISCR_PS ((u16)0x0080)
#define PISCR_PIE ((u16)0x0004)
#define PISCR_PTF ((u16)0x0002)
#define PISCR_PTE ((u16)0x0001)
/* PCI Controller.
*/
typedef struct pci_ctlr {
u32 pci_omisr;
u32 pci_omimr;
u8 res1[8];
u32 pci_ifqpr;
u32 pci_ofqpr;
u8 res2[8];
u32 pci_imr0;
u32 pci_imr1;
u32 pci_omr0;
u32 pci_omr1;
u32 pci_odr;
u8 res3[4];
u32 pci_idr;
u8 res4[20];
u32 pci_imisr;
u32 pci_imimr;
u8 res5[24];
u32 pci_ifhpr;
u8 res6[4];
u32 pci_iftpr;
u8 res7[4];
u32 pci_iphpr;
u8 res8[4];
u32 pci_iptpr;
u8 res9[4];
u32 pci_ofhpr;
u8 res10[4];
u32 pci_oftpr;
u8 res11[4];
u32 pci_ophpr;
u8 res12[4];
u32 pci_optpr;
u8 res13[8];
u32 pci_mucr;
u8 res14[8];
u32 pci_qbar;
u8 res15[12];
u32 pci_dmamr0;
u32 pci_dmasr0;
u32 pci_dmacdar0;
u8 res16[4];
u32 pci_dmasar0;
u8 res17[4];
u32 pci_dmadar0;
u8 res18[4];
u32 pci_dmabcr0;
u32 pci_dmandar0;
u8 res19[86];
u32 pci_dmamr1;
u32 pci_dmasr1;
u32 pci_dmacdar1;
u8 res20[4];
u32 pci_dmasar1;
u8 res21[4];
u32 pci_dmadar1;
u8 res22[4];
u32 pci_dmabcr1;
u32 pci_dmandar1;
u8 res23[88];
u32 pci_dmamr2;
u32 pci_dmasr2;
u32 pci_dmacdar2;
u8 res24[4];
u32 pci_dmasar2;
u8 res25[4];
u32 pci_dmadar2;
u8 res26[4];
u32 pci_dmabcr2;
u32 pci_dmandar2;
u8 res27[88];
u32 pci_dmamr3;
u32 pci_dmasr3;
u32 pci_dmacdar3;
u8 res28[4];
u32 pci_dmasar3;
u8 res29[4];
u32 pci_dmadar3;
u8 res30[4];
u32 pci_dmabcr3;
u32 pci_dmandar3;
u8 res31[344];
u32 pci_potar0;
u8 res32[4];
u32 pci_pobar0;
u8 res33[4];
u32 pci_pocmr0;
u8 res34[4];
u32 pci_potar1;
u8 res35[4];
u32 pci_pobar1;
u8 res36[4];
u32 pci_pocmr1;
u8 res37[4];
u32 pci_potar2;
u8 res38[4];
u32 pci_pobar2;
u8 res39[4];
u32 pci_pocmr2;
u8 res40[50];
u32 pci_ptcr;
u32 pci_gpcr;
u32 pci_gcr;
u32 pci_esr;
u32 pci_emr;
u32 pci_ecr;
u32 pci_eacr;
u8 res41[4];
u32 pci_edcr;
u8 res42[4];
u32 pci_eccr;
u8 res43[44];
u32 pci_pitar1;
u8 res44[4];
u32 pci_pibar1;
u8 res45[4];
u32 pci_picmr1;
u8 res46[4];
u32 pci_pitar0;
u8 res47[4];
u32 pci_pibar0;
u8 res48[4];
u32 pci_picmr0;
u8 res49[4];
u32 pci_cfg_addr;
u32 pci_cfg_data;
u32 pci_int_ack;
u8 res50[756];
} pci_cpm2_t;
/* Interrupt Controller.
*/
typedef struct interrupt_controller {
u16 ic_sicr;
u8 res1[2];
u32 ic_sivec;
u32 ic_sipnrh;
u32 ic_sipnrl;
u32 ic_siprr;
u32 ic_scprrh;
u32 ic_scprrl;
u32 ic_simrh;
u32 ic_simrl;
u32 ic_siexr;
u8 res2[88];
} intctl_cpm2_t;
/* Clocks and Reset.
*/
typedef struct clk_and_reset {
u32 car_sccr;
u8 res1[4];
u32 car_scmr;
u8 res2[4];
u32 car_rsr;
u32 car_rmr;
u8 res[104];
} car_cpm2_t;
/* Input/Output Port control/status registers.
* Names consistent with processor manual, although they are different
* from the original 8xx names.......
*/
typedef struct io_port {
u32 iop_pdira;
u32 iop_ppara;
u32 iop_psora;
u32 iop_podra;
u32 iop_pdata;
u8 res1[12];
u32 iop_pdirb;
u32 iop_pparb;
u32 iop_psorb;
u32 iop_podrb;
u32 iop_pdatb;
u8 res2[12];
u32 iop_pdirc;
u32 iop_pparc;
u32 iop_psorc;
u32 iop_podrc;
u32 iop_pdatc;
u8 res3[12];
u32 iop_pdird;
u32 iop_ppard;
u32 iop_psord;
u32 iop_podrd;
u32 iop_pdatd;
u8 res4[12];
} iop_cpm2_t;
/* Communication Processor Module Timers
*/
typedef struct cpm_timers {
u8 cpmt_tgcr1;
u8 res1[3];
u8 cpmt_tgcr2;
u8 res2[11];
u16 cpmt_tmr1;
u16 cpmt_tmr2;
u16 cpmt_trr1;
u16 cpmt_trr2;
u16 cpmt_tcr1;
u16 cpmt_tcr2;
u16 cpmt_tcn1;
u16 cpmt_tcn2;
u16 cpmt_tmr3;
u16 cpmt_tmr4;
u16 cpmt_trr3;
u16 cpmt_trr4;
u16 cpmt_tcr3;
u16 cpmt_tcr4;
u16 cpmt_tcn3;
u16 cpmt_tcn4;
u16 cpmt_ter1;
u16 cpmt_ter2;
u16 cpmt_ter3;
u16 cpmt_ter4;
u8 res3[584];
} cpmtimer_cpm2_t;
/* DMA control/status registers.
*/
typedef struct sdma_csr {
u8 res0[24];
u8 sdma_sdsr;
u8 res1[3];
u8 sdma_sdmr;
u8 res2[3];
u8 sdma_idsr1;
u8 res3[3];
u8 sdma_idmr1;
u8 res4[3];
u8 sdma_idsr2;
u8 res5[3];
u8 sdma_idmr2;
u8 res6[3];
u8 sdma_idsr3;
u8 res7[3];
u8 sdma_idmr3;
u8 res8[3];
u8 sdma_idsr4;
u8 res9[3];
u8 sdma_idmr4;
u8 res10[707];
} sdma_cpm2_t;
/* Fast controllers
*/
typedef struct fcc {
u32 fcc_gfmr;
u32 fcc_fpsmr;
u16 fcc_ftodr;
u8 res1[2];
u16 fcc_fdsr;
u8 res2[2];
u16 fcc_fcce;
u8 res3[2];
u16 fcc_fccm;
u8 res4[2];
u8 fcc_fccs;
u8 res5[3];
u8 fcc_ftirr_phy[4];
} fcc_t;
/* Fast controllers continued
*/
typedef struct fcc_c {
u32 fcc_firper;
u32 fcc_firer;
u32 fcc_firsr_hi;
u32 fcc_firsr_lo;
u8 fcc_gfemr;
u8 res1[15];
} fcc_c_t;
/* TC Layer
*/
typedef struct tclayer {
u16 tc_tcmode;
u16 tc_cdsmr;
u16 tc_tcer;
u16 tc_rcc;
u16 tc_tcmr;
u16 tc_fcc;
u16 tc_ccc;
u16 tc_icc;
u16 tc_tcc;
u16 tc_ecc;
u8 res1[12];
} tclayer_t;
/* I2C
*/
typedef struct i2c {
u8 i2c_i2mod;
u8 res1[3];
u8 i2c_i2add;
u8 res2[3];
u8 i2c_i2brg;
u8 res3[3];
u8 i2c_i2com;
u8 res4[3];
u8 i2c_i2cer;
u8 res5[3];
u8 i2c_i2cmr;
u8 res6[331];
} i2c_cpm2_t;
typedef struct scc { /* Serial communication channels */
u32 scc_gsmrl;
u32 scc_gsmrh;
u16 scc_psmr;
u8 res1[2];
u16 scc_todr;
u16 scc_dsr;
u16 scc_scce;
u8 res2[2];
u16 scc_sccm;
u8 res3;
u8 scc_sccs;
u8 res4[8];
} scc_t;
typedef struct smc { /* Serial management channels */
u8 res1[2];
u16 smc_smcmr;
u8 res2[2];
u8 smc_smce;
u8 res3[3];
u8 smc_smcm;
u8 res4[5];
} smc_t;
/* Serial Peripheral Interface.
*/
typedef struct spi_ctrl {
u16 spi_spmode;
u8 res1[4];
u8 spi_spie;
u8 res2[3];
u8 spi_spim;
u8 res3[2];
u8 spi_spcom;
u8 res4[82];
} spictl_cpm2_t;
/* CPM Mux.
*/
typedef struct cpmux {
u8 cmx_si1cr;
u8 res1;
u8 cmx_si2cr;
u8 res2;
u32 cmx_fcr;
u32 cmx_scr;
u8 cmx_smr;
u8 res3;
u16 cmx_uar;
u8 res4[16];
} cpmux_t;
/* SIRAM control
*/
typedef struct siram {
u16 si_amr;
u16 si_bmr;
u16 si_cmr;
u16 si_dmr;
u8 si_gmr;
u8 res1;
u8 si_cmdr;
u8 res2;
u8 si_str;
u8 res3;
u16 si_rsr;
} siramctl_t;
typedef struct mcc {
u16 mcc_mcce;
u8 res1[2];
u16 mcc_mccm;
u8 res2[2];
u8 mcc_mccf;
u8 res3[7];
} mcc_t;
typedef struct comm_proc {
u32 cp_cpcr;
u32 cp_rccr;
u8 res1[14];
u16 cp_rter;
u8 res2[2];
u16 cp_rtmr;
u16 cp_rtscr;
u8 res3[2];
u32 cp_rtsr;
u8 res4[12];
} cpm_cpm2_t;
/* USB Controller.
*/
typedef struct usb_ctlr {
u8 usb_usmod;
u8 usb_usadr;
u8 usb_uscom;
u8 res1[1];
u16 usb_usep1;
u16 usb_usep2;
u16 usb_usep3;
u16 usb_usep4;
u8 res2[4];
u16 usb_usber;
u8 res3[2];
u16 usb_usbmr;
u8 usb_usbs;
u8 res4[7];
} usb_cpm2_t;
/* ...and the whole thing wrapped up....
*/
typedef struct immap {
/* Some references are into the unique and known dpram spaces,
* others are from the generic base.
*/
#define im_dprambase im_dpram1
u8 im_dpram1[16*1024];
u8 res1[16*1024];
u8 im_dpram2[4*1024];
u8 res2[8*1024];
u8 im_dpram3[4*1024];
u8 res3[16*1024];
sysconf_cpm2_t im_siu_conf; /* SIU Configuration */
memctl_cpm2_t im_memctl; /* Memory Controller */
sit_cpm2_t im_sit; /* System Integration Timers */
pci_cpm2_t im_pci; /* PCI Controller */
intctl_cpm2_t im_intctl; /* Interrupt Controller */
car_cpm2_t im_clkrst; /* Clocks and reset */
iop_cpm2_t im_ioport; /* IO Port control/status */
cpmtimer_cpm2_t im_cpmtimer; /* CPM timers */
sdma_cpm2_t im_sdma; /* SDMA control/status */
fcc_t im_fcc[3]; /* Three FCCs */
u8 res4z[32];
fcc_c_t im_fcc_c[3]; /* Continued FCCs */
u8 res4[32];
tclayer_t im_tclayer[8]; /* Eight TCLayers */
u16 tc_tcgsr;
u16 tc_tcger;
/* First set of baud rate generators.
*/
u8 res[236];
u32 im_brgc5;
u32 im_brgc6;
u32 im_brgc7;
u32 im_brgc8;
u8 res5[608];
i2c_cpm2_t im_i2c; /* I2C control/status */
cpm_cpm2_t im_cpm; /* Communication processor */
/* Second set of baud rate generators.
*/
u32 im_brgc1;
u32 im_brgc2;
u32 im_brgc3;
u32 im_brgc4;
scc_t im_scc[4]; /* Four SCCs */
smc_t im_smc[2]; /* Couple of SMCs */
spictl_cpm2_t im_spi; /* A SPI */
cpmux_t im_cpmux; /* CPM clock route mux */
siramctl_t im_siramctl1; /* First SI RAM Control */
mcc_t im_mcc1; /* First MCC */
siramctl_t im_siramctl2; /* Second SI RAM Control */
mcc_t im_mcc2; /* Second MCC */
usb_cpm2_t im_usb; /* USB Controller */
u8 res6[1153];
u16 im_si1txram[256];
u8 res7[512];
u16 im_si1rxram[256];
u8 res8[512];
u16 im_si2txram[256];
u8 res9[512];
u16 im_si2rxram[256];
u8 res10[512];
u8 res11[4096];
} cpm2_map_t;
extern cpm2_map_t *cpm2_immr;
#endif /* __IMMAP_CPM2__ */
#endif /* __KERNEL__ */

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#ifdef __KERNEL__
#ifndef _PPC_IO_H
#define _PPC_IO_H
#include <linux/config.h>
#include <linux/string.h>
#include <linux/types.h>
#include <asm/page.h>
#include <asm/byteorder.h>
#include <asm/mmu.h>
#define SIO_CONFIG_RA 0x398
#define SIO_CONFIG_RD 0x399
#define SLOW_DOWN_IO
#define PMAC_ISA_MEM_BASE 0
#define PMAC_PCI_DRAM_OFFSET 0
#define CHRP_ISA_IO_BASE 0xf8000000
#define CHRP_ISA_MEM_BASE 0xf7000000
#define CHRP_PCI_DRAM_OFFSET 0
#define PREP_ISA_IO_BASE 0x80000000
#define PREP_ISA_MEM_BASE 0xc0000000
#define PREP_PCI_DRAM_OFFSET 0x80000000
#if defined(CONFIG_4xx)
#include <asm/ibm4xx.h>
#elif defined(CONFIG_8xx)
#include <asm/mpc8xx.h>
#elif defined(CONFIG_8260)
#include <asm/mpc8260.h>
#elif defined(CONFIG_85xx)
#include <asm/mpc85xx.h>
#elif defined(CONFIG_APUS)
#define _IO_BASE 0
#define _ISA_MEM_BASE 0
#define PCI_DRAM_OFFSET 0
#else /* Everyone else */
#define _IO_BASE isa_io_base
#define _ISA_MEM_BASE isa_mem_base
#define PCI_DRAM_OFFSET pci_dram_offset
#endif /* Platform-dependent I/O */
#define ___IO_BASE ((void __iomem *)_IO_BASE)
extern unsigned long isa_io_base;
extern unsigned long isa_mem_base;
extern unsigned long pci_dram_offset;
/*
* 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
*
* Read operations have additional twi & isync to make sure the read
* is actually performed (i.e. the data has come back) before we start
* executing any following instructions.
*/
extern inline int in_8(volatile unsigned char __iomem *addr)
{
int ret;
__asm__ __volatile__(
"lbz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_8(volatile unsigned char __iomem *addr, int val)
{
__asm__ __volatile__("stb%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
}
extern inline int in_le16(volatile unsigned short __iomem *addr)
{
int ret;
__asm__ __volatile__("lhbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
extern inline int in_be16(volatile unsigned short __iomem *addr)
{
int ret;
__asm__ __volatile__("lhz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_le16(volatile unsigned short __iomem *addr, int val)
{
__asm__ __volatile__("sthbrx %1,0,%2; eieio" : "=m" (*addr) :
"r" (val), "r" (addr));
}
extern inline void out_be16(volatile unsigned short __iomem *addr, int val)
{
__asm__ __volatile__("sth%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
}
extern inline unsigned in_le32(volatile unsigned __iomem *addr)
{
unsigned ret;
__asm__ __volatile__("lwbrx %0,0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) :
"r" (addr), "m" (*addr));
return ret;
}
extern inline unsigned in_be32(volatile unsigned __iomem *addr)
{
unsigned ret;
__asm__ __volatile__("lwz%U1%X1 %0,%1;\n"
"twi 0,%0,0;\n"
"isync" : "=r" (ret) : "m" (*addr));
return ret;
}
extern inline void out_le32(volatile unsigned __iomem *addr, int val)
{
__asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) :
"r" (val), "r" (addr));
}
extern inline void out_be32(volatile unsigned __iomem *addr, int val)
{
__asm__ __volatile__("stw%U0%X0 %1,%0; eieio" : "=m" (*addr) : "r" (val));
}
static inline __u8 readb(volatile void __iomem *addr)
{
return in_8(addr);
}
static inline void writeb(__u8 b, volatile void __iomem *addr)
{
out_8(addr, b);
}
#if defined(CONFIG_APUS)
static inline __u16 readw(volatile void __iomem *addr)
{
return *(__force volatile __u16 *)(addr);
}
static inline __u32 readl(volatile void __iomem *addr)
{
return *(__force volatile __u32 *)(addr);
}
static inline void writew(__u16 b, volatile void __iomem *addr)
{
*(__force volatile __u16 *)(addr) = b;
}
static inline void writel(__u32 b, volatile void __iomem *addr)
{
*(__force volatile __u32 *)(addr) = b;
}
#else
static inline __u16 readw(volatile void __iomem *addr)
{
return in_le16(addr);
}
static inline __u32 readl(volatile void __iomem *addr)
{
return in_le32(addr);
}
static inline void writew(__u16 b, volatile void __iomem *addr)
{
out_le16(addr, b);
}
static inline void writel(__u32 b, volatile void __iomem *addr)
{
out_le32(addr, b);
}
#endif /* CONFIG_APUS */
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
static inline __u8 __raw_readb(volatile void __iomem *addr)
{
return *(__force volatile __u8 *)(addr);
}
static inline __u16 __raw_readw(volatile void __iomem *addr)
{
return *(__force volatile __u16 *)(addr);
}
static inline __u32 __raw_readl(volatile void __iomem *addr)
{
return *(__force volatile __u32 *)(addr);
}
static inline void __raw_writeb(__u8 b, volatile void __iomem *addr)
{
*(__force volatile __u8 *)(addr) = b;
}
static inline void __raw_writew(__u16 b, volatile void __iomem *addr)
{
*(__force volatile __u16 *)(addr) = b;
}
static inline void __raw_writel(__u32 b, volatile void __iomem *addr)
{
*(__force volatile __u32 *)(addr) = b;
}
#define mmiowb()
/*
* The insw/outsw/insl/outsl macros don't do byte-swapping.
* They are only used in practice for transferring buffers which
* are arrays of bytes, and byte-swapping is not appropriate in
* that case. - paulus
*/
#define insb(port, buf, ns) _insb((port)+___IO_BASE, (buf), (ns))
#define outsb(port, buf, ns) _outsb((port)+___IO_BASE, (buf), (ns))
#define insw(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
#define outsw(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
#define insl(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
#define outsl(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
/*
* On powermacs, we will get a machine check exception if we
* try to read data from a non-existent I/O port. Because the
* machine check is an asynchronous exception, it isn't
* well-defined which instruction SRR0 will point to when the
* exception occurs.
* With the sequence below (twi; isync; nop), we have found that
* the machine check occurs on one of the three instructions on
* all PPC implementations tested so far. The twi and isync are
* needed on the 601 (in fact twi; sync works too), the isync and
* nop are needed on 604[e|r], and any of twi, sync or isync will
* work on 603[e], 750, 74xx.
* The twi creates an explicit data dependency on the returned
* value which seems to be needed to make the 601 wait for the
* load to finish.
*/
#define __do_in_asm(name, op) \
extern __inline__ unsigned int name(unsigned int port) \
{ \
unsigned int x; \
__asm__ __volatile__( \
op " %0,0,%1\n" \
"1: twi 0,%0,0\n" \
"2: isync\n" \
"3: nop\n" \
"4:\n" \
".section .fixup,\"ax\"\n" \
"5: li %0,-1\n" \
" b 4b\n" \
".previous\n" \
".section __ex_table,\"a\"\n" \
" .align 2\n" \
" .long 1b,5b\n" \
" .long 2b,5b\n" \
" .long 3b,5b\n" \
".previous" \
: "=&r" (x) \
: "r" (port + ___IO_BASE)); \
return x; \
}
#define __do_out_asm(name, op) \
extern __inline__ void name(unsigned int val, unsigned int port) \
{ \
__asm__ __volatile__( \
op " %0,0,%1\n" \
"1: sync\n" \
"2:\n" \
".section __ex_table,\"a\"\n" \
" .align 2\n" \
" .long 1b,2b\n" \
".previous" \
: : "r" (val), "r" (port + ___IO_BASE)); \
}
__do_out_asm(outb, "stbx")
#ifdef CONFIG_APUS
__do_in_asm(inb, "lbzx")
__do_in_asm(inw, "lhz%U1%X1")
__do_in_asm(inl, "lwz%U1%X1")
__do_out_asm(outl,"stw%U0%X0")
__do_out_asm(outw, "sth%U0%X0")
#elif defined (CONFIG_8260_PCI9)
/* in asm cannot be defined if PCI9 workaround is used */
#define inb(port) in_8((port)+___IO_BASE)
#define inw(port) in_le16((port)+___IO_BASE)
#define inl(port) in_le32((port)+___IO_BASE)
__do_out_asm(outw, "sthbrx")
__do_out_asm(outl, "stwbrx")
#else
__do_in_asm(inb, "lbzx")
__do_in_asm(inw, "lhbrx")
__do_in_asm(inl, "lwbrx")
__do_out_asm(outw, "sthbrx")
__do_out_asm(outl, "stwbrx")
#endif
#define inb_p(port) inb((port))
#define outb_p(val, port) outb((val), (port))
#define inw_p(port) inw((port))
#define outw_p(val, port) outw((val), (port))
#define inl_p(port) inl((port))
#define outl_p(val, port) outl((val), (port))
extern void _insb(volatile u8 __iomem *port, void *buf, int ns);
extern void _outsb(volatile u8 __iomem *port, const void *buf, int ns);
extern void _insw(volatile u16 __iomem *port, void *buf, int ns);
extern void _outsw(volatile u16 __iomem *port, const void *buf, int ns);
extern void _insl(volatile u32 __iomem *port, void *buf, int nl);
extern void _outsl(volatile u32 __iomem *port, const void *buf, int nl);
extern void _insw_ns(volatile u16 __iomem *port, void *buf, int ns);
extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
/*
* The *_ns versions below don't do byte-swapping.
* Neither do the standard versions now, these are just here
* for older code.
*/
#define insw_ns(port, buf, ns) _insw_ns((port)+___IO_BASE, (buf), (ns))
#define outsw_ns(port, buf, ns) _outsw_ns((port)+___IO_BASE, (buf), (ns))
#define insl_ns(port, buf, nl) _insl_ns((port)+___IO_BASE, (buf), (nl))
#define outsl_ns(port, buf, nl) _outsl_ns((port)+___IO_BASE, (buf), (nl))
#define IO_SPACE_LIMIT ~0
static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
{
memset((void __force *)addr, val, count);
}
static inline void memcpy_fromio(void *dst, volatile void __iomem *src, int count)
{
memcpy(dst, (void __force *) src, count);
}
static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
{
memcpy((void __force *) dst, src, count);
}
/*
* Map in an area of physical address space, for accessing
* I/O devices etc.
*/
extern void __iomem *__ioremap(phys_addr_t address, unsigned long size,
unsigned long flags);
extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
#ifdef CONFIG_44x
extern void __iomem *ioremap64(unsigned long long address, unsigned long size);
#endif
#define ioremap_nocache(addr, size) ioremap((addr), (size))
extern void iounmap(volatile void __iomem *addr);
extern unsigned long iopa(unsigned long addr);
extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
unsigned int size, int flags);
/*
* The PCI bus is inherently Little-Endian. The PowerPC is being
* run Big-Endian. Thus all values which cross the [PCI] barrier
* must be endian-adjusted. Also, the local DRAM has a different
* address from the PCI point of view, thus buffer addresses also
* have to be modified [mapped] appropriately.
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
#ifndef CONFIG_APUS
if (address == (void *)0)
return 0;
return (unsigned long)address - KERNELBASE + PCI_DRAM_OFFSET;
#else
return iopa ((unsigned long) address);
#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
#ifndef CONFIG_APUS
if (address == 0)
return NULL;
return (void *)(address - PCI_DRAM_OFFSET + KERNELBASE);
#else
return (void*) mm_ptov (address);
#endif
}
/*
* Change virtual addresses to physical addresses and vv, for
* addresses in the area where the kernel has the RAM mapped.
*/
extern inline unsigned long virt_to_phys(volatile void * address)
{
#ifndef CONFIG_APUS
return (unsigned long) address - KERNELBASE;
#else
return iopa ((unsigned long) address);
#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
#ifndef CONFIG_APUS
return (void *) (address + KERNELBASE);
#else
return (void*) mm_ptov (address);
#endif
}
/*
* Change "struct page" to physical address.
*/
#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
/*
* Enforce In-order Execution of I/O:
* Acts as a barrier to ensure all previous I/O accesses have
* completed before any further ones are issued.
*/
extern inline void eieio(void)
{
__asm__ __volatile__ ("eieio" : : : "memory");
}
/* Enforce in-order execution of data I/O.
* No distinction between read/write on PPC; use eieio for all three.
*/
#define iobarrier_rw() eieio()
#define iobarrier_r() eieio()
#define iobarrier_w() eieio()
static inline int check_signature(volatile void __iomem * io_addr,
const unsigned char *signature, int length)
{
int retval = 0;
do {
if (readb(io_addr) != *signature)
goto out;
io_addr++;
signature++;
length--;
} while (length);
retval = 1;
out:
return retval;
}
/*
* Here comes the ppc implementation of the IOMAP
* interfaces.
*/
static inline unsigned int ioread8(void __iomem *addr)
{
return readb(addr);
}
static inline unsigned int ioread16(void __iomem *addr)
{
return readw(addr);
}
static inline unsigned int ioread32(void __iomem *addr)
{
return readl(addr);
}
static inline void iowrite8(u8 val, void __iomem *addr)
{
writeb(val, addr);
}
static inline void iowrite16(u16 val, void __iomem *addr)
{
writew(val, addr);
}
static inline void iowrite32(u32 val, void __iomem *addr)
{
writel(val, addr);
}
static inline void ioread8_rep(void __iomem *addr, void *dst, unsigned long count)
{
_insb((u8 __force *) addr, dst, count);
}
static inline void ioread16_rep(void __iomem *addr, void *dst, unsigned long count)
{
_insw_ns((u16 __force *) addr, dst, count);
}
static inline void ioread32_rep(void __iomem *addr, void *dst, unsigned long count)
{
_insl_ns((u32 __force *) addr, dst, count);
}
static inline void iowrite8_rep(void __iomem *addr, const void *src, unsigned long count)
{
_outsb((u8 __force *) addr, src, count);
}
static inline void iowrite16_rep(void __iomem *addr, const void *src, unsigned long count)
{
_outsw_ns((u16 __force *) addr, src, count);
}
static inline void iowrite32_rep(void __iomem *addr, const void *src, unsigned long count)
{
_outsl_ns((u32 __force *) addr, src, count);
}
/* Create a virtual mapping cookie for an IO port range */
extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
extern void ioport_unmap(void __iomem *);
/* Create a virtual mapping cookie for a PCI BAR (memory or IO) */
struct pci_dev;
extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
extern void pci_iounmap(struct pci_dev *dev, void __iomem *);
#endif /* _PPC_IO_H */
#ifdef CONFIG_8260_PCI9
#include <asm/mpc8260_pci9.h>
#endif
#endif /* __KERNEL__ */

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#ifndef _PPC_IOCTL_H
#define _PPC_IOCTL_H
/*
* this was copied from the alpha as it's a bit cleaner there.
* -- Cort
*/
#define _IOC_NRBITS 8
#define _IOC_TYPEBITS 8
#define _IOC_SIZEBITS 13
#define _IOC_DIRBITS 3
#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
#define _IOC_NRSHIFT 0
#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
/*
* Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
* And this turns out useful to catch old ioctl numbers in header
* files for us.
*/
#define _IOC_NONE 1U
#define _IOC_READ 2U
#define _IOC_WRITE 4U
#define _IOC(dir,type,nr,size) \
(((dir) << _IOC_DIRSHIFT) | \
((type) << _IOC_TYPESHIFT) | \
((nr) << _IOC_NRSHIFT) | \
((size) << _IOC_SIZESHIFT))
/* provoke compile error for invalid uses of size argument */
extern unsigned int __invalid_size_argument_for_IOC;
#define _IOC_TYPECHECK(t) \
((sizeof(t) == sizeof(t[1]) && \
sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
sizeof(t) : __invalid_size_argument_for_IOC)
/* used to create numbers */
#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0)
#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),(_IOC_TYPECHECK(size)))
#define _IOR_BAD(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size))
#define _IOW_BAD(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size))
#define _IOWR_BAD(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size))
/* used to decode them.. */
#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
/* various drivers, such as the pcmcia stuff, need these... */
#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
#endif

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#ifndef _ASM_PPC_IOCTLS_H
#define _ASM_PPC_IOCTLS_H
#include <asm/ioctl.h>
#define FIOCLEX _IO('f', 1)
#define FIONCLEX _IO('f', 2)
#define FIOASYNC _IOW('f', 125, int)
#define FIONBIO _IOW('f', 126, int)
#define FIONREAD _IOR('f', 127, int)
#define TIOCINQ FIONREAD
#define FIOQSIZE _IOR('f', 128, loff_t)
#define TIOCGETP _IOR('t', 8, struct sgttyb)
#define TIOCSETP _IOW('t', 9, struct sgttyb)
#define TIOCSETN _IOW('t', 10, struct sgttyb) /* TIOCSETP wo flush */
#define TIOCSETC _IOW('t', 17, struct tchars)
#define TIOCGETC _IOR('t', 18, struct tchars)
#define TCGETS _IOR('t', 19, struct termios)
#define TCSETS _IOW('t', 20, struct termios)
#define TCSETSW _IOW('t', 21, struct termios)
#define TCSETSF _IOW('t', 22, struct termios)
#define TCGETA _IOR('t', 23, struct termio)
#define TCSETA _IOW('t', 24, struct termio)
#define TCSETAW _IOW('t', 25, struct termio)
#define TCSETAF _IOW('t', 28, struct termio)
#define TCSBRK _IO('t', 29)
#define TCXONC _IO('t', 30)
#define TCFLSH _IO('t', 31)
#define TIOCSWINSZ _IOW('t', 103, struct winsize)
#define TIOCGWINSZ _IOR('t', 104, struct winsize)
#define TIOCSTART _IO('t', 110) /* start output, like ^Q */
#define TIOCSTOP _IO('t', 111) /* stop output, like ^S */
#define TIOCOUTQ _IOR('t', 115, int) /* output queue size */
#define TIOCGLTC _IOR('t', 116, struct ltchars)
#define TIOCSLTC _IOW('t', 117, struct ltchars)
#define TIOCSPGRP _IOW('t', 118, int)
#define TIOCGPGRP _IOR('t', 119, int)
#define TIOCEXCL 0x540C
#define TIOCNXCL 0x540D
#define TIOCSCTTY 0x540E
#define TIOCSTI 0x5412
#define TIOCMGET 0x5415
#define TIOCMBIS 0x5416
#define TIOCMBIC 0x5417
#define TIOCMSET 0x5418
# define TIOCM_LE 0x001
# define TIOCM_DTR 0x002
# define TIOCM_RTS 0x004
# define TIOCM_ST 0x008
# define TIOCM_SR 0x010
# define TIOCM_CTS 0x020
# define TIOCM_CAR 0x040
# define TIOCM_RNG 0x080
# define TIOCM_DSR 0x100
# define TIOCM_CD TIOCM_CAR
# define TIOCM_RI TIOCM_RNG
#define TIOCGSOFTCAR 0x5419
#define TIOCSSOFTCAR 0x541A
#define TIOCLINUX 0x541C
#define TIOCCONS 0x541D
#define TIOCGSERIAL 0x541E
#define TIOCSSERIAL 0x541F
#define TIOCPKT 0x5420
# define TIOCPKT_DATA 0
# define TIOCPKT_FLUSHREAD 1
# define TIOCPKT_FLUSHWRITE 2
# define TIOCPKT_STOP 4
# define TIOCPKT_START 8
# define TIOCPKT_NOSTOP 16
# define TIOCPKT_DOSTOP 32
#define TIOCNOTTY 0x5422
#define TIOCSETD 0x5423
#define TIOCGETD 0x5424
#define TCSBRKP 0x5425 /* Needed for POSIX tcsendbreak() */
#define TIOCSBRK 0x5427 /* BSD compatibility */
#define TIOCCBRK 0x5428 /* BSD compatibility */
#define TIOCGSID 0x5429 /* Return the session ID of FD */
#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */
#define TIOCSERCONFIG 0x5453
#define TIOCSERGWILD 0x5454
#define TIOCSERSWILD 0x5455
#define TIOCGLCKTRMIOS 0x5456
#define TIOCSLCKTRMIOS 0x5457
#define TIOCSERGSTRUCT 0x5458 /* For debugging only */
#define TIOCSERGETLSR 0x5459 /* Get line status register */
/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */
#define TIOCSERGETMULTI 0x545A /* Get multiport config */
#define TIOCSERSETMULTI 0x545B /* Set multiport config */
#define TIOCMIWAIT 0x545C /* wait for a change on serial input line(s) */
#define TIOCGICOUNT 0x545D /* read serial port inline interrupt counts */
#endif /* _ASM_PPC_IOCTLS_H */

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#ifndef __PPC_IPC_H__
#define __PPC_IPC_H__
/*
* These are used to wrap system calls on PowerPC.
*
* See arch/ppc/kernel/syscalls.c for ugly details..
*/
struct ipc_kludge {
struct msgbuf __user *msgp;
long msgtyp;
};
#define SEMOP 1
#define SEMGET 2
#define SEMCTL 3
#define SEMTIMEDOP 4
#define MSGSND 11
#define MSGRCV 12
#define MSGGET 13
#define MSGCTL 14
#define SHMAT 21
#define SHMDT 22
#define SHMGET 23
#define SHMCTL 24
#define IPCCALL(version,op) ((version)<<16 | (op))
#endif /* __PPC_IPC_H__ */

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#ifndef __PPC_IPCBUF_H__
#define __PPC_IPCBUF_H__
/*
* The ipc64_perm structure for PPC architecture.
* Note extra padding because this structure is passed back and forth
* between kernel and user space.
*
* Pad space is left for:
* - 1 32-bit value to fill up for 8-byte alignment
* - 2 miscellaneous 64-bit values (so that this structure matches
* PPC64 ipc64_perm)
*/
struct ipc64_perm
{
__kernel_key_t key;
__kernel_uid_t uid;
__kernel_gid_t gid;
__kernel_uid_t cuid;
__kernel_gid_t cgid;
__kernel_mode_t mode;
unsigned long seq;
unsigned int __pad2;
unsigned long long __unused1;
unsigned long long __unused2;
};
#endif /* __PPC_IPCBUF_H__ */

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#ifdef __KERNEL__
#ifndef _ASM_IRQ_H
#define _ASM_IRQ_H
#include <linux/config.h>
#include <asm/machdep.h> /* ppc_md */
#include <asm/atomic.h>
/*
* These constants are used for passing information about interrupt
* signal polarity and level/edge sensing to the low-level PIC chip
* drivers.
*/
#define IRQ_SENSE_MASK 0x1
#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
#define IRQ_POLARITY_MASK 0x2
#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
#if defined(CONFIG_40x)
#include <asm/ibm4xx.h>
#ifndef NR_BOARD_IRQS
#define NR_BOARD_IRQS 0
#endif
#ifndef UIC_WIDTH /* Number of interrupts per device */
#define UIC_WIDTH 32
#endif
#ifndef NR_UICS /* number of UIC devices */
#define NR_UICS 1
#endif
#if defined (CONFIG_403)
/*
* The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
* 32 possible interrupts, a majority of which are not implemented on
* all cores. There are six configurable, external interrupt pins and
* there are eight internal interrupts for the on-chip serial port
* (SPU), DMA controller, and JTAG controller.
*
*/
#define NR_AIC_IRQS 32
#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
#elif !defined (CONFIG_403)
/*
* The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
* possible interrupts as well. There are seven, configurable external
* interrupt pins and there are 17 internal interrupts for the on-chip
* serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
*
*/
#define NR_UIC_IRQS UIC_WIDTH
#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
#endif
static __inline__ int
irq_canonicalize(int irq)
{
return (irq);
}
#elif defined(CONFIG_44x)
#include <asm/ibm44x.h>
#define NR_UIC_IRQS 32
#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
static __inline__ int
irq_canonicalize(int irq)
{
return (irq);
}
#elif defined(CONFIG_8xx)
/* Now include the board configuration specific associations.
*/
#include <asm/mpc8xx.h>
/* The MPC8xx cores have 16 possible interrupts. There are eight
* possible level sensitive interrupts assigned and generated internally
* from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
* There are eight external interrupts (IRQs) that can be configured
* as either level or edge sensitive.
*
* On some implementations, there is also the possibility of an 8259
* through the PCI and PCI-ISA bridges.
*
* We are "flattening" the interrupt vectors of the cascaded CPM
* and 8259 interrupt controllers so that we can uniquely identify
* any interrupt source with a single integer.
*/
#define NR_SIU_INTS 16
#define NR_CPM_INTS 32
#ifndef NR_8259_INTS
#define NR_8259_INTS 0
#endif
#define SIU_IRQ_OFFSET 0
#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
/* These values must be zero-based and map 1:1 with the SIU configuration.
* They are used throughout the 8xx I/O subsystem to generate
* interrupt masks, flags, and other control patterns. This is why the
* current kernel assumption of the 8259 as the base controller is such
* a pain in the butt.
*/
#define SIU_IRQ0 (0) /* Highest priority */
#define SIU_LEVEL0 (1)
#define SIU_IRQ1 (2)
#define SIU_LEVEL1 (3)
#define SIU_IRQ2 (4)
#define SIU_LEVEL2 (5)
#define SIU_IRQ3 (6)
#define SIU_LEVEL3 (7)
#define SIU_IRQ4 (8)
#define SIU_LEVEL4 (9)
#define SIU_IRQ5 (10)
#define SIU_LEVEL5 (11)
#define SIU_IRQ6 (12)
#define SIU_LEVEL6 (13)
#define SIU_IRQ7 (14)
#define SIU_LEVEL7 (15)
/* The internal interrupts we can configure as we see fit.
* My personal preference is CPM at level 2, which puts it above the
* MBX PCI/ISA/IDE interrupts.
*/
#ifndef PIT_INTERRUPT
#define PIT_INTERRUPT SIU_LEVEL0
#endif
#ifndef CPM_INTERRUPT
#define CPM_INTERRUPT SIU_LEVEL2
#endif
#ifndef PCMCIA_INTERRUPT
#define PCMCIA_INTERRUPT SIU_LEVEL6
#endif
#ifndef DEC_INTERRUPT
#define DEC_INTERRUPT SIU_LEVEL7
#endif
/* Some internal interrupt registers use an 8-bit mask for the interrupt
* level instead of a number.
*/
#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
/* always the same on 8xx -- Cort */
static __inline__ int irq_canonicalize(int irq)
{
return irq;
}
#elif defined(CONFIG_CPM2) && defined(CONFIG_85xx)
/* Now include the board configuration specific associations.
*/
#include <asm/mpc85xx.h>
/* The MPC8560 openpic has 32 internal interrupts and 12 external
* interrupts.
*
* We are "flattening" the interrupt vectors of the cascaded CPM
* so that we can uniquely identify any interrupt source with a
* single integer.
*/
#define NR_CPM_INTS 64
#define NR_EPIC_INTS 44
#ifndef NR_8259_INTS
#define NR_8259_INTS 0
#endif
#define NUM_8259_INTERRUPTS NR_8259_INTS
#ifndef CPM_IRQ_OFFSET
#define CPM_IRQ_OFFSET 0
#endif
#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
/* These values must be zero-based and map 1:1 with the EPIC configuration.
* They are used throughout the 8560 I/O subsystem to generate
* interrupt masks, flags, and other control patterns. This is why the
* current kernel assumption of the 8259 as the base controller is such
* a pain in the butt.
*/
#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
static __inline__ int irq_canonicalize(int irq)
{
return irq;
}
#else /* CONFIG_40x + CONFIG_8xx */
/*
* this is the # irq's for all ppc arch's (pmac/chrp/prep)
* so it is the max of them all
*/
#define NR_IRQS 256
#ifndef CONFIG_8260
#define NUM_8259_INTERRUPTS 16
#else /* CONFIG_8260 */
/* The 8260 has an internal interrupt controller with a maximum of
* 64 IRQs. We will use NR_IRQs from above since it is large enough.
* Don't be confused by the 8260 documentation where they list an
* "interrupt number" and "interrupt vector". We are only interested
* in the interrupt vector. There are "reserved" holes where the
* vector number increases, but the interrupt number in the table does not.
* (Document errata updates have fixed this...make sure you have up to
* date processor documentation -- Dan).
*/
#define NR_SIU_INTS 64
#define SIU_INT_ERROR ((uint)0x00)
#define SIU_INT_I2C ((uint)0x01)
#define SIU_INT_SPI ((uint)0x02)
#define SIU_INT_RISC ((uint)0x03)
#define SIU_INT_SMC1 ((uint)0x04)
#define SIU_INT_SMC2 ((uint)0x05)
#define SIU_INT_IDMA1 ((uint)0x06)
#define SIU_INT_IDMA2 ((uint)0x07)
#define SIU_INT_IDMA3 ((uint)0x08)
#define SIU_INT_IDMA4 ((uint)0x09)
#define SIU_INT_SDMA ((uint)0x0a)
#define SIU_INT_TIMER1 ((uint)0x0c)
#define SIU_INT_TIMER2 ((uint)0x0d)
#define SIU_INT_TIMER3 ((uint)0x0e)
#define SIU_INT_TIMER4 ((uint)0x0f)
#define SIU_INT_TMCNT ((uint)0x10)
#define SIU_INT_PIT ((uint)0x11)
#define SIU_INT_IRQ1 ((uint)0x13)
#define SIU_INT_IRQ2 ((uint)0x14)
#define SIU_INT_IRQ3 ((uint)0x15)
#define SIU_INT_IRQ4 ((uint)0x16)
#define SIU_INT_IRQ5 ((uint)0x17)
#define SIU_INT_IRQ6 ((uint)0x18)
#define SIU_INT_IRQ7 ((uint)0x19)
#define SIU_INT_FCC1 ((uint)0x20)
#define SIU_INT_FCC2 ((uint)0x21)
#define SIU_INT_FCC3 ((uint)0x22)
#define SIU_INT_MCC1 ((uint)0x24)
#define SIU_INT_MCC2 ((uint)0x25)
#define SIU_INT_SCC1 ((uint)0x28)
#define SIU_INT_SCC2 ((uint)0x29)
#define SIU_INT_SCC3 ((uint)0x2a)
#define SIU_INT_SCC4 ((uint)0x2b)
#define SIU_INT_PC15 ((uint)0x30)
#define SIU_INT_PC14 ((uint)0x31)
#define SIU_INT_PC13 ((uint)0x32)
#define SIU_INT_PC12 ((uint)0x33)
#define SIU_INT_PC11 ((uint)0x34)
#define SIU_INT_PC10 ((uint)0x35)
#define SIU_INT_PC9 ((uint)0x36)
#define SIU_INT_PC8 ((uint)0x37)
#define SIU_INT_PC7 ((uint)0x38)
#define SIU_INT_PC6 ((uint)0x39)
#define SIU_INT_PC5 ((uint)0x3a)
#define SIU_INT_PC4 ((uint)0x3b)
#define SIU_INT_PC3 ((uint)0x3c)
#define SIU_INT_PC2 ((uint)0x3d)
#define SIU_INT_PC1 ((uint)0x3e)
#define SIU_INT_PC0 ((uint)0x3f)
#endif /* CONFIG_8260 */
/*
* This gets called from serial.c, which is now used on
* powermacs as well as prep/chrp boxes.
* Prep and chrp both have cascaded 8259 PICs.
*/
static __inline__ int irq_canonicalize(int irq)
{
if (ppc_md.irq_canonicalize)
return ppc_md.irq_canonicalize(irq);
return irq;
}
#endif
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
/* pedantic: these are long because they are used with set_bit --RR */
extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
extern atomic_t ppc_n_lost_interrupts;
struct irqaction;
struct pt_regs;
int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *);
#endif /* _ASM_IRQ_H */
#endif /* __KERNEL__ */

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extra/linux-2.6.10/include/asm-ppc/keylargo.h Normal file
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/*
* keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
*
*/
/* "Pangea" chipset has keylargo device-id 0x25 while core99
* has device-id 0x22. The rev. of the pangea one is 0, so we
* fake an artificial rev. in keylargo_rev by oring 0x100
*/
#define KL_PANGEA_REV 0x100
/* offset from base for feature control registers */
#define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
#define KEYLARGO_FCR0 0x38
#define KEYLARGO_FCR1 0x3c
#define KEYLARGO_FCR2 0x40
#define KEYLARGO_FCR3 0x44
#define KEYLARGO_FCR4 0x48
#define KEYLARGO_FCR5 0x4c /* Pangea only */
/* K2 aditional FCRs */
#define K2_FCR6 0x34
#define K2_FCR7 0x30
#define K2_FCR8 0x2c
#define K2_FCR9 0x28
#define K2_FCR10 0x24
/* GPIO registers */
#define KEYLARGO_GPIO_LEVELS0 0x50
#define KEYLARGO_GPIO_LEVELS1 0x54
#define KEYLARGO_GPIO_EXTINT_0 0x58
#define KEYLARGO_GPIO_EXTINT_CNT 18
#define KEYLARGO_GPIO_0 0x6A
#define KEYLARGO_GPIO_CNT 17
#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE 0x80
#define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04
#define KEYLARGO_GPIO_OUTOUT_DATA 0x01
#define KEYLARGO_GPIO_INPUT_DATA 0x02
/* K2 does only extint GPIOs and does 51 of them */
#define K2_GPIO_EXTINT_0 0x58
#define K2_GPIO_EXTINT_CNT 51
/* Specific GPIO regs */
#define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03)
#define KL_GPIO_MODEM_POWER (KEYLARGO_GPIO_0+0x02) /* Pangea */
#define KL_GPIO_SOUND_POWER (KEYLARGO_GPIO_0+0x05)
/* Hrm... this one is only to be used on Pismo. It seeem to also
* control the timebase enable on other machines. Still to be
* experimented... --BenH.
*/
#define KL_GPIO_FW_CABLE_POWER (KEYLARGO_GPIO_0+0x09)
#define KL_GPIO_TB_ENABLE (KEYLARGO_GPIO_0+0x09)
#define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10)
#define KL_GPIO_EXTINT_CPU1 (KEYLARGO_GPIO_0+0x0a)
#define KL_GPIO_EXTINT_CPU1_ASSERT 0x04
#define KL_GPIO_EXTINT_CPU1_RELEASE 0x38
#define KL_GPIO_RESET_CPU0 (KEYLARGO_GPIO_EXTINT_0+0x03)
#define KL_GPIO_RESET_CPU1 (KEYLARGO_GPIO_EXTINT_0+0x04)
#define KL_GPIO_RESET_CPU2 (KEYLARGO_GPIO_EXTINT_0+0x0f)
#define KL_GPIO_RESET_CPU3 (KEYLARGO_GPIO_EXTINT_0+0x10)
#define KL_GPIO_PMU_MESSAGE_IRQ (KEYLARGO_GPIO_EXTINT_0+0x09)
#define KL_GPIO_PMU_MESSAGE_BIT KEYLARGO_GPIO_INPUT_DATA
#define KL_GPIO_MEDIABAY_IRQ (KEYLARGO_GPIO_EXTINT_0+0x0e)
#define KL_GPIO_AIRPORT_0 (KEYLARGO_GPIO_EXTINT_0+0x0a)
#define KL_GPIO_AIRPORT_1 (KEYLARGO_GPIO_EXTINT_0+0x0d)
#define KL_GPIO_AIRPORT_2 (KEYLARGO_GPIO_0+0x0d)
#define KL_GPIO_AIRPORT_3 (KEYLARGO_GPIO_0+0x0e)
#define KL_GPIO_AIRPORT_4 (KEYLARGO_GPIO_0+0x0f)
/*
* Bits in feature control register. Those bits different for K2 are
* listed separately
*/
#define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */
#define KL_MBCR_MB0_IDE_ENABLE 0x00001000
#define KL_MBCR_MB0_FLOPPY_ENABLE 0x00002000 /* exist ? */
#define KL_MBCR_MB0_SOUND_ENABLE 0x00004000 /* hrm... */
#define KL_MBCR_MB0_DEV_MASK 0x00007800
#define KL_MBCR_MB0_DEV_POWER 0x00000400
#define KL_MBCR_MB0_DEV_RESET 0x00000200
#define KL_MBCR_MB0_ENABLE 0x00000100
#define KL_MBCR_MB1_PCI_ENABLE 0x08000000 /* exist ? */
#define KL_MBCR_MB1_IDE_ENABLE 0x10000000
#define KL_MBCR_MB1_FLOPPY_ENABLE 0x20000000 /* exist ? */
#define KL_MBCR_MB1_SOUND_ENABLE 0x40000000 /* hrm... */
#define KL_MBCR_MB1_DEV_MASK 0x78000000
#define KL_MBCR_MB1_DEV_POWER 0x04000000
#define KL_MBCR_MB1_DEV_RESET 0x02000000
#define KL_MBCR_MB1_ENABLE 0x01000000
#define KL0_SCC_B_INTF_ENABLE 0x00000001 /* (KL Only) */
#define KL0_SCC_A_INTF_ENABLE 0x00000002
#define KL0_SCC_SLOWPCLK 0x00000004
#define KL0_SCC_RESET 0x00000008
#define KL0_SCCA_ENABLE 0x00000010
#define KL0_SCCB_ENABLE 0x00000020
#define KL0_SCC_CELL_ENABLE 0x00000040
#define KL0_IRDA_HIGH_BAND 0x00000100 /* (KL Only) */
#define KL0_IRDA_SOURCE2_SEL 0x00000200 /* (KL Only) */
#define KL0_IRDA_SOURCE1_SEL 0x00000400 /* (KL Only) */
#define KL0_PG_USB0_PMI_ENABLE 0x00000400 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_RESET 0x00000800 /* (KL Only) */
#define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_DEFAULT1 0x00001000 /* (KL Only) */
#define KL0_PG_USB0_REF_SUSPEND 0x00001000 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_DEFAULT0 0x00002000 /* (KL Only) */
#define KL0_PG_USB0_PAD_SUSPEND 0x00002000 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_FAST_CONNECT 0x00004000 /* (KL Only) */
#define KL0_PG_USB1_PMI_ENABLE 0x00004000 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_ENABLE 0x00008000 /* (KL Only) */
#define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_CLK32_ENABLE 0x00010000 /* (KL Only) */
#define KL0_PG_USB1_REF_SUSPEND 0x00010000 /* (Pangea/Intrepid Only) */
#define KL0_IRDA_CLK19_ENABLE 0x00020000 /* (KL Only) */
#define KL0_PG_USB1_PAD_SUSPEND 0x00020000 /* (Pangea/Intrepid Only) */
#define KL0_USB0_PAD_SUSPEND0 0x00040000
#define KL0_USB0_PAD_SUSPEND1 0x00080000
#define KL0_USB0_CELL_ENABLE 0x00100000
#define KL0_USB1_PAD_SUSPEND0 0x00400000
#define KL0_USB1_PAD_SUSPEND1 0x00800000
#define KL0_USB1_CELL_ENABLE 0x01000000
#define KL0_USB_REF_SUSPEND 0x10000000 /* (KL Only) */
#define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \
KL0_SCC_SLOWPCLK | \
KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
#define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */
#define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */
#define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */
#define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */
#define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */
#define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */
#define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */
#define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */
#define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */
#define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */
#define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */
#define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */
#define KL1_I2S0_CHOOSE 0x00000200 /* KL Only */
#define KL1_I2S0_CELL_ENABLE 0x00000400
#define KL1_I2S0_CLK_ENABLE_BIT 0x00001000
#define KL1_I2S0_ENABLE 0x00002000
#define KL1_I2S1_CELL_ENABLE 0x00020000
#define KL1_I2S1_CLK_ENABLE_BIT 0x00080000
#define KL1_I2S1_ENABLE 0x00100000
#define KL1_EIDE0_ENABLE 0x00800000 /* KL/Intrepid Only */
#define KL1_EIDE0_RESET_N 0x01000000 /* KL/Intrepid Only */
#define KL1_EIDE1_ENABLE 0x04000000 /* KL Only */
#define KL1_EIDE1_RESET_N 0x08000000 /* KL Only */
#define KL1_UIDE_ENABLE 0x20000000 /* KL/Pangea Only */
#define KL1_UIDE_RESET_N 0x40000000 /* KL/Pangea Only */
#define KL2_IOBUS_ENABLE 0x00000002
#define KL2_SLEEP_STATE_BIT 0x00000100 /* KL Only */
#define KL2_PG_STOP_ALL_CLOCKS 0x00000100 /* Pangea Only */
#define KL2_MPIC_ENABLE 0x00020000
#define KL2_CARDSLOT_RESET 0x00040000 /* Pangea/Intrepid Only */
#define KL2_ALT_DATA_OUT 0x02000000 /* KL Only ??? */
#define KL2_MEM_IS_BIG 0x04000000
#define KL2_CARDSEL_16 0x08000000
#define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */
#define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */
#define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */
#define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */
#define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */
#define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */
#define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */
#define KL3_SHUTDOWN_PLLKW12 0x00000010 /* KL Only */
#define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */
#define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */
#define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */
#define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */
#define KL3_SHUTDOWN_PLL2X 0x00000080 /* KL Only */
#define KL3_CLK66_ENABLE 0x00000100 /* KL Only */
#define KL3_CLK49_ENABLE 0x00000200
#define KL3_CLK45_ENABLE 0x00000400
#define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */
#define KL3_TIMER_CLK18_ENABLE 0x00001000
#define KL3_I2S1_CLK18_ENABLE 0x00002000
#define KL3_I2S0_CLK18_ENABLE 0x00004000
#define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */
#define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */
#define KL3_STOPPING33_ENABLED 0x00080000 /* KL Only */
#define KL3_PG_PLL_ENABLE_TEST 0x00080000 /* Pangea Only */
/* Intrepid USB bus 2, port 0,1 */
#define KL3_IT_PORT_WAKEUP_ENABLE(p) (0x00080000 << ((p)<<3))
#define KL3_IT_PORT_RESUME_WAKE_EN(p) (0x00040000 << ((p)<<3))
#define KL3_IT_PORT_CONNECT_WAKE_EN(p) (0x00020000 << ((p)<<3))
#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p) (0x00010000 << ((p)<<3))
#define KL3_IT_PORT_RESUME_STAT(p) (0x00300000 << ((p)<<3))
#define KL3_IT_PORT_CONNECT_STAT(p) (0x00200000 << ((p)<<3))
#define KL3_IT_PORT_DISCONNECT_STAT(p) (0x00100000 << ((p)<<3))
/* Port 0,1 : bus 0, port 2,3 : bus 1 */
#define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3))
#define KL4_PORT_RESUME_WAKE_EN(p) (0x00000004 << ((p)<<3))
#define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3))
#define KL4_PORT_DISCONNECT_WAKE_EN(p) (0x00000001 << ((p)<<3))
#define KL4_PORT_RESUME_STAT(p) (0x00000040 << ((p)<<3))
#define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3))
#define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3))
/* Pangea and Intrepid only */
#define KL5_VIA_USE_CLK31 0000000001 /* Pangea Only */
#define KL5_SCC_USE_CLK31 0x00000002 /* Pangea Only */
#define KL5_PWM_CLK32_EN 0x00000004
#define KL5_CLK3_68_EN 0x00000010
#define KL5_CLK32_EN 0x00000020
/* K2 definitions */
#define K2_FCR0_USB0_SWRESET 0x00200000
#define K2_FCR0_USB1_SWRESET 0x02000000
#define K2_FCR0_RING_PME_DISABLE 0x08000000
#define K2_FCR1_PCI1_BUS_RESET_N 0x00000010
#define K2_FCR1_PCI1_SLEEP_RESET_EN 0x00000020
#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000
#define K2_FCR1_FW_CLK_ENABLE 0x00008000
#define K2_FCR1_FW_RESET_N 0x00010000
#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000
#define K2_FCR1_GMAC_POWER_DOWN 0x00800000
#define K2_FCR1_GMAC_RESET_N 0x01000000
#define K2_FCR1_SATA_CLK_ENABLE 0x02000000
#define K2_FCR1_SATA_POWER_DOWN 0x04000000
#define K2_FCR1_SATA_RESET_N 0x08000000
#define K2_FCR1_UATA_CLK_ENABLE 0x10000000
#define K2_FCR1_UATA_RESET_N 0x40000000
#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000

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/*
* kgdb.h: Defines and declarations for serial line source level
* remote debugging of the Linux kernel using gdb.
*
* PPC Mods (C) 1998 Michael Tesch (tesch@cs.wisc.edu)
*
* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
*/
#ifdef __KERNEL__
#ifndef _PPC_KGDB_H
#define _PPC_KGDB_H
#ifndef __ASSEMBLY__
/* Things specific to the gen550 backend. */
struct uart_port;
extern void gen550_progress(char *, unsigned short);
extern void gen550_kgdb_map_scc(void);
extern void gen550_init(int, struct uart_port *);
/* Things specific to the pmac backend. */
extern void zs_kgdb_hook(int tty_num);
/* To init the kgdb engine. (called by serial hook)*/
extern void set_debug_traps(void);
/* To enter the debugger explicitly. */
extern void breakpoint(void);
/* For taking exceptions
* these are defined in traps.c
*/
extern void (*debugger)(struct pt_regs *regs);
extern int (*debugger_bpt)(struct pt_regs *regs);
extern int (*debugger_sstep)(struct pt_regs *regs);
extern int (*debugger_iabr_match)(struct pt_regs *regs);
extern int (*debugger_dabr_match)(struct pt_regs *regs);
extern void (*debugger_fault_handler)(struct pt_regs *regs);
/* What we bring to the party */
int kgdb_bpt(struct pt_regs *regs);
int kgdb_sstep(struct pt_regs *regs);
void kgdb(struct pt_regs *regs);
int kgdb_iabr_match(struct pt_regs *regs);
int kgdb_dabr_match(struct pt_regs *regs);
/*
* external low-level support routines (ie macserial.c)
*/
extern void kgdb_interruptible(int); /* control interrupts from serial */
extern void putDebugChar(char); /* write a single character */
extern char getDebugChar(void); /* read and return a single char */
#endif /* !(__ASSEMBLY__) */
#endif /* !(_PPC_KGDB_H) */
#endif /* __KERNEL__ */

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#ifdef __KERNEL__
#ifndef _ASM_KMAP_TYPES_H
#define _ASM_KMAP_TYPES_H
enum km_type {
KM_BOUNCE_READ,
KM_SKB_SUNRPC_DATA,
KM_SKB_DATA_SOFTIRQ,
KM_USER0,
KM_USER1,
KM_BIO_SRC_IRQ,
KM_BIO_DST_IRQ,
KM_PTE0,
KM_PTE1,
KM_IRQ0,
KM_IRQ1,
KM_SOFTIRQ0,
KM_SOFTIRQ1,
KM_PPC_SYNC_PAGE,
KM_TYPE_NR
};
#endif
#endif /* __KERNEL__ */

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#ifndef __ASM_LINKAGE_H
#define __ASM_LINKAGE_H
/* Nothing to see here... */
#endif

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#ifndef __PPC_LOCAL_H
#define __PPC_LOCAL_H
#include <asm-generic/local.h>
#endif /* __PPC_LOCAL_H */

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/*
* Registers for the SGS-Thomson M48T35 Timekeeper RAM chip
* and
* Registers for the SGS-Thomson M48T37 Timekeeper RAM chip
* The 37 is the 35 plus alarm and century thus the offsets
* are shifted by the extra registers.
*/
#ifndef __PPC_M48T35_H
#define __PPC_M48T35_H
/* RTC offsets */
#define M48T35_RTC_FLAGS (-8) /* the negative regs are really T37 only */
#define M48T35_RTC_CENTURY (-7)
#define M48T35_RTC_AL_SEC (-6)
#define M48T35_RTC_AL_MIN (-5)
#define M48T35_RTC_AL_HRS (-4)
#define M48T35_RTC_AL_DOM (-3)
#define M48T35_RTC_INTERRUPT (-2)
#define M48T35_RTC_WATCHDOG (-1)
#define M48T35_RTC_CONTROL 0 /* T35 starts here */
#define M48T35_RTC_SECONDS 1
#define M48T35_RTC_MINUTES 2
#define M48T35_RTC_HOURS 3
#define M48T35_RTC_DAY 4
#define M48T35_RTC_DOM 5
#define M48T35_RTC_MONTH 6
#define M48T35_RTC_YEAR 7
/* this way help us know which bits go with which regs */
#define M48T35_RTC_FLAGS_BL 0x10
#define M48T35_RTC_FLAGS_AF 0x40
#define M48T35_RTC_FLAGS_WDF 0x80
#define M48T35_RTC_INTERRUPT_AFE 0x80
#define M48T35_RTC_INTERRUPT_ABE 0x20
#define M48T35_RTC_INTERRUPT_ALL (M48T35_RTC_INTERRUPT_AFE|M48T35_RTC_INTERRUPT_ABE)
#define M48T35_RTC_WATCHDOG_RB 0x03
#define M48T35_RTC_WATCHDOG_BMB 0x7c
#define M48T35_RTC_WATCHDOG_WDS 0x80
#define M48T35_RTC_WATCHDOG_ALL (M48T35_RTC_WATCHDOG_RB|M48T35_RTC_WATCHDOG_BMB|M48T35_RTC_W
#define M48T35_RTC_CONTROL_WRITE 0x80
#define M48T35_RTC_CONTROL_READ 0x40
#define M48T35_RTC_CONTROL_CAL_SIGN 0x20
#define M48T35_RTC_CONTROL_CAL_VALUE 0x1f
#define M48T35_RTC_CONTROL_LOCKED (M48T35_RTC_WRITE|M48T35_RTC_READ)
#define M48T35_RTC_CONTROL_CALIBRATION (M48T35_RTC_CONTROL_CAL_SIGN|M48T35_RTC_CONTROL_CAL_VALUE)
#define M48T35_RTC_SECONDS_SEC_1 0x0f
#define M48T35_RTC_SECONDS_SEC_10 0x70
#define M48T35_RTC_SECONDS_ST 0x80
#define M48T35_RTC_SECONDS_SEC_ALL (M48T35_RTC_SECONDS_SEC_1|M48T35_RTC_SECONDS_SEC_10)
#define M48T35_RTC_MINUTES_MIN_1 0x0f
#define M48T35_RTC_MINUTES_MIN_10 0x70
#define M48T35_RTC_MINUTES_MIN_ALL (M48T35_RTC_MINUTES_MIN_1|M48T35_RTC_MINUTES_MIN_10)
#define M48T35_RTC_HOURS_HRS_1 0x0f
#define M48T35_RTC_HOURS_HRS_10 0x30
#define M48T35_RTC_HOURS_HRS_ALL (M48T35_RTC_HOURS_HRS_1|M48T35_RTC_HOURS_HRS_10)
#define M48T35_RTC_DAY_DAY_1 0x03
#define M48T35_RTC_DAY_FT 0x40
#define M48T35_RTC_ALARM_OFF 0x00
#define M48T35_RTC_WATCHDOG_OFF 0x00
/* legacy */
#define M48T35_RTC_SET 0x80
#define M48T35_RTC_STOPPED 0x80
#define M48T35_RTC_READ 0x40
#endif

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/*
* include/asm-ppc/m8260_pci.h
*
* Definitions for the MPC8250/MPC8265/MPC8266 integrated PCI host bridge.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifdef __KERNEL__
#ifndef __M8260_PCI_H
#define __M8260_PCI_H
#include <linux/pci_ids.h>
/*
* Define the vendor/device ID for the MPC8265.
*/
#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
#define M8265_PCIBR0 0x101ac
#define M8265_PCIBR1 0x101b0
#define M8265_PCIMSK0 0x101c4
#define M8265_PCIMSK1 0x101c8
/* Bit definitions for PCIBR registers */
#define PCIBR_ENABLE 0x00000001
/* Bit definitions for PCIMSK registers */
#define PCIMSK_32KiB 0xFFFF8000 /* Size of window, smallest */
#define PCIMSK_64KiB 0xFFFF0000
#define PCIMSK_128KiB 0xFFFE0000
#define PCIMSK_256KiB 0xFFFC0000
#define PCIMSK_512KiB 0xFFF80000
#define PCIMSK_1MiB 0xFFF00000
#define PCIMSK_2MiB 0xFFE00000
#define PCIMSK_4MiB 0xFFC00000
#define PCIMSK_8MiB 0xFF800000
#define PCIMSK_16MiB 0xFF000000
#define PCIMSK_32MiB 0xFE000000
#define PCIMSK_64MiB 0xFC000000
#define PCIMSK_128MiB 0xF8000000
#define PCIMSK_256MiB 0xF0000000
#define PCIMSK_512MiB 0xE0000000
#define PCIMSK_1GiB 0xC0000000 /* Size of window, largest */
#define M826X_SCCR_PCI_MODE_EN 0x100
/*
* Outbound ATU registers (3 sets). These registers control how 60x bus (local)
* addresses are translated to PCI addresses when the MPC826x is a PCI bus
* master (initiator).
*/
#define POTAR_REG0 0x10800 /* PCI Outbound Translation Addr registers */
#define POTAR_REG1 0x10818
#define POTAR_REG2 0x10830
#define POBAR_REG0 0x10808 /* PCI Outbound Base Addr registers */
#define POBAR_REG1 0x10820
#define POBAR_REG2 0x10838
#define POCMR_REG0 0x10810 /* PCI Outbound Comparison Mask registers */
#define POCMR_REG1 0x10828
#define POCMR_REG2 0x10840
/* Bit definitions for POMCR registers */
#define POCMR_MASK_4KiB 0x000FFFFF
#define POCMR_MASK_8KiB 0x000FFFFE
#define POCMR_MASK_16KiB 0x000FFFFC
#define POCMR_MASK_32KiB 0x000FFFF8
#define POCMR_MASK_64KiB 0x000FFFF0
#define POCMR_MASK_128KiB 0x000FFFE0
#define POCMR_MASK_256KiB 0x000FFFC0
#define POCMR_MASK_512KiB 0x000FFF80
#define POCMR_MASK_1MiB 0x000FFF00
#define POCMR_MASK_2MiB 0x000FFE00
#define POCMR_MASK_4MiB 0x000FFC00
#define POCMR_MASK_8MiB 0x000FF800
#define POCMR_MASK_16MiB 0x000FF000
#define POCMR_MASK_32MiB 0x000FE000
#define POCMR_MASK_64MiB 0x000FC000
#define POCMR_MASK_128MiB 0x000F8000
#define POCMR_MASK_256MiB 0x000F0000
#define POCMR_MASK_512MiB 0x000E0000
#define POCMR_MASK_1GiB 0x000C0000
#define POCMR_ENABLE 0x80000000
#define POCMR_PCI_IO 0x40000000
#define POCMR_PREFETCH_EN 0x20000000
/* Soft PCI reset */
#define PCI_GCR_REG 0x10880
/* Bit definitions for PCI_GCR registers */
#define PCIGCR_PCI_BUS_EN 0x1
#define PCI_EMR_REG 0x10888
/*
* Inbound ATU registers (2 sets). These registers control how PCI addresses
* are translated to 60x bus (local) addresses when the MPC826x is a PCI bus target.
*/
#define PITAR_REG1 0x108D0
#define PIBAR_REG1 0x108D8
#define PICMR_REG1 0x108E0
#define PITAR_REG0 0x108E8
#define PIBAR_REG0 0x108F0
#define PICMR_REG0 0x108F8
/* Bit definitions for PCI Inbound Comparison Mask registers */
#define PICMR_MASK_4KiB 0x000FFFFF
#define PICMR_MASK_8KiB 0x000FFFFE
#define PICMR_MASK_16KiB 0x000FFFFC
#define PICMR_MASK_32KiB 0x000FFFF8
#define PICMR_MASK_64KiB 0x000FFFF0
#define PICMR_MASK_128KiB 0x000FFFE0
#define PICMR_MASK_256KiB 0x000FFFC0
#define PICMR_MASK_512KiB 0x000FFF80
#define PICMR_MASK_1MiB 0x000FFF00
#define PICMR_MASK_2MiB 0x000FFE00
#define PICMR_MASK_4MiB 0x000FFC00
#define PICMR_MASK_8MiB 0x000FF800
#define PICMR_MASK_16MiB 0x000FF000
#define PICMR_MASK_32MiB 0x000FE000
#define PICMR_MASK_64MiB 0x000FC000
#define PICMR_MASK_128MiB 0x000F8000
#define PICMR_MASK_256MiB 0x000F0000
#define PICMR_MASK_512MiB 0x000E0000
#define PICMR_MASK_1GiB 0x000C0000
#define PICMR_ENABLE 0x80000000
#define PICMR_NO_SNOOP_EN 0x40000000
#define PICMR_PREFETCH_EN 0x20000000
/* PCI error Registers */
#define PCI_ERROR_STATUS_REG 0x10884
#define PCI_ERROR_MASK_REG 0x10888
#define PCI_ERROR_CONTROL_REG 0x1088C
#define PCI_ERROR_ADRS_CAPTURE_REG 0x10890
#define PCI_ERROR_DATA_CAPTURE_REG 0x10898
#define PCI_ERROR_CTRL_CAPTURE_REG 0x108A0
/* PCI error Register bit defines */
#define PCI_ERROR_PCI_ADDR_PAR 0x00000001
#define PCI_ERROR_PCI_DATA_PAR_WR 0x00000002
#define PCI_ERROR_PCI_DATA_PAR_RD 0x00000004
#define PCI_ERROR_PCI_NO_RSP 0x00000008
#define PCI_ERROR_PCI_TAR_ABT 0x00000010
#define PCI_ERROR_PCI_SERR 0x00000020
#define PCI_ERROR_PCI_PERR_RD 0x00000040
#define PCI_ERROR_PCI_PERR_WR 0x00000080
#define PCI_ERROR_I2O_OFQO 0x00000100
#define PCI_ERROR_I2O_IPQO 0x00000200
#define PCI_ERROR_IRA 0x00000400
#define PCI_ERROR_NMI 0x00000800
#define PCI_ERROR_I2O_DBMC 0x00001000
/*
* Register pair used to generate configuration cycles on the PCI bus
* and access the MPC826x's own PCI configuration registers.
*/
#define PCI_CFG_ADDR_REG 0x10900
#define PCI_CFG_DATA_REG 0x10904
/* Bus parking decides where the bus control sits when idle */
/* If modifying memory controllers for PCI park on the core */
#define PPC_ACR_BUS_PARK_CORE 0x6
#define PPC_ACR_BUS_PARK_PCI 0x3
#endif /* __M8260_PCI_H */
#endif /* __KERNEL__ */

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#ifdef __KERNEL__
#ifndef _PPC_MACHDEP_H
#define _PPC_MACHDEP_H
#include <linux/config.h>
#include <linux/init.h>
#include <asm/setup.h>
#ifdef CONFIG_APUS
#include <asm-m68k/machdep.h>
#endif
struct pt_regs;
struct pci_bus;
struct pci_dev;
struct seq_file;
/* We export this macro for external modules like Alsa to know if
* ppc_md.feature_call is implemented or not
*/
#define CONFIG_PPC_HAS_FEATURE_CALLS
struct machdep_calls {
void (*setup_arch)(void);
/* Optional, may be NULL. */
int (*show_cpuinfo)(struct seq_file *m);
int (*show_percpuinfo)(struct seq_file *m, int i);
/* Optional, may be NULL. */
unsigned int (*irq_canonicalize)(unsigned int irq);
void (*init_IRQ)(void);
int (*get_irq)(struct pt_regs *);
/* A general init function, called by ppc_init in init/main.c.
May be NULL. */
void (*init)(void);
void (*restart)(char *cmd);
void (*power_off)(void);
void (*halt)(void);
void (*idle)(void);
void (*power_save)(void);
long (*time_init)(void); /* Optional, may be NULL */
int (*set_rtc_time)(unsigned long nowtime);
unsigned long (*get_rtc_time)(void);
unsigned char (*rtc_read_val)(int addr);
void (*rtc_write_val)(int addr, unsigned char val);
void (*calibrate_decr)(void);
void (*heartbeat)(void);
unsigned long heartbeat_reset;
unsigned long heartbeat_count;
unsigned long (*find_end_of_memory)(void);
void (*setup_io_mappings)(void);
void (*early_serial_map)(void);
void (*progress)(char *, unsigned short);
void (*kgdb_map_scc)(void);
unsigned char (*nvram_read_val)(int addr);
void (*nvram_write_val)(int addr, unsigned char val);
void (*nvram_sync)(void);
/*
* optional PCI "hooks"
*/
/* Called after scanning the bus, before allocating resources */
void (*pcibios_fixup)(void);
/* Called after PPC generic resource fixup to perform
machine specific fixups */
void (*pcibios_fixup_resources)(struct pci_dev *);
/* Called for each PCI bus in the system when it's probed */
void (*pcibios_fixup_bus)(struct pci_bus *);
/* Called when pci_enable_device() is called (initial=0) or
* when a device with no assigned resource is found (initial=1).
* Returns 0 to allow assignment/enabling of the device. */
int (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
/* For interrupt routing */
unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *);
int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char);
/* Called in indirect_* to avoid touching devices */
int (*pci_exclude_device)(unsigned char, unsigned char);
/* Called at then very end of pcibios_init() */
void (*pcibios_after_init)(void);
/* this is for modules, since _machine can be a define -- Cort */
int ppc_machine;
/* Motherboard/chipset features. This is a kind of general purpose
* hook used to control some machine specific features (like reset
* lines, chip power control, etc...).
*/
long (*feature_call)(unsigned int feature, ...);
#ifdef CONFIG_SMP
/* functions for dealing with other cpus */
struct smp_ops_t *smp_ops;
#endif /* CONFIG_SMP */
};
extern struct machdep_calls ppc_md;
extern char cmd_line[COMMAND_LINE_SIZE];
extern void setup_pci_ptrs(void);
/*
* Power macintoshes have either a CUDA or a PMU controlling
* system reset, power, NVRAM, RTC.
*/
typedef enum sys_ctrler_kind {
SYS_CTRLER_UNKNOWN = 0,
SYS_CTRLER_CUDA = 1,
SYS_CTRLER_PMU = 2,
} sys_ctrler_t;
extern sys_ctrler_t sys_ctrler;
#ifdef CONFIG_SMP
struct smp_ops_t {
void (*message_pass)(int target, int msg, unsigned long data, int wait);
int (*probe)(void);
void (*kick_cpu)(int nr);
void (*setup_cpu)(int nr);
void (*space_timers)(int nr);
void (*take_timebase)(void);
void (*give_timebase)(void);
};
/* Poor default implementations */
extern void __devinit smp_generic_give_timebase(void);
extern void __devinit smp_generic_take_timebase(void);
#endif /* CONFIG_SMP */
#endif /* _PPC_MACHDEP_H */
#endif /* __KERNEL__ */

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#ifndef __MACIO_ASIC_H__
#define __MACIO_ASIC_H__
#include <asm/of_device.h>
extern struct bus_type macio_bus_type;
/* MacIO device driver is defined later */
struct macio_driver;
struct macio_chip;
#define MACIO_DEV_COUNT_RESOURCES 8
#define MACIO_DEV_COUNT_IRQS 8
/*
* the macio_bus structure is used to describe a "virtual" bus
* within a MacIO ASIC. It's typically provided by a macio_pci_asic
* PCI device, but could be provided differently as well (nubus
* machines using a fake OF tree).
*
* The pdev field can be NULL on non-PCI machines
*/
struct macio_bus
{
struct macio_chip *chip; /* macio_chip (private use) */
int index; /* macio chip index in system */
#ifdef CONFIG_PCI
struct pci_dev *pdev; /* PCI device hosting this bus */
#endif
};
/*
* the macio_dev structure is used to describe a device
* within an Apple MacIO ASIC.
*/
struct macio_dev
{
struct macio_bus *bus; /* macio bus this device is on */
struct macio_dev *media_bay; /* Device is part of a media bay */
struct of_device ofdev;
int n_resources;
struct resource resource[MACIO_DEV_COUNT_RESOURCES];
int n_interrupts;
struct resource interrupt[MACIO_DEV_COUNT_IRQS];
};
#define to_macio_device(d) container_of(d, struct macio_dev, ofdev.dev)
#define of_to_macio_device(d) container_of(d, struct macio_dev, ofdev)
extern struct macio_dev *macio_dev_get(struct macio_dev *dev);
extern void macio_dev_put(struct macio_dev *dev);
/*
* Accessors to resources & interrupts and other device
* fields
*/
static inline int macio_resource_count(struct macio_dev *dev)
{
return dev->n_resources;
}
static inline unsigned long macio_resource_start(struct macio_dev *dev, int resource_no)
{
return dev->resource[resource_no].start;
}
static inline unsigned long macio_resource_end(struct macio_dev *dev, int resource_no)
{
return dev->resource[resource_no].end;
}
static inline unsigned long macio_resource_len(struct macio_dev *dev, int resource_no)
{
struct resource *res = &dev->resource[resource_no];
if (res->start == 0 || res->end == 0 || res->end < res->start)
return 0;
return res->end - res->start + 1;
}
extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
extern void macio_release_resource(struct macio_dev *dev, int resource_no);
extern int macio_request_resources(struct macio_dev *dev, const char *name);
extern void macio_release_resources(struct macio_dev *dev);
static inline int macio_irq_count(struct macio_dev *dev)
{
return dev->n_interrupts;
}
static inline int macio_irq(struct macio_dev *dev, int irq_no)
{
return dev->interrupt[irq_no].start;
}
static inline void macio_set_drvdata(struct macio_dev *dev, void *data)
{
dev_set_drvdata(&dev->ofdev.dev, data);
}
static inline void* macio_get_drvdata(struct macio_dev *dev)
{
return dev_get_drvdata(&dev->ofdev.dev);
}
static inline struct device_node *macio_get_of_node(struct macio_dev *mdev)
{
return mdev->ofdev.node;
}
#ifdef CONFIG_PCI
static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
{
return mdev->bus->pdev;
}
#endif
/*
* A driver for a mac-io chip based device
*/
struct macio_driver
{
char *name;
struct of_match *match_table;
struct module *owner;
int (*probe)(struct macio_dev* dev, const struct of_match *match);
int (*remove)(struct macio_dev* dev);
int (*suspend)(struct macio_dev* dev, u32 state);
int (*resume)(struct macio_dev* dev);
int (*shutdown)(struct macio_dev* dev);
struct device_driver driver;
};
#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
extern int macio_register_driver(struct macio_driver *);
extern void macio_unregister_driver(struct macio_driver *);
#endif /* __MACIO_ASIC_H__ */

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/*
* Machine dependent access functions for RTC registers.
*/
#ifdef __KERNEL__
#ifndef __ASM_PPC_MC146818RTC_H
#define __ASM_PPC_MC146818RTC_H
#include <asm/io.h>
#ifndef RTC_PORT
#define RTC_PORT(x) (0x70 + (x))
#define RTC_ALWAYS_BCD 1 /* RTC operates in binary mode */
#endif
/*
* The yet supported machines all access the RTC index register via
* an ISA port access but the way to access the date register differs ...
*/
#define CMOS_READ(addr) ({ \
outb_p((addr),RTC_PORT(0)); \
inb_p(RTC_PORT(1)); \
})
#define CMOS_WRITE(val, addr) ({ \
outb_p((addr),RTC_PORT(0)); \
outb_p((val),RTC_PORT(1)); \
})
#define RTC_IRQ 8
#endif /* __ASM_PPC_MC146818RTC_H */
#endif /* __KERNEL__ */

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/*
* md.h: High speed xor_block operation for RAID4/5
*
*/
#ifdef __KERNEL__
#ifndef __ASM_MD_H
#define __ASM_MD_H
/* #define HAVE_ARCH_XORBLOCK */
#define MD_XORBLOCK_ALIGNMENT sizeof(long)
#endif /* __ASM_MD_H */
#endif /* __KERNEL__ */

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/*
* mediabay.h: definitions for using the media bay
* on PowerBook 3400 and similar computers.
*
* Copyright (C) 1997 Paul Mackerras.
*/
#ifndef _PPC_MEDIABAY_H
#define _PPC_MEDIABAY_H
#ifdef __KERNEL__
#define MB_FD 0 /* media bay contains floppy drive (automatic eject ?) */
#define MB_FD1 1 /* media bay contains floppy drive (manual eject ?) */
#define MB_SOUND 2 /* sound device ? */
#define MB_CD 3 /* media bay contains ATA drive such as CD or ZIP */
#define MB_PCI 5 /* media bay contains a PCI device */
#define MB_POWER 6 /* media bay contains a Power device (???) */
#define MB_NO 7 /* media bay contains nothing */
int check_media_bay(struct device_node *which_bay, int what);
int check_media_bay_by_base(unsigned long base, int what);
/* Number of bays in the machine or 0 */
extern int media_bay_count;
/* called by pmac-ide.c to register IDE controller for media bay */
extern int media_bay_set_ide_infos(struct device_node* which_bay,
unsigned long base, int irq, int index);
#endif /* __KERNEL__ */
#endif /* _PPC_MEDIABAY_H */

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/*
* Registers for the mk48t59 real-time-clock
*/
#ifndef _PPC_MK48T59_H
#define _PPC_MK48T59_H
/* RTC Offsets */
#define MK48T59_RTC_SECONDS 0x1FF9
#define MK48T59_RTC_MINUTES 0x1FFA
#define MK48T59_RTC_HOURS 0x1FFB
#define MK48T59_RTC_DAY_OF_WEEK 0x1FFC
#define MK48T59_RTC_DAY_OF_MONTH 0x1FFD
#define MK48T59_RTC_MONTH 0x1FFE
#define MK48T59_RTC_YEAR 0x1FFF
#define MK48T59_RTC_CONTROLA 0x1FF8
#define MK48T59_RTC_CA_WRITE 0x80
#define MK48T59_RTC_CA_READ 0x40
#define MK48T59_RTC_CA_CALIB_SIGN 0x20
#define MK48T59_RTC_CA_CALIB_MASK 0x1f
#define MK48T59_RTC_CONTROLB 0x1FF9
#define MK48T59_RTC_CB_STOP 0x80
#endif /* _PPC_MK48T59_H */

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#ifndef __PPC_MMAN_H__
#define __PPC_MMAN_H__
#define PROT_READ 0x1 /* page can be read */
#define PROT_WRITE 0x2 /* page can be written */
#define PROT_EXEC 0x4 /* page can be executed */
#define PROT_SEM 0x8 /* page may be used for atomic ops */
#define PROT_NONE 0x0 /* page can not be accessed */
#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */
#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */
#define MAP_SHARED 0x01 /* Share changes */
#define MAP_PRIVATE 0x02 /* Changes are private */
#define MAP_TYPE 0x0f /* Mask for type of mapping */
#define MAP_FIXED 0x10 /* Interpret addr exactly */
#define MAP_ANONYMOUS 0x20 /* don't use a file */
#define MAP_RENAME MAP_ANONYMOUS /* In SunOS terminology */
#define MAP_NORESERVE 0x40 /* don't reserve swap pages */
#define MAP_LOCKED 0x80
#define MAP_GROWSDOWN 0x0100 /* stack-like segment */
#define MAP_DENYWRITE 0x0800 /* ETXTBSY */
#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */
#define MAP_POPULATE 0x8000 /* populate (prefault) pagetables */
#define MAP_NONBLOCK 0x10000 /* do not block on IO */
#define MS_ASYNC 1 /* sync memory asynchronously */
#define MS_INVALIDATE 2 /* invalidate the caches */
#define MS_SYNC 4 /* synchronous memory sync */
#define MCL_CURRENT 0x2000 /* lock all currently mapped pages */
#define MCL_FUTURE 0x4000 /* lock all additions to address space */
#define MADV_NORMAL 0x0 /* default page-in behavior */
#define MADV_RANDOM 0x1 /* page-in minimum required */
#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */
#define MADV_WILLNEED 0x3 /* pre-fault pages */
#define MADV_DONTNEED 0x4 /* discard these pages */
/* compatibility flags */
#define MAP_ANON MAP_ANONYMOUS
#define MAP_FILE 0
#endif /* __PPC_MMAN_H__ */

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/*
* PowerPC memory management structures
*/
#ifdef __KERNEL__
#ifndef _PPC_MMU_H_
#define _PPC_MMU_H_
#include <linux/config.h>
#ifndef __ASSEMBLY__
/*
* Define physical address type. Machines using split size
* virtual/physical addressing like 32-bit virtual / 36-bit
* physical need a larger than native word size type. -Matt
*/
#ifndef CONFIG_PTE_64BIT
typedef unsigned long phys_addr_t;
#else
typedef unsigned long long phys_addr_t;
extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
#endif
/* Default "unsigned long" context */
typedef unsigned long mm_context_t;
/* Hardware Page Table Entry */
typedef struct _PTE {
#ifdef CONFIG_PPC64BRIDGE
unsigned long long vsid:52;
unsigned long api:5;
unsigned long :5;
unsigned long h:1;
unsigned long v:1;
unsigned long long rpn:52;
#else /* CONFIG_PPC64BRIDGE */
unsigned long v:1; /* Entry is valid */
unsigned long vsid:24; /* Virtual segment identifier */
unsigned long h:1; /* Hash algorithm indicator */
unsigned long api:6; /* Abbreviated page index */
unsigned long rpn:20; /* Real (physical) page number */
#endif /* CONFIG_PPC64BRIDGE */
unsigned long :3; /* Unused */
unsigned long r:1; /* Referenced */
unsigned long c:1; /* Changed */
unsigned long w:1; /* Write-thru cache mode */
unsigned long i:1; /* Cache inhibited */
unsigned long m:1; /* Memory coherence */
unsigned long g:1; /* Guarded */
unsigned long :1; /* Unused */
unsigned long pp:2; /* Page protection */
} PTE;
/* Values for PP (assumes Ks=0, Kp=1) */
#define PP_RWXX 0 /* Supervisor read/write, User none */
#define PP_RWRX 1 /* Supervisor read/write, User read */
#define PP_RWRW 2 /* Supervisor read/write, User read/write */
#define PP_RXRX 3 /* Supervisor read, User read */
/* Segment Register */
typedef struct _SEGREG {
unsigned long t:1; /* Normal or I/O type */
unsigned long ks:1; /* Supervisor 'key' (normally 0) */
unsigned long kp:1; /* User 'key' (normally 1) */
unsigned long n:1; /* No-execute */
unsigned long :4; /* Unused */
unsigned long vsid:24; /* Virtual Segment Identifier */
} SEGREG;
/* Block Address Translation (BAT) Registers */
typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
unsigned long bepi:15; /* Effective page index (virtual address) */
unsigned long :8; /* unused */
unsigned long w:1;
unsigned long i:1; /* Cache inhibit */
unsigned long m:1; /* Memory coherence */
unsigned long ks:1; /* Supervisor key (normally 0) */
unsigned long kp:1; /* User key (normally 1) */
unsigned long pp:2; /* Page access protections */
} P601_BATU;
typedef struct _BATU { /* Upper part of BAT (all except 601) */
#ifdef CONFIG_PPC64BRIDGE
unsigned long long bepi:47;
#else /* CONFIG_PPC64BRIDGE */
unsigned long bepi:15; /* Effective page index (virtual address) */
#endif /* CONFIG_PPC64BRIDGE */
unsigned long :4; /* Unused */
unsigned long bl:11; /* Block size mask */
unsigned long vs:1; /* Supervisor valid */
unsigned long vp:1; /* User valid */
} BATU;
typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
unsigned long brpn:15; /* Real page index (physical address) */
unsigned long :10; /* Unused */
unsigned long v:1; /* Valid bit */
unsigned long bl:6; /* Block size mask */
} P601_BATL;
typedef struct _BATL { /* Lower part of BAT (all except 601) */
#ifdef CONFIG_PPC64BRIDGE
unsigned long long brpn:47;
#else /* CONFIG_PPC64BRIDGE */
unsigned long brpn:15; /* Real page index (physical address) */
#endif /* CONFIG_PPC64BRIDGE */
unsigned long :10; /* Unused */
unsigned long w:1; /* Write-thru cache */
unsigned long i:1; /* Cache inhibit */
unsigned long m:1; /* Memory coherence */
unsigned long g:1; /* Guarded (MBZ in IBAT) */
unsigned long :1; /* Unused */
unsigned long pp:2; /* Page access protections */
} BATL;
typedef struct _BAT {
BATU batu; /* Upper register */
BATL batl; /* Lower register */
} BAT;
typedef struct _P601_BAT {
P601_BATU batu; /* Upper register */
P601_BATL batl; /* Lower register */
} P601_BAT;
#endif /* __ASSEMBLY__ */
/* Block size masks */
#define BL_128K 0x000
#define BL_256K 0x001
#define BL_512K 0x003
#define BL_1M 0x007
#define BL_2M 0x00F
#define BL_4M 0x01F
#define BL_8M 0x03F
#define BL_16M 0x07F
#define BL_32M 0x0FF
#define BL_64M 0x1FF
#define BL_128M 0x3FF
#define BL_256M 0x7FF
/* BAT Access Protection */
#define BPP_XX 0x00 /* No access */
#define BPP_RX 0x01 /* Read only */
#define BPP_RW 0x02 /* Read/write */
/* Control/status registers for the MPC8xx.
* A write operation to these registers causes serialized access.
* During software tablewalk, the registers used perform mask/shift-add
* operations when written/read. A TLB entry is created when the Mx_RPN
* is written, and the contents of several registers are used to
* create the entry.
*/
#define MI_CTR 784 /* Instruction TLB control register */
#define MI_GPM 0x80000000 /* Set domain manager mode */
#define MI_PPM 0x40000000 /* Set subpage protection */
#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
#define MI_RESETVAL 0x00000000 /* Value of register at reset */
/* These are the Ks and Kp from the PowerPC books. For proper operation,
* Ks = 0, Kp = 1.
*/
#define MI_AP 786
#define MI_Ks 0x80000000 /* Should not be set */
#define MI_Kp 0x40000000 /* Should always be set */
/* The effective page number register. When read, contains the information
* about the last instruction TLB miss. When MI_RPN is written, bits in
* this register are used to create the TLB entry.
*/
#define MI_EPN 787
#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
#define MI_EVALID 0x00000200 /* Entry is valid */
#define MI_ASIDMASK 0x0000000f /* ASID match value */
/* Reset value is undefined */
/* A "level 1" or "segment" or whatever you want to call it register.
* For the instruction TLB, it contains bits that get loaded into the
* TLB entry when the MI_RPN is written.
*/
#define MI_TWC 789
#define MI_APG 0x000001e0 /* Access protection group (0) */
#define MI_GUARDED 0x00000010 /* Guarded storage */
#define MI_PSMASK 0x0000000c /* Mask of page size bits */
#define MI_PS8MEG 0x0000000c /* 8M page size */
#define MI_PS512K 0x00000004 /* 512K page size */
#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
#define MI_SVALID 0x00000001 /* Segment entry is valid */
/* Reset value is undefined */
/* Real page number. Defined by the pte. Writing this register
* causes a TLB entry to be created for the instruction TLB, using
* additional information from the MI_EPN, and MI_TWC registers.
*/
#define MI_RPN 790
/* Define an RPN value for mapping kernel memory to large virtual
* pages for boot initialization. This has real page number of 0,
* large page size, shared page, cache enabled, and valid.
* Also mark all subpages valid and write access.
*/
#define MI_BOOTINIT 0x000001fd
#define MD_CTR 792 /* Data TLB control register */
#define MD_GPM 0x80000000 /* Set domain manager mode */
#define MD_PPM 0x40000000 /* Set subpage protection */
#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
#define MD_RESETVAL 0x04000000 /* Value of register at reset */
#define M_CASID 793 /* Address space ID (context) to match */
#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
/* These are the Ks and Kp from the PowerPC books. For proper operation,
* Ks = 0, Kp = 1.
*/
#define MD_AP 794
#define MD_Ks 0x80000000 /* Should not be set */
#define MD_Kp 0x40000000 /* Should always be set */
/* The effective page number register. When read, contains the information
* about the last instruction TLB miss. When MD_RPN is written, bits in
* this register are used to create the TLB entry.
*/
#define MD_EPN 795
#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
#define MD_EVALID 0x00000200 /* Entry is valid */
#define MD_ASIDMASK 0x0000000f /* ASID match value */
/* Reset value is undefined */
/* The pointer to the base address of the first level page table.
* During a software tablewalk, reading this register provides the address
* of the entry associated with MD_EPN.
*/
#define M_TWB 796
#define M_L1TB 0xfffff000 /* Level 1 table base address */
#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
/* Reset value is undefined */
/* A "level 1" or "segment" or whatever you want to call it register.
* For the data TLB, it contains bits that get loaded into the TLB entry
* when the MD_RPN is written. It is also provides the hardware assist
* for finding the PTE address during software tablewalk.
*/
#define MD_TWC 797
#define MD_L2TB 0xfffff000 /* Level 2 table base address */
#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
#define MD_APG 0x000001e0 /* Access protection group (0) */
#define MD_GUARDED 0x00000010 /* Guarded storage */
#define MD_PSMASK 0x0000000c /* Mask of page size bits */
#define MD_PS8MEG 0x0000000c /* 8M page size */
#define MD_PS512K 0x00000004 /* 512K page size */
#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
#define MD_WT 0x00000002 /* Use writethrough page attribute */
#define MD_SVALID 0x00000001 /* Segment entry is valid */
/* Reset value is undefined */
/* Real page number. Defined by the pte. Writing this register
* causes a TLB entry to be created for the data TLB, using
* additional information from the MD_EPN, and MD_TWC registers.
*/
#define MD_RPN 798
/* This is a temporary storage register that could be used to save
* a processor working register during a tablewalk.
*/
#define M_TW 799
/*
* At present, all PowerPC 400-class processors share a similar TLB
* architecture. The instruction and data sides share a unified,
* 64-entry, fully-associative TLB which is maintained totally under
* software control. In addition, the instruction side has a
* hardware-managed, 4-entry, fully- associative TLB which serves as a
* first level to the shared TLB. These two TLBs are known as the UTLB
* and ITLB, respectively.
*/
#define PPC4XX_TLB_SIZE 64
/*
* TLB entries are defined by a "high" tag portion and a "low" data
* portion. On all architectures, the data portion is 32-bits.
*
* TLB entries are managed entirely under software control by reading,
* writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
* instructions.
*/
#define TLB_LO 1
#define TLB_HI 0
#define TLB_DATA TLB_LO
#define TLB_TAG TLB_HI
/* Tag portion */
#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
#define TLB_PAGESZ_MASK 0x00000380
#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
#define PAGESZ_1K 0
#define PAGESZ_4K 1
#define PAGESZ_16K 2
#define PAGESZ_64K 3
#define PAGESZ_256K 4
#define PAGESZ_1M 5
#define PAGESZ_4M 6
#define PAGESZ_16M 7
#define TLB_VALID 0x00000040 /* Entry is valid */
/* Data portion */
#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
#define TLB_PERM_MASK 0x00000300
#define TLB_EX 0x00000200 /* Instruction execution allowed */
#define TLB_WR 0x00000100 /* Writes permitted */
#define TLB_ZSEL_MASK 0x000000F0
#define TLB_ZSEL(x) (((x) & 0xF) << 4)
#define TLB_ATTR_MASK 0x0000000F
#define TLB_W 0x00000008 /* Caching is write-through */
#define TLB_I 0x00000004 /* Caching is inhibited */
#define TLB_M 0x00000002 /* Memory is coherent */
#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
/*
* PPC440 support
*/
#define PPC44x_MMUCR_TID 0x000000ff
#define PPC44x_MMUCR_STS 0x00010000
#define PPC44x_TLB_PAGEID 0
#define PPC44x_TLB_XLAT 1
#define PPC44x_TLB_ATTRIB 2
/* Page identification fields */
#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
#define PPC44x_TLB_TS 0x00000100 /* Translation address space */
#define PPC44x_TLB_1K 0x00000000 /* Page sizes */
#define PPC44x_TLB_4K 0x00000010
#define PPC44x_TLB_16K 0x00000020
#define PPC44x_TLB_64K 0x00000030
#define PPC44x_TLB_256K 0x00000040
#define PPC44x_TLB_1M 0x00000050
#define PPC44x_TLB_16M 0x00000070
#define PPC44x_TLB_256M 0x00000090
/* Translation fields */
#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
#define PPC44x_TLB_ERPN_MASK 0x0000000f
/* Storage attribute and access control fields */
#define PPC44x_TLB_ATTR_MASK 0x0000ff80
#define PPC44x_TLB_U0 0x00008000 /* User 0 */
#define PPC44x_TLB_U1 0x00004000 /* User 1 */
#define PPC44x_TLB_U2 0x00002000 /* User 2 */
#define PPC44x_TLB_U3 0x00001000 /* User 3 */
#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
#define PPC44x_TLB_PERM_MASK 0x0000003f
#define PPC44x_TLB_UX 0x00000020 /* User execution */
#define PPC44x_TLB_UW 0x00000010 /* User write */
#define PPC44x_TLB_UR 0x00000008 /* User read */
#define PPC44x_TLB_SX 0x00000004 /* Super execution */
#define PPC44x_TLB_SW 0x00000002 /* Super write */
#define PPC44x_TLB_SR 0x00000001 /* Super read */
/* Book-E defined page sizes */
#define BOOKE_PAGESZ_1K 0
#define BOOKE_PAGESZ_4K 1
#define BOOKE_PAGESZ_16K 2
#define BOOKE_PAGESZ_64K 3
#define BOOKE_PAGESZ_256K 4
#define BOOKE_PAGESZ_1M 5
#define BOOKE_PAGESZ_4M 6
#define BOOKE_PAGESZ_16M 7
#define BOOKE_PAGESZ_64M 8
#define BOOKE_PAGESZ_256M 9
#define BOOKE_PAGESZ_1GB 10
#define BOOKE_PAGESZ_4GB 11
#define BOOKE_PAGESZ_16GB 12
#define BOOKE_PAGESZ_64GB 13
#define BOOKE_PAGESZ_256GB 14
#define BOOKE_PAGESZ_1TB 15
/*
* Freescale Book-E MMU support
*/
#define MAS0_TLBSEL 0x10000000
#define MAS0_ESEL 0x000F0000
#define MAS0_NV 0x00000001
#define MAS1_VALID 0x80000000
#define MAS1_IPROT 0x40000000
#define MAS1_TID 0x03FF0000
#define MAS1_TS 0x00001000
#define MAS1_TSIZE(x) (x << 8)
#define MAS2_EPN 0xFFFFF000
#define MAS2_SHAREN 0x00000200
#define MAS2_X0 0x00000040
#define MAS2_X1 0x00000020
#define MAS2_W 0x00000010
#define MAS2_I 0x00000008
#define MAS2_M 0x00000004
#define MAS2_G 0x00000002
#define MAS2_E 0x00000001
#define MAS3_RPN 0xFFFFF000
#define MAS3_U0 0x00000200
#define MAS3_U1 0x00000100
#define MAS3_U2 0x00000080
#define MAS3_U3 0x00000040
#define MAS3_UX 0x00000020
#define MAS3_SX 0x00000010
#define MAS3_UW 0x00000008
#define MAS3_SW 0x00000004
#define MAS3_UR 0x00000002
#define MAS3_SR 0x00000001
#define MAS4_TLBSELD 0x10000000
#define MAS4_TIDDSEL 0x00030000
#define MAS4_DSHAREN 0x00001000
#define MAS4_TSIZED(x) (x << 8)
#define MAS4_X0D 0x00000040
#define MAS4_X1D 0x00000020
#define MAS4_WD 0x00000010
#define MAS4_ID 0x00000008
#define MAS4_MD 0x00000004
#define MAS4_GD 0x00000002
#define MAS4_ED 0x00000001
#define MAS6_SPID 0x00FF0000
#define MAS6_SAS 0x00000001
#endif /* _PPC_MMU_H_ */
#endif /* __KERNEL__ */

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#ifdef __KERNEL__
#ifndef __PPC_MMU_CONTEXT_H
#define __PPC_MMU_CONTEXT_H
#include <linux/config.h>
#include <asm/atomic.h>
#include <asm/bitops.h>
#include <asm/mmu.h>
#include <asm/cputable.h>
/*
* On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs
* (virtual segment identifiers) for each context. Although the
* hardware supports 24-bit VSIDs, and thus >1 million contexts,
* we only use 32,768 of them. That is ample, since there can be
* at most around 30,000 tasks in the system anyway, and it means
* that we can use a bitmap to indicate which contexts are in use.
* Using a bitmap means that we entirely avoid all of the problems
* that we used to have when the context number overflowed,
* particularly on SMP systems.
* -- paulus.
*/
/*
* This function defines the mapping from contexts to VSIDs (virtual
* segment IDs). We use a skew on both the context and the high 4 bits
* of the 32-bit virtual address (the "effective segment ID") in order
* to spread out the entries in the MMU hash table. Note, if this
* function is changed then arch/ppc/mm/hashtable.S will have to be
* changed to correspond.
*/
#define CTX_TO_VSID(ctx, va) (((ctx) * (897 * 16) + ((va) >> 28) * 0x111) \
& 0xffffff)
/*
The MPC8xx has only 16 contexts. We rotate through them on each
task switch. A better way would be to keep track of tasks that
own contexts, and implement an LRU usage. That way very active
tasks don't always have to pay the TLB reload overhead. The
kernel pages are mapped shared, so the kernel can run on behalf
of any task that makes a kernel entry. Shared does not mean they
are not protected, just that the ASID comparison is not performed.
-- Dan
The IBM4xx has 256 contexts, so we can just rotate through these
as a way of "switching" contexts. If the TID of the TLB is zero,
the PID/TID comparison is disabled, so we can use a TID of zero
to represent all kernel pages as shared among all contexts.
-- Dan
*/
static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}
#ifdef CONFIG_8xx
#define NO_CONTEXT 16
#define LAST_CONTEXT 15
#define FIRST_CONTEXT 0
#elif defined(CONFIG_4xx)
#define NO_CONTEXT 256
#define LAST_CONTEXT 255
#define FIRST_CONTEXT 1
#elif defined(CONFIG_E500)
#define NO_CONTEXT 256
#define LAST_CONTEXT 255
#define FIRST_CONTEXT 1
#else
/* PPC 6xx, 7xx CPUs */
#define NO_CONTEXT ((mm_context_t) -1)
#define LAST_CONTEXT 32767
#define FIRST_CONTEXT 1
#endif
/*
* Set the current MMU context.
* On 32-bit PowerPCs (other than the 8xx embedded chips), this is done by
* loading up the segment registers for the user part of the address space.
*
* Since the PGD is immediately available, it is much faster to simply
* pass this along as a second parameter, which is required for 8xx and
* can be used for debugging on all processors (if you happen to have
* an Abatron).
*/
extern void set_context(mm_context_t context, pgd_t *pgd);
/*
* Bitmap of contexts in use.
* The size of this bitmap is LAST_CONTEXT + 1 bits.
*/
extern unsigned long context_map[];
/*
* This caches the next context number that we expect to be free.
* Its use is an optimization only, we can't rely on this context
* number to be free, but it usually will be.
*/
extern mm_context_t next_mmu_context;
/*
* If we don't have sufficient contexts to give one to every task
* that could be in the system, we need to be able to steal contexts.
* These variables support that.
*/
#if LAST_CONTEXT < 30000
#define FEW_CONTEXTS 1
extern atomic_t nr_free_contexts;
extern struct mm_struct *context_mm[LAST_CONTEXT+1];
extern void steal_context(void);
#endif
/*
* Get a new mmu context for the address space described by `mm'.
*/
static inline void get_mmu_context(struct mm_struct *mm)
{
mm_context_t ctx;
if (mm->context != NO_CONTEXT)
return;
#ifdef FEW_CONTEXTS
while (atomic_dec_if_positive(&nr_free_contexts) < 0)
steal_context();
#endif
ctx = next_mmu_context;
while (test_and_set_bit(ctx, context_map)) {
ctx = find_next_zero_bit(context_map, LAST_CONTEXT+1, ctx);
if (ctx > LAST_CONTEXT)
ctx = 0;
}
next_mmu_context = (ctx + 1) & LAST_CONTEXT;
mm->context = ctx;
#ifdef FEW_CONTEXTS
context_mm[ctx] = mm;
#endif
}
/*
* Set up the context for a new address space.
*/
#define init_new_context(tsk,mm) (((mm)->context = NO_CONTEXT), 0)
/*
* We're finished using the context for an address space.
*/
static inline void destroy_context(struct mm_struct *mm)
{
if (mm->context != NO_CONTEXT) {
clear_bit(mm->context, context_map);
mm->context = NO_CONTEXT;
#ifdef FEW_CONTEXTS
atomic_inc(&nr_free_contexts);
#endif
}
}
static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
struct task_struct *tsk)
{
#ifdef CONFIG_ALTIVEC
asm volatile (
BEGIN_FTR_SECTION
"dssall;\n"
#ifndef CONFIG_POWER4
"sync;\n" /* G4 needs a sync here, G5 apparently not */
#endif
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
: : );
#endif /* CONFIG_ALTIVEC */
tsk->thread.pgdir = next->pgd;
/* No need to flush userspace segments if the mm doesnt change */
if (prev == next)
return;
/* Setup new userspace context */
get_mmu_context(next);
set_context(next->context, next->pgd);
}
#define deactivate_mm(tsk,mm) do { } while (0)
/*
* After we have set current->mm to a new value, this activates
* the context for the new mm so we see the new mappings.
*/
#define activate_mm(active_mm, mm) switch_mm(active_mm, mm, current)
extern void mmu_context_init(void);
#endif /* __PPC_MMU_CONTEXT_H */
#endif /* __KERNEL__ */

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#ifndef _ASM_PPC_MODULE_H
#define _ASM_PPC_MODULE_H
/* Module stuff for PPC. (C) 2001 Rusty Russell */
#include <linux/list.h>
#include <asm/bug.h>
/* Thanks to Paul M for explaining this.
PPC can only do rel jumps += 32MB, and often the kernel and other
modules are furthur away than this. So, we jump to a table of
trampolines attached to the module (the Procedure Linkage Table)
whenever that happens.
*/
struct ppc_plt_entry
{
/* 16 byte jump instruction sequence (4 instructions) */
unsigned int jump[4];
};
struct mod_arch_specific
{
/* Indices of PLT sections within module. */
unsigned int core_plt_section, init_plt_section;
/* List of BUG addresses, source line numbers and filenames */
struct list_head bug_list;
struct bug_entry *bug_table;
unsigned int num_bugs;
};
extern struct bug_entry *module_find_bug(unsigned long bugaddr);
#define Elf_Shdr Elf32_Shdr
#define Elf_Sym Elf32_Sym
#define Elf_Ehdr Elf32_Ehdr
/* Make empty sections for module_frob_arch_sections to expand. */
#ifdef MODULE
asm(".section .plt,\"ax\",@nobits; .align 3; .previous");
asm(".section .init.plt,\"ax\",@nobits; .align 3; .previous");
#endif
#endif /* _ASM_PPC_MODULE_H */

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/*
* arch/ppc/kernel/mpc10x.h
*
* Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem
* ctlr/EPIC/etc.
*
* Author: Mark A. Greer
* mgreer@mvista.com
*
* 2001 (c) MontaVista, Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef __PPC_KERNEL_MPC10X_H
#define __PPC_KERNEL_MPC10X_H
#include <linux/pci_ids.h>
#include <asm/pci-bridge.h>
/*
* The values here don't completely map everything but should work in most
* cases.
*
* MAP A (PReP Map)
* Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff
* Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff
* PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000
* EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
*
* MAP B (CHRP Map)
* Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff
* Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff
* PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000
* EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB)
*/
/*
* Define the vendor/device IDs for the various bridges--should be added to
* <linux/pci_ids.h>
*/
#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \
PCI_VENDOR_ID_MOTOROLA)
#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA)
#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA)
#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA)
/* Define the type of map to use */
#define MPC10X_MEM_MAP_A 1
#define MPC10X_MEM_MAP_B 2
/* Map A (PReP Map) Defines */
#define MPC10X_MAPA_CNFG_ADDR 0x80000cf8
#define MPC10X_MAPA_CNFG_DATA 0x80000cfc
#define MPC10X_MAPA_ISA_IO_BASE 0x80000000
#define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000
#define MPC10X_MAPA_DRAM_OFFSET 0x80000000
#define MPC10X_MAPA_PCI_INTACK_ADDR 0xbffffff0
#define MPC10X_MAPA_PCI_IO_START 0x00000000
#define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1)
#define MPC10X_MAPA_PCI_MEM_START 0x00000000
#define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1)
#define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \
MPC10X_MAPA_PCI_MEM_START)
/* Map B (CHRP Map) Defines */
#define MPC10X_MAPB_CNFG_ADDR 0xfec00000
#define MPC10X_MAPB_CNFG_DATA 0xfee00000
#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000
#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000
#define MPC10X_MAPB_DRAM_OFFSET 0x00000000
#define MPC10X_MAPB_PCI_INTACK_ADDR 0xfef00000
#define MPC10X_MAPB_PCI_IO_START 0x00000000
#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1)
#define MPC10X_MAPB_PCI_MEM_START 0x80000000
#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1)
#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \
MPC10X_MAPB_PCI_MEM_START)
/* Set hose members to values appropriate for the mem map used */
#define MPC10X_SETUP_HOSE(hose, map) { \
(hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET; \
(hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START; \
(hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END; \
(hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START; \
(hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END; \
(hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE; \
}
/* Miscellaneous Configuration register offsets */
#define MPC10X_CFG_PIR_REG 0x09
#define MPC10X_CFG_PIR_HOST_BRIDGE 0x00
#define MPC10X_CFG_PIR_AGENT 0x01
#define MPC10X_CFG_EUMBBAR 0x78
#define MPC10X_CFG_PICR1_REG 0xa8
#define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000
#define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000
#define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000
#define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040
#define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0
#define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */
#define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */
#define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */
#define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x80 /* PCI_COMPATIBILITY_HOLE */
#define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x40 /* PROC_COMPATIBILITY_HOLE */
/* Define offsets for the memory controller registers in the config space */
#define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */
#define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */
#define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */
#define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */
#define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */
#define MPC10X_MCTLR_MEM_END_2 0x94 /* Banks 4-7 */
#define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */
#define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */
#define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0
/* Define some offset in the EUMB */
#define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */
#define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */
#define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */
#define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */
#define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */
#define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */
#define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */
#define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */
#define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */
#define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */
#define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */
#define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */
#define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */
#define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */
#define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */
#define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */
#define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */
/*
* Define some recommended places to put the EUMB regs.
* For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff.
*/
extern unsigned long ioremap_base;
#define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE)
#define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE
int mpc10x_bridge_init(struct pci_controller *hose,
uint current_map,
uint new_map,
uint phys_eumb_base);
unsigned long mpc10x_get_mem_size(uint mem_map);
int mpc10x_enable_store_gathering(struct pci_controller *hose);
int mpc10x_disable_store_gathering(struct pci_controller *hose);
/* For MPC107 boards that use the built-in openpic */
void mpc10x_set_openpic(void);
#endif /* __PPC_KERNEL_MPC10X_H */

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/*
* include/asm-ppc/mpc52xx.h
*
* Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
* May need to be cleaned as the port goes on ...
*
*
* Maintainer : Sylvain Munaut <tnt@246tNt.com>
*
* Originally written by Dale Farnsworth <dfarnsworth@mvista.com>
* for the 2.4 kernel.
*
* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2003 MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef __ASM_MPC52xx_H__
#define __ASM_MPC52xx_H__
#ifndef __ASSEMBLY__
#include <asm/ppcboot.h>
#include <asm/types.h>
struct pt_regs;
struct ocp_def;
#endif /* __ASSEMBLY__ */
/* ======================================================================== */
/* Main registers/struct addresses */
/* ======================================================================== */
/* Theses are PHYSICAL addresses ! */
/* TODO : There should be no static mapping, but it's not yet the case, so */
/* we require a 1:1 mapping */
#define MPC52xx_MBAR 0xf0000000 /* Phys address */
#define MPC52xx_MBAR_SIZE 0x00010000
#define MPC52xx_MBAR_VIRT 0xf0000000 /* Virt address */
#define MPC52xx_MMAP_CTL (MPC52xx_MBAR + 0x0000)
#define MPC52xx_SDRAM (MPC52xx_MBAR + 0x0100)
#define MPC52xx_CDM (MPC52xx_MBAR + 0x0200)
#define MPC52xx_SFTRST (MPC52xx_MBAR + 0x0220)
#define MPC52xx_SFTRST_BIT 0x01000000
#define MPC52xx_INTR (MPC52xx_MBAR + 0x0500)
#define MPC52xx_GPTx(x) (MPC52xx_MBAR + 0x0600 + ((x)<<4))
#define MPC52xx_RTC (MPC52xx_MBAR + 0x0800)
#define MPC52xx_MSCAN1 (MPC52xx_MBAR + 0x0900)
#define MPC52xx_MSCAN2 (MPC52xx_MBAR + 0x0980)
#define MPC52xx_GPIO (MPC52xx_MBAR + 0x0b00)
#define MPC52xx_GPIO_WKUP (MPC52xx_MBAR + 0x0c00)
#define MPC52xx_PCI (MPC52xx_MBAR + 0x0d00)
#define MPC52xx_USB_OHCI (MPC52xx_MBAR + 0x1000)
#define MPC52xx_SDMA (MPC52xx_MBAR + 0x1200)
#define MPC52xx_XLB (MPC52xx_MBAR + 0x1f00)
#define MPC52xx_PSCx(x) (MPC52xx_MBAR + 0x2000 + ((x)<<9))
#define MPC52xx_PSC1 (MPC52xx_MBAR + 0x2000)
#define MPC52xx_PSC2 (MPC52xx_MBAR + 0x2200)
#define MPC52xx_PSC3 (MPC52xx_MBAR + 0x2400)
#define MPC52xx_PSC4 (MPC52xx_MBAR + 0x2600)
#define MPC52xx_PSC5 (MPC52xx_MBAR + 0x2800)
#define MPC52xx_PSC6 (MPC52xx_MBAR + 0x2C00)
#define MPC52xx_FEC (MPC52xx_MBAR + 0x3000)
#define MPC52xx_ATA (MPC52xx_MBAR + 0x3a00)
#define MPC52xx_I2C1 (MPC52xx_MBAR + 0x3d00)
#define MPC52xx_I2C_MICR (MPC52xx_MBAR + 0x3d20)
#define MPC52xx_I2C2 (MPC52xx_MBAR + 0x3d40)
/* SRAM used for SDMA */
#define MPC52xx_SRAM (MPC52xx_MBAR + 0x8000)
#define MPC52xx_SRAM_SIZE (16*1024)
/* ======================================================================== */
/* IRQ mapping */
/* ======================================================================== */
/* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change
* this
*/
#define MPC52xx_CRIT_IRQ_NUM 4
#define MPC52xx_MAIN_IRQ_NUM 17
#define MPC52xx_SDMA_IRQ_NUM 17
#define MPC52xx_PERP_IRQ_NUM 23
#define MPC52xx_CRIT_IRQ_BASE 0
#define MPC52xx_MAIN_IRQ_BASE (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
#define MPC52xx_SDMA_IRQ_BASE (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
#define MPC52xx_PERP_IRQ_BASE (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
#define MPC52xx_IRQ0 (MPC52xx_CRIT_IRQ_BASE + 0)
#define MPC52xx_SLICE_TIMER_0_IRQ (MPC52xx_CRIT_IRQ_BASE + 1)
#define MPC52xx_HI_INT_IRQ (MPC52xx_CRIT_IRQ_BASE + 2)
#define MPC52xx_CCS_IRQ (MPC52xx_CRIT_IRQ_BASE + 3)
#define MPC52xx_IRQ1 (MPC52xx_MAIN_IRQ_BASE + 1)
#define MPC52xx_IRQ2 (MPC52xx_MAIN_IRQ_BASE + 2)
#define MPC52xx_IRQ3 (MPC52xx_MAIN_IRQ_BASE + 3)
#define MPC52xx_SDMA_IRQ (MPC52xx_PERP_IRQ_BASE + 0)
#define MPC52xx_PSC1_IRQ (MPC52xx_PERP_IRQ_BASE + 1)
#define MPC52xx_PSC2_IRQ (MPC52xx_PERP_IRQ_BASE + 2)
#define MPC52xx_PSC3_IRQ (MPC52xx_PERP_IRQ_BASE + 3)
#define MPC52xx_PSC6_IRQ (MPC52xx_PERP_IRQ_BASE + 4)
#define MPC52xx_IRDA_IRQ (MPC52xx_PERP_IRQ_BASE + 4)
#define MPC52xx_FEC_IRQ (MPC52xx_PERP_IRQ_BASE + 5)
#define MPC52xx_USB_IRQ (MPC52xx_PERP_IRQ_BASE + 6)
#define MPC52xx_ATA_IRQ (MPC52xx_PERP_IRQ_BASE + 7)
#define MPC52xx_PCI_CNTRL_IRQ (MPC52xx_PERP_IRQ_BASE + 8)
#define MPC52xx_PCI_SCIRX_IRQ (MPC52xx_PERP_IRQ_BASE + 9)
#define MPC52xx_PCI_SCITX_IRQ (MPC52xx_PERP_IRQ_BASE + 10)
#define MPC52xx_PSC4_IRQ (MPC52xx_PERP_IRQ_BASE + 11)
#define MPC52xx_PSC5_IRQ (MPC52xx_PERP_IRQ_BASE + 12)
#define MPC52xx_SPI_MODF_IRQ (MPC52xx_PERP_IRQ_BASE + 13)
#define MPC52xx_SPI_SPIF_IRQ (MPC52xx_PERP_IRQ_BASE + 14)
#define MPC52xx_I2C1_IRQ (MPC52xx_PERP_IRQ_BASE + 15)
#define MPC52xx_I2C2_IRQ (MPC52xx_PERP_IRQ_BASE + 16)
#define MPC52xx_CAN1_IRQ (MPC52xx_PERP_IRQ_BASE + 17)
#define MPC52xx_CAN2_IRQ (MPC52xx_PERP_IRQ_BASE + 18)
#define MPC52xx_IR_RX_IRQ (MPC52xx_PERP_IRQ_BASE + 19)
#define MPC52xx_IR_TX_IRQ (MPC52xx_PERP_IRQ_BASE + 20)
#define MPC52xx_XLB_ARB_IRQ (MPC52xx_PERP_IRQ_BASE + 21)
/* ======================================================================== */
/* Structures mapping of some unit register set */
/* ======================================================================== */
#ifndef __ASSEMBLY__
/* Memory Mapping Control */
struct mpc52xx_mmap_ctl {
u32 mbar; /* MMAP_CTRL + 0x00 */
u32 cs0_start; /* MMAP_CTRL + 0x04 */
u32 cs0_stop; /* MMAP_CTRL + 0x08 */
u32 cs1_start; /* MMAP_CTRL + 0x0c */
u32 cs1_stop; /* MMAP_CTRL + 0x10 */
u32 cs2_start; /* MMAP_CTRL + 0x14 */
u32 cs2_stop; /* MMAP_CTRL + 0x18 */
u32 cs3_start; /* MMAP_CTRL + 0x1c */
u32 cs3_stop; /* MMAP_CTRL + 0x20 */
u32 cs4_start; /* MMAP_CTRL + 0x24 */
u32 cs4_stop; /* MMAP_CTRL + 0x28 */
u32 cs5_start; /* MMAP_CTRL + 0x2c */
u32 cs5_stop; /* MMAP_CTRL + 0x30 */
u32 sdram0; /* MMAP_CTRL + 0x34 */
u32 sdram1; /* MMAP_CTRL + 0X38 */
u32 reserved[4]; /* MMAP_CTRL + 0x3c .. 0x48 */
u32 boot_start; /* MMAP_CTRL + 0x4c */
u32 boot_stop; /* MMAP_CTRL + 0x50 */
u32 ipbi_ws_ctrl; /* MMAP_CTRL + 0x54 */
u32 cs6_start; /* MMAP_CTRL + 0x58 */
u32 cs6_stop; /* MMAP_CTRL + 0x5c */
u32 cs7_start; /* MMAP_CTRL + 0x60 */
u32 cs7_stop; /* MMAP_CTRL + 0x60 */
};
/* SDRAM control */
struct mpc52xx_sdram {
u32 mode; /* SDRAM + 0x00 */
u32 ctrl; /* SDRAM + 0x04 */
u32 config1; /* SDRAM + 0x08 */
u32 config2; /* SDRAM + 0x0c */
};
/* Interrupt controller */
struct mpc52xx_intr {
u32 per_mask; /* INTR + 0x00 */
u32 per_pri1; /* INTR + 0x04 */
u32 per_pri2; /* INTR + 0x08 */
u32 per_pri3; /* INTR + 0x0c */
u32 ctrl; /* INTR + 0x10 */
u32 main_mask; /* INTR + 0x14 */
u32 main_pri1; /* INTR + 0x18 */
u32 main_pri2; /* INTR + 0x1c */
u32 reserved1; /* INTR + 0x20 */
u32 enc_status; /* INTR + 0x24 */
u32 crit_status; /* INTR + 0x28 */
u32 main_status; /* INTR + 0x2c */
u32 per_status; /* INTR + 0x30 */
u32 reserved2; /* INTR + 0x34 */
u32 per_error; /* INTR + 0x38 */
};
/* SDMA */
struct mpc52xx_sdma {
u32 taskBar; /* SDMA + 0x00 */
u32 currentPointer; /* SDMA + 0x04 */
u32 endPointer; /* SDMA + 0x08 */
u32 variablePointer;/* SDMA + 0x0c */
u8 IntVect1; /* SDMA + 0x10 */
u8 IntVect2; /* SDMA + 0x11 */
u16 PtdCntrl; /* SDMA + 0x12 */
u32 IntPend; /* SDMA + 0x14 */
u32 IntMask; /* SDMA + 0x18 */
u16 tcr[16]; /* SDMA + 0x1c .. 0x3a */
u8 ipr[32]; /* SDMA + 0x3c .. 5b */
u32 cReqSelect; /* SDMA + 0x5c */
u32 task_size0; /* SDMA + 0x60 */
u32 task_size1; /* SDMA + 0x64 */
u32 MDEDebug; /* SDMA + 0x68 */
u32 ADSDebug; /* SDMA + 0x6c */
u32 Value1; /* SDMA + 0x70 */
u32 Value2; /* SDMA + 0x74 */
u32 Control; /* SDMA + 0x78 */
u32 Status; /* SDMA + 0x7c */
u32 PTDDebug; /* SDMA + 0x80 */
};
/* GPT */
struct mpc52xx_gpt {
u32 mode; /* GPTx + 0x00 */
u32 count; /* GPTx + 0x04 */
u32 pwm; /* GPTx + 0x08 */
u32 status; /* GPTx + 0X0c */
};
/* RTC */
struct mpc52xx_rtc {
u32 time_set; /* RTC + 0x00 */
u32 date_set; /* RTC + 0x04 */
u32 stopwatch; /* RTC + 0x08 */
u32 int_enable; /* RTC + 0x0c */
u32 time; /* RTC + 0x10 */
u32 date; /* RTC + 0x14 */
u32 stopwatch_intr; /* RTC + 0x18 */
u32 bus_error; /* RTC + 0x1c */
u32 dividers; /* RTC + 0x20 */
};
/* GPIO */
struct mpc52xx_gpio {
u32 port_config; /* GPIO + 0x00 */
u32 simple_gpioe; /* GPIO + 0x04 */
u32 simple_ode; /* GPIO + 0x08 */
u32 simple_ddr; /* GPIO + 0x0c */
u32 simple_dvo; /* GPIO + 0x10 */
u32 simple_ival; /* GPIO + 0x14 */
u8 outo_gpioe; /* GPIO + 0x18 */
u8 reserved1[3]; /* GPIO + 0x19 */
u8 outo_dvo; /* GPIO + 0x1c */
u8 reserved2[3]; /* GPIO + 0x1d */
u8 sint_gpioe; /* GPIO + 0x20 */
u8 reserved3[3]; /* GPIO + 0x21 */
u8 sint_ode; /* GPIO + 0x24 */
u8 reserved4[3]; /* GPIO + 0x25 */
u8 sint_ddr; /* GPIO + 0x28 */
u8 reserved5[3]; /* GPIO + 0x29 */
u8 sint_dvo; /* GPIO + 0x2c */
u8 reserved6[3]; /* GPIO + 0x2d */
u8 sint_inten; /* GPIO + 0x30 */
u8 reserved7[3]; /* GPIO + 0x31 */
u16 sint_itype; /* GPIO + 0x34 */
u16 reserved8; /* GPIO + 0x36 */
u8 gpio_control; /* GPIO + 0x38 */
u8 reserved9[3]; /* GPIO + 0x39 */
u8 sint_istat; /* GPIO + 0x3c */
u8 sint_ival; /* GPIO + 0x3d */
u8 bus_errs; /* GPIO + 0x3e */
u8 reserved10; /* GPIO + 0x3f */
};
#define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
#define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD 5
#define MPC52xx_GPIO_PCI_DIS (1<<15)
/* GPIO with WakeUp*/
struct mpc52xx_gpio_wkup {
u8 wkup_gpioe; /* GPIO_WKUP + 0x00 */
u8 reserved1[3]; /* GPIO_WKUP + 0x03 */
u8 wkup_ode; /* GPIO_WKUP + 0x04 */
u8 reserved2[3]; /* GPIO_WKUP + 0x05 */
u8 wkup_ddr; /* GPIO_WKUP + 0x08 */
u8 reserved3[3]; /* GPIO_WKUP + 0x09 */
u8 wkup_dvo; /* GPIO_WKUP + 0x0C */
u8 reserved4[3]; /* GPIO_WKUP + 0x0D */
u8 wkup_inten; /* GPIO_WKUP + 0x10 */
u8 reserved5[3]; /* GPIO_WKUP + 0x11 */
u8 wkup_iinten; /* GPIO_WKUP + 0x14 */
u8 reserved6[3]; /* GPIO_WKUP + 0x15 */
u16 wkup_itype; /* GPIO_WKUP + 0x18 */
u8 reserved7[2]; /* GPIO_WKUP + 0x1A */
u8 wkup_maste; /* GPIO_WKUP + 0x1C */
u8 reserved8[3]; /* GPIO_WKUP + 0x1D */
u8 wkup_ival; /* GPIO_WKUP + 0x20 */
u8 reserved9[3]; /* GPIO_WKUP + 0x21 */
u8 wkup_istat; /* GPIO_WKUP + 0x24 */
u8 reserved10[3]; /* GPIO_WKUP + 0x25 */
};
/* XLB Bus control */
struct mpc52xx_xlb {
u8 reserved[0x40];
u32 config; /* XLB + 0x40 */
u32 version; /* XLB + 0x44 */
u32 status; /* XLB + 0x48 */
u32 int_enable; /* XLB + 0x4c */
u32 addr_capture; /* XLB + 0x50 */
u32 bus_sig_capture; /* XLB + 0x54 */
u32 addr_timeout; /* XLB + 0x58 */
u32 data_timeout; /* XLB + 0x5c */
u32 bus_act_timeout; /* XLB + 0x60 */
u32 master_pri_enable; /* XLB + 0x64 */
u32 master_priority; /* XLB + 0x68 */
u32 base_address; /* XLB + 0x6c */
u32 snoop_window; /* XLB + 0x70 */
};
#define MPC52xx_XLB_CFG_SNOOP (1 << 15)
/* Clock Distribution control */
struct mpc52xx_cdm {
u32 jtag_id; /* CDM + 0x00 reg0 read only */
u32 rstcfg; /* CDM + 0x04 reg1 read only */
u32 breadcrumb; /* CDM + 0x08 reg2 */
u8 mem_clk_sel; /* CDM + 0x0c reg3 byte0 */
u8 xlb_clk_sel; /* CDM + 0x0d reg3 byte1 read only */
u8 ipb_clk_sel; /* CDM + 0x0e reg3 byte2 */
u8 pci_clk_sel; /* CDM + 0x0f reg3 byte3 */
u8 ext_48mhz_en; /* CDM + 0x10 reg4 byte0 */
u8 fd_enable; /* CDM + 0x11 reg4 byte1 */
u16 fd_counters; /* CDM + 0x12 reg4 byte2,3 */
u32 clk_enables; /* CDM + 0x14 reg5 */
u8 osc_disable; /* CDM + 0x18 reg6 byte0 */
u8 reserved0[3]; /* CDM + 0x19 reg6 byte1,2,3 */
u8 ccs_sleep_enable; /* CDM + 0x1c reg7 byte0 */
u8 osc_sleep_enable; /* CDM + 0x1d reg7 byte1 */
u8 reserved1; /* CDM + 0x1e reg7 byte2 */
u8 ccs_qreq_test; /* CDM + 0x1f reg7 byte3 */
u8 soft_reset; /* CDM + 0x20 u8 byte0 */
u8 no_ckstp; /* CDM + 0x21 u8 byte0 */
u8 reserved2[2]; /* CDM + 0x22 u8 byte1,2,3 */
u8 pll_lock; /* CDM + 0x24 reg9 byte0 */
u8 pll_looselock; /* CDM + 0x25 reg9 byte1 */
u8 pll_sm_lockwin; /* CDM + 0x26 reg9 byte2 */
u8 reserved3; /* CDM + 0x27 reg9 byte3 */
u16 reserved4; /* CDM + 0x28 reg10 byte0,1 */
u16 mclken_div_psc1; /* CDM + 0x2a reg10 byte2,3 */
u16 reserved5; /* CDM + 0x2c reg11 byte0,1 */
u16 mclken_div_psc2; /* CDM + 0x2e reg11 byte2,3 */
u16 reserved6; /* CDM + 0x30 reg12 byte0,1 */
u16 mclken_div_psc3; /* CDM + 0x32 reg12 byte2,3 */
u16 reserved7; /* CDM + 0x34 reg13 byte0,1 */
u16 mclken_div_psc6; /* CDM + 0x36 reg13 byte2,3 */
};
#endif /* __ASSEMBLY__ */
/* ========================================================================= */
/* Prototypes for MPC52xx syslib */
/* ========================================================================= */
#ifndef __ASSEMBLY__
extern void mpc52xx_init_irq(void);
extern int mpc52xx_get_irq(struct pt_regs *regs);
extern unsigned long mpc52xx_find_end_of_memory(void);
extern void mpc52xx_set_bat(void);
extern void mpc52xx_map_io(void);
extern void mpc52xx_restart(char *cmd);
extern void mpc52xx_halt(void);
extern void mpc52xx_power_off(void);
extern void mpc52xx_progress(char *s, unsigned short hex);
extern void mpc52xx_calibrate_decr(void);
extern void mpc52xx_add_board_devices(struct ocp_def board_ocp[]);
#endif /* __ASSEMBLY__ */
/* ========================================================================= */
/* Platform configuration */
/* ========================================================================= */
/* The U-Boot platform information struct */
extern bd_t __res;
/* Platform options */
#if defined(CONFIG_LITE5200)
#include <platforms/lite5200.h>
#endif
#endif /* __ASM_MPC52xx_H__ */

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/*
* include/asm-ppc/mpc52xx_psc.h
*
* Definitions of consts/structs to drive the Freescale MPC52xx OnChip
* PSCs. Theses are shared between multiple drivers since a PSC can be
* UART, AC97, IR, I2S, ... So this header is in asm-ppc.
*
*
* Maintainer : Sylvain Munaut <tnt@246tNt.com>
*
* Based/Extracted from some header of the 2.4 originally written by
* Dale Farnsworth <dfarnsworth@mvista.com>
*
* Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
* Copyright (C) 2003 MontaVista, Software, Inc.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef __ASM_MPC52xx_PSC_H__
#define __ASM_MPC52xx_PSC_H__
#include <asm/types.h>
/* Max number of PSCs */
#define MPC52xx_PSC_MAXNUM 6
/* Programmable Serial Controller (PSC) status register bits */
#define MPC52xx_PSC_SR_CDE 0x0080
#define MPC52xx_PSC_SR_RXRDY 0x0100
#define MPC52xx_PSC_SR_RXFULL 0x0200
#define MPC52xx_PSC_SR_TXRDY 0x0400
#define MPC52xx_PSC_SR_TXEMP 0x0800
#define MPC52xx_PSC_SR_OE 0x1000
#define MPC52xx_PSC_SR_PE 0x2000
#define MPC52xx_PSC_SR_FE 0x4000
#define MPC52xx_PSC_SR_RB 0x8000
/* PSC Command values */
#define MPC52xx_PSC_RX_ENABLE 0x0001
#define MPC52xx_PSC_RX_DISABLE 0x0002
#define MPC52xx_PSC_TX_ENABLE 0x0004
#define MPC52xx_PSC_TX_DISABLE 0x0008
#define MPC52xx_PSC_SEL_MODE_REG_1 0x0010
#define MPC52xx_PSC_RST_RX 0x0020
#define MPC52xx_PSC_RST_TX 0x0030
#define MPC52xx_PSC_RST_ERR_STAT 0x0040
#define MPC52xx_PSC_RST_BRK_CHG_INT 0x0050
#define MPC52xx_PSC_START_BRK 0x0060
#define MPC52xx_PSC_STOP_BRK 0x0070
/* PSC TxRx FIFO status bits */
#define MPC52xx_PSC_RXTX_FIFO_ERR 0x0040
#define MPC52xx_PSC_RXTX_FIFO_UF 0x0020
#define MPC52xx_PSC_RXTX_FIFO_OF 0x0010
#define MPC52xx_PSC_RXTX_FIFO_FR 0x0008
#define MPC52xx_PSC_RXTX_FIFO_FULL 0x0004
#define MPC52xx_PSC_RXTX_FIFO_ALARM 0x0002
#define MPC52xx_PSC_RXTX_FIFO_EMPTY 0x0001
/* PSC interrupt mask bits */
#define MPC52xx_PSC_IMR_TXRDY 0x0100
#define MPC52xx_PSC_IMR_RXRDY 0x0200
#define MPC52xx_PSC_IMR_DB 0x0400
#define MPC52xx_PSC_IMR_IPC 0x8000
/* PSC input port change bit */
#define MPC52xx_PSC_CTS 0x01
#define MPC52xx_PSC_DCD 0x02
#define MPC52xx_PSC_D_CTS 0x10
#define MPC52xx_PSC_D_DCD 0x20
/* PSC mode fields */
#define MPC52xx_PSC_MODE_5_BITS 0x00
#define MPC52xx_PSC_MODE_6_BITS 0x01
#define MPC52xx_PSC_MODE_7_BITS 0x02
#define MPC52xx_PSC_MODE_8_BITS 0x03
#define MPC52xx_PSC_MODE_BITS_MASK 0x03
#define MPC52xx_PSC_MODE_PAREVEN 0x00
#define MPC52xx_PSC_MODE_PARODD 0x04
#define MPC52xx_PSC_MODE_PARFORCE 0x08
#define MPC52xx_PSC_MODE_PARNONE 0x10
#define MPC52xx_PSC_MODE_ERR 0x20
#define MPC52xx_PSC_MODE_FFULL 0x40
#define MPC52xx_PSC_MODE_RXRTS 0x80
#define MPC52xx_PSC_MODE_ONE_STOP_5_BITS 0x00
#define MPC52xx_PSC_MODE_ONE_STOP 0x07
#define MPC52xx_PSC_MODE_TWO_STOP 0x0f
#define MPC52xx_PSC_RFNUM_MASK 0x01ff
/* Structure of the hardware registers */
struct mpc52xx_psc {
u8 mode; /* PSC + 0x00 */
u8 reserved0[3];
union { /* PSC + 0x04 */
u16 status;
u16 clock_select;
} sr_csr;
#define mpc52xx_psc_status sr_csr.status
#define mpc52xx_psc_clock_select sr_csr.clock_select
u16 reserved1;
u8 command; /* PSC + 0x08 */
u8 reserved2[3];
union { /* PSC + 0x0c */
u8 buffer_8;
u16 buffer_16;
u32 buffer_32;
} buffer;
#define mpc52xx_psc_buffer_8 buffer.buffer_8
#define mpc52xx_psc_buffer_16 buffer.buffer_16
#define mpc52xx_psc_buffer_32 buffer.buffer_32
union { /* PSC + 0x10 */
u8 ipcr;
u8 acr;
} ipcr_acr;
#define mpc52xx_psc_ipcr ipcr_acr.ipcr
#define mpc52xx_psc_acr ipcr_acr.acr
u8 reserved3[3];
union { /* PSC + 0x14 */
u16 isr;
u16 imr;
} isr_imr;
#define mpc52xx_psc_isr isr_imr.isr
#define mpc52xx_psc_imr isr_imr.imr
u16 reserved4;
u8 ctur; /* PSC + 0x18 */
u8 reserved5[3];
u8 ctlr; /* PSC + 0x1c */
u8 reserved6[3];
u16 ccr; /* PSC + 0x20 */
u8 reserved7[14];
u8 ivr; /* PSC + 0x30 */
u8 reserved8[3];
u8 ip; /* PSC + 0x34 */
u8 reserved9[3];
u8 op1; /* PSC + 0x38 */
u8 reserved10[3];
u8 op0; /* PSC + 0x3c */
u8 reserved11[3];
u32 sicr; /* PSC + 0x40 */
u8 ircr1; /* PSC + 0x44 */
u8 reserved13[3];
u8 ircr2; /* PSC + 0x44 */
u8 reserved14[3];
u8 irsdr; /* PSC + 0x4c */
u8 reserved15[3];
u8 irmdr; /* PSC + 0x50 */
u8 reserved16[3];
u8 irfdr; /* PSC + 0x54 */
u8 reserved17[3];
u16 rfnum; /* PSC + 0x58 */
u16 reserved18;
u16 tfnum; /* PSC + 0x5c */
u16 reserved19;
u32 rfdata; /* PSC + 0x60 */
u16 rfstat; /* PSC + 0x64 */
u16 reserved20;
u8 rfcntl; /* PSC + 0x68 */
u8 reserved21[5];
u16 rfalarm; /* PSC + 0x6e */
u16 reserved22;
u16 rfrptr; /* PSC + 0x72 */
u16 reserved23;
u16 rfwptr; /* PSC + 0x76 */
u16 reserved24;
u16 rflrfptr; /* PSC + 0x7a */
u16 reserved25;
u16 rflwfptr; /* PSC + 0x7e */
u32 tfdata; /* PSC + 0x80 */
u16 tfstat; /* PSC + 0x84 */
u16 reserved26;
u8 tfcntl; /* PSC + 0x88 */
u8 reserved27[5];
u16 tfalarm; /* PSC + 0x8e */
u16 reserved28;
u16 tfrptr; /* PSC + 0x92 */
u16 reserved29;
u16 tfwptr; /* PSC + 0x96 */
u16 reserved30;
u16 tflrfptr; /* PSC + 0x9a */
u16 reserved31;
u16 tflwfptr; /* PSC + 0x9e */
};
#endif /* __ASM_MPC52xx_PSC_H__ */

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/*
* Since there are many different boards and no standard configuration,
* we have a unique include file for each. Rather than change every
* file that has to include MPC8260 configuration, they all include
* this one and the configuration switching is done here.
*/
#ifdef __KERNEL__
#ifndef __ASM_PPC_MPC8260_H__
#define __ASM_PPC_MPC8260_H__
#include <linux/config.h>
#ifdef CONFIG_8260
#ifdef CONFIG_EST8260
#include <platforms/est8260.h>
#endif
#ifdef CONFIG_SBC82xx
#include <platforms/sbc82xx.h>
#endif
#ifdef CONFIG_SBS8260
#include <platforms/sbs8260.h>
#endif
#ifdef CONFIG_RPX8260
#include <platforms/rpx8260.h>
#endif
#ifdef CONFIG_WILLOW
#include <platforms/willow.h>
#endif
#ifdef CONFIG_TQM8260
#include <platforms/tqm8260.h>
#endif
#ifdef CONFIG_PQ2ADS
#include <platforms/pq2ads.h>
#endif
#ifdef CONFIG_PCI_8260
#include <syslib/m8260_pci.h>
#endif
/* Make sure the memory translation stuff is there if PCI not used.
*/
#ifndef _IO_BASE
#define _IO_BASE 0
#endif
#ifndef _ISA_MEM_BASE
#define _ISA_MEM_BASE 0
#endif
#ifndef PCI_DRAM_OFFSET
#define PCI_DRAM_OFFSET 0
#endif
/* Map 256MB I/O region
*/
#ifndef IO_PHYS_ADDR
#define IO_PHYS_ADDR 0xe0000000
#endif
#ifndef IO_VIRT_ADDR
#define IO_VIRT_ADDR IO_PHYS_ADDR
#endif
#ifndef __ASSEMBLY__
/* The "residual" data board information structure the boot loader
* hands to us.
*/
extern unsigned char __res[];
#endif
#endif /* CONFIG_8260 */
#endif /* !__ASM_PPC_MPC8260_H__ */
#endif /* __KERNEL__ */

51
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/* include/asm-ppc/mpc8260_pci9.h
*
* Undefine the PCI read* and in* macros so we can define them as functions
* that implement the workaround for the MPC8260 device erratum PCI 9.
*
* This header file should only be included at the end of include/asm-ppc/io.h
* and never included directly anywhere else.
*
* Author: andy_lowe@mvista.com
*
* 2003 (c) MontaVista Software, Inc. This file is licensed under
* the terms of the GNU General Public License version 2. This program
* is licensed "as is" without any warranty of any kind, whether express
* or implied.
*/
#ifndef _PPC_IO_H
#error "Do not include mpc8260_pci9.h directly."
#endif
#ifdef __KERNEL__
#ifndef __CONFIG_8260_PCI9_DEFS
#define __CONFIG_8260_PCI9_DEFS
#undef readb
#undef readw
#undef readl
#undef insb
#undef insw
#undef insl
#undef inb
#undef inw
#undef inl
#undef insw_ns
#undef insl_ns
#undef memcpy_fromio
extern int readb(volatile unsigned char *addr);
extern int readw(volatile unsigned short *addr);
extern unsigned readl(volatile unsigned *addr);
extern void insb(unsigned port, void *buf, int ns);
extern void insw(unsigned port, void *buf, int ns);
extern void insl(unsigned port, void *buf, int nl);
extern int inb(unsigned port);
extern int inw(unsigned port);
extern unsigned inl(unsigned port);
extern void insw_ns(unsigned port, void *buf, int ns);
extern void insl_ns(unsigned port, void *buf, int nl);
extern void *memcpy_fromio(void *dest, unsigned long src, size_t count);
#endif /* !__CONFIG_8260_PCI9_DEFS */
#endif /* __KERNEL__ */

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/*
* include/asm-ppc/mpc85xx.h
*
* MPC85xx definitions
*
* Maintainer: Kumar Gala <kumar.gala@freescale.com>
*
* Copyright 2004 Freescale Semiconductor, Inc
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifdef __KERNEL__
#ifndef __ASM_MPC85xx_H__
#define __ASM_MPC85xx_H__
#include <linux/config.h>
#include <asm/mmu.h>
#ifdef CONFIG_85xx
#ifdef CONFIG_MPC8540_ADS
#include <platforms/85xx/mpc8540_ads.h>
#endif
#ifdef CONFIG_MPC8555_CDS
#include <platforms/85xx/mpc8555_cds.h>
#endif
#ifdef CONFIG_MPC8560_ADS
#include <platforms/85xx/mpc8560_ads.h>
#endif
#ifdef CONFIG_SBC8560
#include <platforms/85xx/sbc8560.h>
#endif
#define _IO_BASE isa_io_base
#define _ISA_MEM_BASE isa_mem_base
#ifdef CONFIG_PCI
#define PCI_DRAM_OFFSET pci_dram_offset
#else
#define PCI_DRAM_OFFSET 0
#endif
/*
* The "residual" board information structure the boot loader passes
* into the kernel.
*/
extern unsigned char __res[];
/* Internal IRQs on MPC85xx OpenPIC */
/* Not all of these exist on all MPC85xx implementations */
#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
#define MPC85xx_OPENPIC_IRQ_OFFSET 64
#endif
/* The 32 internal sources */
#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
/* The 12 external interrupt lines */
#define MPC85xx_IRQ_EXT0 (32 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT1 (33 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT2 (34 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT3 (35 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT4 (36 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT5 (37 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT6 (38 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT7 (39 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT8 (40 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT9 (41 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT10 (42 + MPC85xx_OPENPIC_IRQ_OFFSET)
#define MPC85xx_IRQ_EXT11 (43 + MPC85xx_OPENPIC_IRQ_OFFSET)
/* Offset from CCSRBAR */
#define MPC85xx_CPM_OFFSET (0x80000)
#define MPC85xx_CPM_SIZE (0x40000)
#define MPC85xx_DMA_OFFSET (0x21000)
#define MPC85xx_DMA_SIZE (0x01000)
#define MPC85xx_ENET1_OFFSET (0x24000)
#define MPC85xx_ENET1_SIZE (0x01000)
#define MPC85xx_ENET2_OFFSET (0x25000)
#define MPC85xx_ENET2_SIZE (0x01000)
#define MPC85xx_ENET3_OFFSET (0x26000)
#define MPC85xx_ENET3_SIZE (0x01000)
#define MPC85xx_GUTS_OFFSET (0xe0000)
#define MPC85xx_GUTS_SIZE (0x01000)
#define MPC85xx_IIC1_OFFSET (0x03000)
#define MPC85xx_IIC1_SIZE (0x01000)
#define MPC85xx_OPENPIC_OFFSET (0x40000)
#define MPC85xx_OPENPIC_SIZE (0x40000)
#define MPC85xx_PCI1_OFFSET (0x08000)
#define MPC85xx_PCI1_SIZE (0x01000)
#define MPC85xx_PCI2_OFFSET (0x09000)
#define MPC85xx_PCI2_SIZE (0x01000)
#define MPC85xx_PERFMON_OFFSET (0xe1000)
#define MPC85xx_PERFMON_SIZE (0x01000)
#define MPC85xx_SEC2_OFFSET (0x30000)
#define MPC85xx_SEC2_SIZE (0x10000)
#define MPC85xx_UART0_OFFSET (0x04500)
#define MPC85xx_UART0_SIZE (0x00100)
#define MPC85xx_UART1_OFFSET (0x04600)
#define MPC85xx_UART1_SIZE (0x00100)
#define MPC85xx_CCSRBAR_SIZE (1024*1024)
/* Let modules/drivers get at CCSRBAR */
extern phys_addr_t get_ccsrbar(void);
#ifdef MODULE
#define CCSRBAR get_ccsrbar()
#else
#define CCSRBAR BOARD_CCSRBAR
#endif
#endif /* CONFIG_85xx */
#endif /* __ASM_MPC85xx_H__ */
#endif /* __KERNEL__ */

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/* This is the single file included by all MPC8xx build options.
* Since there are many different boards and no standard configuration,
* we have a unique include file for each. Rather than change every
* file that has to include MPC8xx configuration, they all include
* this one and the configuration switching is done here.
*/
#ifdef __KERNEL__
#ifndef __CONFIG_8xx_DEFS
#define __CONFIG_8xx_DEFS
#include <linux/config.h>
#ifdef CONFIG_8xx
#ifdef CONFIG_MBX
#include <platforms/mbx.h>
#endif
#ifdef CONFIG_FADS
#include <platforms/fads.h>
#endif
#ifdef CONFIG_RPXLITE
#include <platforms/rpxlite.h>
#endif
#ifdef CONFIG_BSEIP
#include <platforms/bseip.h>
#endif
#ifdef CONFIG_RPXCLASSIC
#include <platforms/rpxclassic.h>
#endif
#if defined(CONFIG_TQM8xxL)
#include <platforms/tqm8xx.h>
#endif
#if defined(CONFIG_SPD823TS)
#include <platforms/spd8xx.h>
#endif
#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
#include <platforms/ivms8.h>
#endif
#if defined(CONFIG_HERMES_PRO)
#include <platforms/hermes.h>
#endif
#if defined(CONFIG_IP860)
#include <platforms/ip860.h>
#endif
#if defined(CONFIG_LWMON)
#include <platforms/lwmon.h>
#endif
#if defined(CONFIG_PCU_E)
#include <platforms/pcu_e.h>
#endif
#if defined(CONFIG_CCM)
#include <platforms/ccm.h>
#endif
#if defined(CONFIG_LANTEC)
#include <platforms/lantec.h>
#endif
/* Currently, all 8xx boards that support a processor to PCI/ISA bridge
* use the same memory map.
*/
#if 0
#if defined(CONFIG_PCI) && defined(PCI_ISA_IO_ADDR)
#define _IO_BASE PCI_ISA_IO_ADDR
#define _ISA_MEM_BASE PCI_ISA_MEM_ADDR
#define PCI_DRAM_OFFSET 0x80000000
#else
#define _IO_BASE 0
#define _ISA_MEM_BASE 0
#define PCI_DRAM_OFFSET 0
#endif
#else
#if !defined(_IO_BASE) /* defined in board specific header */
#define _IO_BASE 0
#endif
#define _ISA_MEM_BASE 0
#define PCI_DRAM_OFFSET 0
#endif
#ifndef __ASSEMBLY__
/* The "residual" data board information structure the boot loader
* hands to us.
*/
extern unsigned char __res[];
struct pt_regs;
#endif /* !__ASSEMBLY__ */
#endif /* CONFIG_8xx */
#endif /* __CONFIG_8xx_DEFS */
#endif /* __KERNEL__ */

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#ifndef _PPC_MSGBUF_H
#define _PPC_MSGBUF_H
/*
* The msqid64_ds structure for the PPC architecture.
*/
struct msqid64_ds {
struct ipc64_perm msg_perm;
unsigned int __unused1;
__kernel_time_t msg_stime; /* last msgsnd time */
unsigned int __unused2;
__kernel_time_t msg_rtime; /* last msgrcv time */
unsigned int __unused3;
__kernel_time_t msg_ctime; /* last change time */
unsigned long msg_cbytes; /* current number of bytes on queue */
unsigned long msg_qnum; /* number of messages in queue */
unsigned long msg_qbytes; /* max number of bytes on queue */
__kernel_pid_t msg_lspid; /* pid of last msgsnd */
__kernel_pid_t msg_lrpid; /* last receive pid */
unsigned long __unused4;
unsigned long __unused5;
};
#endif /* _PPC_MSGBUF_H */

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/*
* include/asm-ppc/namei.h
* Adapted from include/asm-alpha/namei.h
*
* Included from fs/namei.c
*/
#ifdef __KERNEL__
#ifndef __PPC_NAMEI_H
#define __PPC_NAMEI_H
/* This dummy routine maybe changed to something useful
* for /usr/gnemul/ emulation stuff.
* Look at asm-sparc/namei.h for details.
*/
#define __emul_prefix() NULL
#endif /* __PPC_NAMEI_H */
#endif /* __KERNEL__ */

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/*
* PreP compliant NVRAM access
*/
#ifdef __KERNEL__
#ifndef _PPC_NVRAM_H
#define _PPC_NVRAM_H
#define NVRAM_AS0 0x74
#define NVRAM_AS1 0x75
#define NVRAM_DATA 0x77
/* RTC Offsets */
#define MOTO_RTC_SECONDS 0x1FF9
#define MOTO_RTC_MINUTES 0x1FFA
#define MOTO_RTC_HOURS 0x1FFB
#define MOTO_RTC_DAY_OF_WEEK 0x1FFC
#define MOTO_RTC_DAY_OF_MONTH 0x1FFD
#define MOTO_RTC_MONTH 0x1FFE
#define MOTO_RTC_YEAR 0x1FFF
#define MOTO_RTC_CONTROLA 0x1FF8
#define MOTO_RTC_CONTROLB 0x1FF9
/* PowerMac specific nvram stuffs */
enum {
pmac_nvram_OF, /* Open Firmware partition */
pmac_nvram_XPRAM, /* MacOS XPRAM partition */
pmac_nvram_NR /* MacOS Name Registry partition */
};
/* Return partition offset in nvram */
extern int pmac_get_partition(int partition);
/* Direct access to XPRAM on PowerMacs */
extern u8 pmac_xpram_read(int xpaddr);
extern void pmac_xpram_write(int xpaddr, u8 data);
/* Synchronize NVRAM */
extern void nvram_sync(void);
/* Normal access to NVRAM */
extern unsigned char nvram_read_byte(int i);
extern void nvram_write_byte(unsigned char c, int i);
/* Some offsets in XPRAM */
#define PMAC_XPRAM_MACHINE_LOC 0xe4
#define PMAC_XPRAM_SOUND_VOLUME 0x08
/* Machine location structure in PowerMac XPRAM */
struct pmac_machine_location {
unsigned int latitude; /* 2+30 bit Fractional number */
unsigned int longitude; /* 2+30 bit Fractional number */
unsigned int delta; /* mix of GMT delta and DLS */
};
/*
* /dev/nvram ioctls
*
* Note that PMAC_NVRAM_GET_OFFSET is still supported, but is
* definitely obsolete. Do not use it if you can avoid it
*/
#define OBSOLETE_PMAC_NVRAM_GET_OFFSET \
_IOWR('p', 0x40, int)
#define IOC_NVRAM_GET_OFFSET _IOWR('p', 0x42, int) /* Get NVRAM partition offset */
#define IOC_NVRAM_SYNC _IO('p', 0x43) /* Sync NVRAM image */
#endif
#endif /* __KERNEL__ */

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/*
* ocp.h
*
* (c) Benjamin Herrenschmidt (benh@kernel.crashing.org)
* Mipsys - France
*
* Derived from work (c) Armin Kuster akuster@pacbell.net
*
* Additional support and port to 2.6 LDM/sysfs by
* Matt Porter <mporter@kernel.crashing.org>
* Copyright 2003-2004 MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
* TODO: - Add get/put interface & fixup locking to provide same API for
* 2.4 and 2.5
* - Rework PM callbacks
*/
#ifdef __KERNEL__
#ifndef __OCP_H__
#define __OCP_H__
#include <linux/init.h>
#include <linux/list.h>
#include <linux/config.h>
#include <linux/devfs_fs_kernel.h>
#include <linux/device.h>
#include <asm/mmu.h>
#include <asm/ocp_ids.h>
#include <asm/rwsem.h>
#include <asm/semaphore.h>
#ifdef CONFIG_PPC_OCP
#define OCP_MAX_IRQS 7
#define MAX_EMACS 4
#define OCP_IRQ_NA -1 /* used when ocp device does not have an irq */
#define OCP_IRQ_MUL -2 /* used for ocp devices with multiply irqs */
#define OCP_NULL_TYPE -1 /* used to mark end of list */
#define OCP_CPM_NA 0 /* No Clock or Power Management avaliable */
#define OCP_PADDR_NA 0 /* No MMIO registers */
#define OCP_ANY_ID (~0)
#define OCP_ANY_INDEX -1
extern struct list_head ocp_devices;
extern struct rw_semaphore ocp_devices_sem;
struct ocp_device_id {
unsigned int vendor, function; /* Vendor and function ID or OCP_ANY_ID */
unsigned long driver_data; /* Data private to the driver */
};
/*
* Static definition of an OCP device.
*
* @vendor: Vendor code. It is _STRONGLY_ discouraged to use
* the vendor code as a way to match a unique device,
* though I kept that possibility open, you should
* really define different function codes for different
* device types
* @function: This is the function code for this device.
* @index: This index is used for mapping the Nth function of a
* given core. This is typically used for cross-driver
* matching, like looking for a given MAL or ZMII from
* an EMAC or for getting to the proper set of DCRs.
* Indices are no longer magically calculated based on
* structure ordering, they have to be actually coded
* into the ocp_def to avoid any possible confusion
* I _STRONGLY_ (again ? wow !) encourage anybody relying
* on index mapping to encode the "target" index in an
* associated structure pointed to by "additions", see
* how it's done for the EMAC driver.
* @paddr: Device physical address (may not mean anything...)
* @irq: Interrupt line for this device (TODO: think about making
* an array with this)
* @pm: Currently, contains the bitmask in CPMFR DCR for the device
* @additions: Optionally points to a function specific structure
* providing additional informations for a given device
* instance. It's currently used by the EMAC driver for MAL
* channel & ZMII port mapping among others.
* @show: Optionally points to a function specific structure
* providing a sysfs show routine for additions fields.
*/
struct ocp_def {
unsigned int vendor;
unsigned int function;
int index;
phys_addr_t paddr;
int irq;
unsigned long pm;
void *additions;
void (*show)(struct device *);
};
/* Struct for a given device instance */
struct ocp_device {
struct list_head link;
char name[80]; /* device name */
struct ocp_def *def; /* device definition */
void *drvdata; /* driver data for this device */
struct ocp_driver *driver;
u32 current_state; /* Current operating state. In ACPI-speak,
this is D0-D3, D0 being fully functional,
and D3 being off. */
struct device dev;
};
struct ocp_driver {
struct list_head node;
char *name;
const struct ocp_device_id *id_table; /* NULL if wants all devices */
int (*probe) (struct ocp_device *dev); /* New device inserted */
void (*remove) (struct ocp_device *dev); /* Device removed (NULL if not a hot-plug capable driver) */
int (*suspend) (struct ocp_device *dev, u32 state); /* Device suspended */
int (*resume) (struct ocp_device *dev); /* Device woken up */
struct device_driver driver;
};
#define to_ocp_dev(n) container_of(n, struct ocp_device, dev)
#define to_ocp_drv(n) container_of(n, struct ocp_driver, driver)
/* Similar to the helpers above, these manipulate per-ocp_dev
* driver-specific data. Currently stored as ocp_dev::ocpdev,
* a void pointer, but it is not present on older kernels.
*/
static inline void *
ocp_get_drvdata(struct ocp_device *pdev)
{
return pdev->drvdata;
}
static inline void
ocp_set_drvdata(struct ocp_device *pdev, void *data)
{
pdev->drvdata = data;
}
#if defined (CONFIG_PM)
/*
* This is right for the IBM 405 and 440 but will need to be
* generalized if the OCP stuff gets used on other processors.
*/
static inline void
ocp_force_power_off(struct ocp_device *odev)
{
mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm);
}
static inline void
ocp_force_power_on(struct ocp_device *odev)
{
mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm);
}
#else
#define ocp_force_power_off(x) (void)(x)
#define ocp_force_power_on(x) (void)(x)
#endif
/* Register/Unregister an OCP driver */
extern int ocp_register_driver(struct ocp_driver *drv);
extern void ocp_unregister_driver(struct ocp_driver *drv);
/* Build list of devices */
extern int ocp_early_init(void) __init;
/* Find a device by index */
extern struct ocp_device *ocp_find_device(unsigned int vendor, unsigned int function, int index);
/* Get a def by index */
extern struct ocp_def *ocp_get_one_device(unsigned int vendor, unsigned int function, int index);
/* Add a device by index */
extern int ocp_add_one_device(struct ocp_def *def);
/* Remove a device by index */
extern int ocp_remove_one_device(unsigned int vendor, unsigned int function, int index);
/* Iterate over devices and execute a routine */
extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg), void *arg);
/* Sysfs support */
#define OCP_SYSFS_ADDTL(type, format, name, field) \
static ssize_t \
show_##name##_##field(struct device *dev, char *buf) \
{ \
struct ocp_device *odev = to_ocp_dev(dev); \
type *add = odev->def->additions; \
\
return sprintf(buf, format, add->field); \
} \
static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
#ifdef CONFIG_IBM_OCP
#include <asm/ibm_ocp.h>
#endif
#ifdef CONFIG_FSL_OCP
#include <asm/fsl_ocp.h>
#endif
#endif /* CONFIG_PPC_OCP */
#endif /* __OCP_H__ */
#endif /* __KERNEL__ */

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/*
* ocp_ids.h
*
* OCP device ids based on the ideas from PCI
*
* The numbers below are almost completely arbitrary, and in fact
* strings might work better. -- paulus
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
/*
* Vender device
* [xxxx] [xxxx]
*
* Keep in order, please
*/
/* Vendor IDs 0x0001 - 0xFFFF copied from pci_ids.h */
#define OCP_VENDOR_INVALID 0x0000
#define OCP_VENDOR_ARM 0x0004
#define OCP_VENDOR_FREESCALE 0x1057
#define OCP_VENDOR_IBM 0x1014
#define OCP_VENDOR_MOTOROLA OCP_VENDOR_FREESCALE
#define OCP_VENDOR_XILINX 0x10ee
#define OCP_VENDOR_UNKNOWN 0xFFFF
/* device identification */
/* define type */
#define OCP_FUNC_INVALID 0x0000
/* system 0x0001 - 0x001F */
/* Timers 0x0020 - 0x002F */
/* Serial 0x0030 - 0x006F*/
#define OCP_FUNC_16550 0x0031
#define OCP_FUNC_IIC 0x0032
#define OCP_FUNC_USB 0x0033
#define OCP_FUNC_PSC_UART 0x0034
/* Memory devices 0x0090 - 0x009F */
#define OCP_FUNC_MAL 0x0090
#define OCP_FUNC_DMA 0x0091
/* Display 0x00A0 - 0x00AF */
/* Sound 0x00B0 - 0x00BF */
/* Mass Storage 0x00C0 - 0xxCF */
#define OCP_FUNC_IDE 0x00C0
/* Misc 0x00D0 - 0x00DF*/
#define OCP_FUNC_GPIO 0x00D0
#define OCP_FUNC_ZMII 0x00D1
#define OCP_FUNC_PERFMON 0x00D2 /* Performance Monitor */
#define OCP_FUNC_RGMII 0x00D3
#define OCP_FUNC_TAH 0x00D4
#define OCP_FUNC_SEC2 0x00D5 /* Crypto/Security 2.0 */
/* Network 0x0200 - 0x02FF */
#define OCP_FUNC_EMAC 0x0200
#define OCP_FUNC_GFAR 0x0201 /* TSEC & FEC */
/* Bridge devices 0xE00 - 0xEFF */
#define OCP_FUNC_OPB 0x0E00
#define OCP_FUNC_UNKNOWN 0xFFFF

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#ifndef __OF_DEVICE_H__
#define __OF_DEVICE_H__
#include <linux/device.h>
#include <asm/prom.h>
/*
* The of_platform_bus_type is a bus type used by drivers that do not
* attach to a macio or similar bus but still use OF probing
* mecanism
*/
extern struct bus_type of_platform_bus_type;
/*
* The of_device is a kind of "base class" that is a superset of
* struct device for use by devices attached to an OF node and
* probed using OF properties
*/
struct of_device
{
struct device_node *node; /* OF device node */
u64 dma_mask; /* DMA mask */
struct device dev; /* Generic device interface */
};
#define to_of_device(d) container_of(d, struct of_device, dev)
/*
* Struct used for matching a device
*/
struct of_match
{
char *name;
char *type;
char *compatible;
void *data;
};
#define OF_ANY_MATCH ((char *)-1L)
extern const struct of_match *of_match_device(
const struct of_match *matches, const struct of_device *dev);
extern struct of_device *of_dev_get(struct of_device *dev);
extern void of_dev_put(struct of_device *dev);
/*
* An of_platform_driver driver is attached to a basic of_device on
* the "platform bus" (of_platform_bus_type)
*/
struct of_platform_driver
{
char *name;
struct of_match *match_table;
struct module *owner;
int (*probe)(struct of_device* dev, const struct of_match *match);
int (*remove)(struct of_device* dev);
int (*suspend)(struct of_device* dev, u32 state);
int (*resume)(struct of_device* dev);
int (*shutdown)(struct of_device* dev);
struct device_driver driver;
};
#define to_of_platform_driver(drv) container_of(drv,struct of_platform_driver, driver)
extern int of_register_driver(struct of_platform_driver *drv);
extern void of_unregister_driver(struct of_platform_driver *drv);
extern int of_device_register(struct of_device *ofdev);
extern void of_device_unregister(struct of_device *ofdev);
extern struct of_device *of_platform_device_create(struct device_node *np, const char *bus_id);
extern void of_release_dev(struct device *dev);
#endif /* __OF_DEVICE_H__ */

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/*
* ohare.h: definitions for using the "O'Hare" I/O controller chip.
*
* Copyright (C) 1997 Paul Mackerras.
*
* BenH: Changed to match those of heathrow (but not all of them). Please
* check if I didn't break anything (especially the media bay).
*/
/* offset from ohare base for feature control register */
#define OHARE_MBCR 0x34
#define OHARE_FCR 0x38
/*
* Bits in feature control register.
* These were mostly derived by experiment on a powerbook 3400
* and may differ for other machines.
*/
#define OH_SCC_RESET 1
#define OH_BAY_POWER_N 2 /* a guess */
#define OH_BAY_PCI_ENABLE 4 /* a guess */
#define OH_BAY_IDE_ENABLE 8
#define OH_BAY_FLOPPY_ENABLE 0x10
#define OH_IDE0_ENABLE 0x20
#define OH_IDE0_RESET_N 0x40 /* a guess */
#define OH_BAY_DEV_MASK 0x1c
#define OH_BAY_RESET_N 0x80
#define OH_IOBUS_ENABLE 0x100 /* IOBUS seems to be IDE */
#define OH_SCC_ENABLE 0x200
#define OH_MESH_ENABLE 0x400
#define OH_FLOPPY_ENABLE 0x800
#define OH_SCCA_IO 0x4000
#define OH_SCCB_IO 0x8000
#define OH_VIA_ENABLE 0x10000 /* Is apparently wrong, to be verified */
#define OH_IDE1_RESET_N 0x800000
/*
* Bits to set in the feature control register on PowerBooks.
*/
#define PBOOK_FEATURES (OH_IDE_ENABLE | OH_SCC_ENABLE | \
OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO)
/*
* A magic value to put into the feature control register of the
* "ohare" I/O controller on Starmaxes to enable the IDE CD interface.
* Contributed by Harry Eaton.
*/
#define STARMAX_FEATURES 0xbeff7a

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/*
* include/asm-ppc/open_pic.h -- OpenPIC Interrupt Handling
*
* Copyright (C) 1997 Geert Uytterhoeven
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
*
*/
#ifndef _PPC_KERNEL_OPEN_PIC_H
#define _PPC_KERNEL_OPEN_PIC_H
#include <linux/config.h>
#include <linux/irq.h>
#define OPENPIC_SIZE 0x40000
/*
* Non-offset'ed vector numbers
*/
#define OPENPIC_VEC_TIMER 110 /* and up */
#define OPENPIC_VEC_IPI 118 /* and up */
#define OPENPIC_VEC_SPURIOUS 255
/* OpenPIC IRQ controller structure */
extern struct hw_interrupt_type open_pic;
/* OpenPIC IPI controller structure */
#ifdef CONFIG_SMP
extern struct hw_interrupt_type open_pic_ipi;
#endif /* CONFIG_SMP */
extern u_int OpenPIC_NumInitSenses;
extern u_char *OpenPIC_InitSenses;
extern void* OpenPIC_Addr;
extern int epic_serial_mode;
/* Exported functions */
extern void openpic_set_sources(int first_irq, int num_irqs, void *isr);
extern void openpic_init(int linux_irq_offset);
extern void openpic_init_nmi_irq(u_int irq);
extern void openpic_hookup_cascade(u_int irq, char *name,
int (*cascade_fn)(struct pt_regs *));
extern u_int openpic_irq(void);
extern void openpic_eoi(void);
extern void openpic_request_IPIs(void);
extern void do_openpic_setup_cpu(void);
extern int openpic_get_irq(struct pt_regs *regs);
extern void openpic_reset_processor_phys(u_int cpumask);
extern void openpic_setup_ISU(int isu_num, unsigned long addr);
extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
extern void smp_openpic_message_pass(int target, int msg, unsigned long data,
int wait);
extern void openpic_set_k2_cascade(int irq);
extern void openpic_set_priority(u_int pri);
extern inline int openpic_to_irq(int irq)
{
/* IRQ 0 usually means 'disabled'.. don't mess with it
* exceptions to this (sandpoint maybe?)
* shouldn't use openpic_to_irq
*/
if (irq != 0){
return irq += NUM_8259_INTERRUPTS;
} else {
return 0;
}
}
/* Support for second openpic on G5 macs */
// FIXME: To be replaced by sane cascaded controller management */
#define PMAC_OPENPIC2_OFFSET 128
#define OPENPIC2_VEC_TIMER 110 /* and up */
#define OPENPIC2_VEC_IPI 118 /* and up */
#define OPENPIC2_VEC_SPURIOUS 127
extern void* OpenPIC2_Addr;
/* Exported functions */
extern void openpic2_set_sources(int first_irq, int num_irqs, void *isr);
extern void openpic2_init(int linux_irq_offset);
extern void openpic2_init_nmi_irq(u_int irq);
extern u_int openpic2_irq(void);
extern void openpic2_eoi(void);
extern int openpic2_get_irq(struct pt_regs *regs);
extern void openpic2_setup_ISU(int isu_num, unsigned long addr);
#endif /* _PPC_KERNEL_OPEN_PIC_H */

167
extra/linux-2.6.10/include/asm-ppc/page.h Normal file
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#ifndef _PPC_PAGE_H
#define _PPC_PAGE_H
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
#define PAGE_SIZE (1UL << PAGE_SHIFT)
/*
* Subtle: this is an int (not an unsigned long) and so it
* gets extended to 64 bits the way want (i.e. with 1s). -- paulus
*/
#define PAGE_MASK (~((1 << PAGE_SHIFT) - 1))
#ifdef __KERNEL__
#include <linux/config.h>
/* This must match what is in arch/ppc/Makefile */
#define PAGE_OFFSET CONFIG_KERNEL_START
#define KERNELBASE PAGE_OFFSET
#ifndef __ASSEMBLY__
/*
* The basic type of a PTE - 64 bits for those CPUs with > 32 bit
* physical addressing. For now this just the IBM PPC440.
*/
#ifdef CONFIG_PTE_64BIT
typedef unsigned long long pte_basic_t;
#define PTE_SHIFT (PAGE_SHIFT - 3) /* 512 ptes per page */
#define PTE_FMT "%16Lx"
#else
typedef unsigned long pte_basic_t;
#define PTE_SHIFT (PAGE_SHIFT - 2) /* 1024 ptes per page */
#define PTE_FMT "%.8lx"
#endif
#undef STRICT_MM_TYPECHECKS
#ifdef STRICT_MM_TYPECHECKS
/*
* These are used to make use of C type-checking..
*/
typedef struct { pte_basic_t pte; } pte_t;
typedef struct { unsigned long pmd; } pmd_t;
typedef struct { unsigned long pgd; } pgd_t;
typedef struct { unsigned long pgprot; } pgprot_t;
#define pte_val(x) ((x).pte)
#define pmd_val(x) ((x).pmd)
#define pgd_val(x) ((x).pgd)
#define pgprot_val(x) ((x).pgprot)
#define __pte(x) ((pte_t) { (x) } )
#define __pmd(x) ((pmd_t) { (x) } )
#define __pgd(x) ((pgd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
#else
/*
* .. while these make it easier on the compiler
*/
typedef pte_basic_t pte_t;
typedef unsigned long pmd_t;
typedef unsigned long pgd_t;
typedef unsigned long pgprot_t;
#define pte_val(x) (x)
#define pmd_val(x) (x)
#define pgd_val(x) (x)
#define pgprot_val(x) (x)
#define __pte(x) (x)
#define __pmd(x) (x)
#define __pgd(x) (x)
#define __pgprot(x) (x)
#endif
/* align addr on a size boundary - adjust address up if needed -- Cort */
#define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1)))
/* to align the pointer to the (next) page boundary */
#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
struct page;
extern void clear_pages(void *page, int order);
static inline void clear_page(void *page) { clear_pages(page, 0); }
extern void copy_page(void *to, void *from);
extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg);
extern void copy_user_page(void *to, void *from, unsigned long vaddr,
struct page *pg);
#ifndef CONFIG_APUS
#define PPC_MEMSTART 0
#define PPC_PGSTART 0
#define PPC_MEMOFFSET PAGE_OFFSET
#else
extern unsigned long ppc_memstart;
extern unsigned long ppc_pgstart;
extern unsigned long ppc_memoffset;
#define PPC_MEMSTART ppc_memstart
#define PPC_PGSTART ppc_pgstart
#define PPC_MEMOFFSET ppc_memoffset
#endif
#if defined(CONFIG_APUS) && !defined(MODULE)
/* map phys->virtual and virtual->phys for RAM pages */
static inline unsigned long ___pa(unsigned long v)
{
unsigned long p;
asm volatile ("1: addis %0, %1, %2;"
".section \".vtop_fixup\",\"aw\";"
".align 1;"
".long 1b;"
".previous;"
: "=r" (p)
: "b" (v), "K" (((-PAGE_OFFSET) >> 16) & 0xffff));
return p;
}
static inline void* ___va(unsigned long p)
{
unsigned long v;
asm volatile ("1: addis %0, %1, %2;"
".section \".ptov_fixup\",\"aw\";"
".align 1;"
".long 1b;"
".previous;"
: "=r" (v)
: "b" (p), "K" (((PAGE_OFFSET) >> 16) & 0xffff));
return (void*) v;
}
#else
#define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET)
#define ___va(paddr) ((paddr)+PPC_MEMOFFSET)
#endif
#define __pa(x) ___pa((unsigned long)(x))
#define __va(x) ((void *)(___va((unsigned long)(x))))
#define pfn_to_page(pfn) (mem_map + ((pfn) - PPC_PGSTART))
#define page_to_pfn(page) ((unsigned long)((page) - mem_map) + PPC_PGSTART)
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
#define page_to_virt(page) __va(page_to_pfn(page) << PAGE_SHIFT)
#define pfn_valid(pfn) (((pfn) - PPC_PGSTART) < max_mapnr)
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
/* Pure 2^n version of get_order */
extern __inline__ int get_order(unsigned long size)
{
int lz;
size = (size-1) >> PAGE_SHIFT;
asm ("cntlzw %0,%1" : "=r" (lz) : "r" (size));
return 32 - lz;
}
#endif /* __ASSEMBLY__ */
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
#endif /* __KERNEL__ */
#endif /* _PPC_PAGE_H */

22
extra/linux-2.6.10/include/asm-ppc/param.h Normal file
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#ifndef _ASM_PPC_PARAM_H
#define _ASM_PPC_PARAM_H
#ifdef __KERNEL__
#define HZ 1000 /* internal timer frequency */
#define USER_HZ 100 /* for user interfaces in "ticks" */
#define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */
#endif /* __KERNEL__ */
#ifndef HZ
#define HZ 100
#endif
#define EXEC_PAGESIZE 4096
#ifndef NOGROUP
#define NOGROUP (-1)
#endif
#define MAXHOSTNAMELEN 64 /* max length of hostname */
#endif

18
extra/linux-2.6.10/include/asm-ppc/parport.h Normal file
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/*
* parport.h: platform-specific PC-style parport initialisation
*
* Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
*
* This file should only be included by drivers/parport/parport_pc.c.
*/
#ifndef _ASM_PPC_PARPORT_H
#define _ASM_PPC_PARPORT_H
static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
{
return parport_pc_find_isa_ports (autoirq, autodma);
}
#endif /* !(_ASM_PPC_PARPORT_H) */

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