417 lines
11 KiB
ArmAsm
417 lines
11 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/head.S
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*
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* Copyright (C) 1994-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Kernel startup code for all 32-bit CPUs
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*/
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#include <linux/config.h>
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#include <linux/linkage.h>
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#include <linux/init.h>
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#include <asm/assembler.h>
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#include <asm/mach-types.h>
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#include <asm/procinfo.h>
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#include <asm/ptrace.h>
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#include <asm/constants.h>
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#ifndef CONFIG_XIP_KERNEL
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/*
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* We place the page tables 16K below TEXTADDR. Therefore, we must make sure
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* that TEXTADDR is correctly set. Currently, we expect the least significant
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* 16 bits to be 0x8000, but we could probably relax this restriction to
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* TEXTADDR >= PAGE_OFFSET + 0x4000
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*
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* Note that swapper_pg_dir is the virtual address of the page tables, and
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* pgtbl gives us a position-independent reference to these tables. We can
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* do this because stext == TEXTADDR
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*/
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#if (TEXTADDR & 0xffff) != 0x8000
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#error TEXTADDR must start at 0xXXXX8000
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#endif
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.globl swapper_pg_dir
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.equ swapper_pg_dir, TEXTADDR - 0x4000
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.macro pgtbl, rd, phys
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adr \rd, stext
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sub \rd, \rd, #0x4000
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.endm
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#else
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/*
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* XIP Kernel:
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*
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* We place the page tables 16K below DATAADDR. Therefore, we must make sure
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* that DATAADDR is correctly set. Currently, we expect the least significant
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* 16 bits to be 0x8000, but we could probably relax this restriction to
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* DATAADDR >= PAGE_OFFSET + 0x4000
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*
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* Note that pgtbl is meant to return the physical address of swapper_pg_dir.
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* We can't make it relative to the kernel position in this case since
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* the kernel can physically be anywhere.
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*/
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#if (DATAADDR & 0xffff) != 0x8000
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#error DATAADDR must start at 0xXXXX8000
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#endif
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.globl swapper_pg_dir
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.equ swapper_pg_dir, DATAADDR - 0x4000
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.macro pgtbl, rd, phys
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ldr \rd, =((DATAADDR - 0x4000) - VIRT_OFFSET)
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add \rd, \rd, \phys
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.endm
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#endif
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/*
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* Kernel startup entry point.
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* ---------------------------
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*
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* This is normally called from the decompressor code. The requirements
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* are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
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* r1 = machine nr.
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*
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* This code is mostly position independent, so if you link the kernel at
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* 0xc0008000, you call this at __pa(0xc0008000).
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*
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* See linux/arch/arm/tools/mach-types for the complete list of machine
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* numbers for r1.
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*
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* We're trying to keep crap to a minimum; DO NOT add any machine specific
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* crap here - that's what the boot loader (or in extreme, well justified
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* circumstances, zImage) is for.
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*/
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__INIT
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.type stext, #function
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ENTRY(stext)
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mov r12, r0
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mov r0, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ make sure svc mode
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msr cpsr_c, r0 @ and all irqs disabled
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bl __lookup_processor_type
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teq r10, #0 @ invalid processor?
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moveq r0, #'p' @ yes, error 'p'
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beq __error
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bl __lookup_architecture_type
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teq r7, #0 @ invalid architecture?
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moveq r0, #'a' @ yes, error 'a'
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beq __error
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bl __create_page_tables
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/*
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* The following calls CPU specific code in a position independent
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* manner. See arch/arm/mm/proc-*.S for details. r10 = base of
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* xxx_proc_info structure selected by __lookup_architecture_type
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* above. On return, the CPU will be ready for the MMU to be
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* turned on, and r0 will hold the CPU control register value.
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*/
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adr lr, __turn_mmu_on @ return (PIC) address
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add pc, r10, #12
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.type __switch_data, %object
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__switch_data:
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.long __mmap_switched
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.long __data_loc @ r2
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.long __data_start @ r3
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.long __bss_start @ r4
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.long _end @ r5
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.long processor_id @ r6
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.long __machine_arch_type @ r7
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.long cr_alignment @ r8
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.long init_thread_union+8192 @ sp
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/*
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* Enable the MMU. This completely changes the structure of the visible
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* memory space. You will not be able to trace execution through this.
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* If you have an enquiry about this, *please* check the linux-arm-kernel
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* mailing list archives BEFORE sending another post to the list.
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*/
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.align 5
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.type __turn_mmu_on, %function
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__turn_mmu_on:
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ldr lr, __switch_data
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#ifdef CONFIG_ALIGNMENT_TRAP
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orr r0, r0, #2 @ ...........A.
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#endif
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mcr p15, 0, r0, c1, c0, 0 @ write control reg
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mrc p15, 0, r3, c0, c0, 0 @ read id reg
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mov r3, r3
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mov r3, r3
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mov pc, lr
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/*
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* The following fragment of code is executed with the MMU on, and uses
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* absolute addresses; this is not position independent.
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*
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* r0 = processor control register
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* r1 = machine ID
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* r9 = processor ID
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* r12 = value of r0 when kernel was called (currently always zero)
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*/
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.align 5
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__mmap_switched:
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adr r2, __switch_data + 4
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ldmia r2, {r2, r3, r4, r5, r6, r7, r8, sp}
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cmp r2, r3 @ Copy data segment if needed
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1: cmpne r3, r4
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ldrne fp, [r2], #4
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strne fp, [r3], #4
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bne 1b
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mov fp, #0 @ Clear BSS (and zero fp)
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1: cmp r4, r5
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strcc fp, [r4],#4
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bcc 1b
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str r9, [r6] @ Save processor ID
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str r1, [r7] @ Save machine type
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bic r2, r0, #2 @ Clear 'A' bit
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stmia r8, {r0, r2} @ Save control register values
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b start_kernel
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/*
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* Setup the initial page tables. We only setup the barest
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* amount which are required to get the kernel running, which
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* generally means mapping in the kernel code.
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*
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* r5 = physical address of start of RAM
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* r6 = physical IO address
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* r7 = byte offset into page tables for IO
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* r8 = page table flags
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*/
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__create_page_tables:
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pgtbl r4, r5 @ page table address
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/*
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* Clear the 16K level 1 swapper page table
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*/
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mov r0, r4
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mov r3, #0
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add r2, r0, #0x4000
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1: str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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teq r0, r2
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bne 1b
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/*
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* Create identity mapping for first MB of kernel to
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* cater for the MMU enable. This identity mapping
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* will be removed by paging_init(). We use our current program
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* counter to determine corresponding section base address.
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*/
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mov r2, pc, lsr #20 @ start of kernel section
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add r3, r8, r2, lsl #20 @ flags + kernel base
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str r3, [r4, r2, lsl #2] @ identity mapping
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/*
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* Now setup the pagetables for our kernel direct
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* mapped region. We round TEXTADDR down to the
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* nearest megabyte boundary. It is assumed that
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* the kernel fits within 4 contigous 1MB sections.
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*/
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add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
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str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
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add r3, r3, #1 << 20
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str r3, [r0, #4]! @ KERNEL + 1MB
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add r3, r3, #1 << 20
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str r3, [r0, #4]! @ KERNEL + 2MB
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add r3, r3, #1 << 20
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str r3, [r0, #4] @ KERNEL + 3MB
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/*
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* Then map first 1MB of ram in case it contains our boot params.
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*/
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add r0, r4, #VIRT_OFFSET >> 18
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add r2, r5, r8
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str r2, [r0]
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#ifdef CONFIG_XIP_KERNEL
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/*
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* Map some ram to cover our .data and .bss areas.
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* Mapping 3MB should be plenty.
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*/
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sub r3, r4, r5
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mov r3, r3, lsr #20
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add r0, r0, r3, lsl #2
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add r2, r2, r3, lsl #20
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str r2, [r0], #4
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add r2, r2, #(1 << 20)
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str r2, [r0], #4
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add r2, r2, #(1 << 20)
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str r2, [r0]
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#endif
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bic r8, r8, #0x0c @ turn off cacheable
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@ and bufferable bits
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#ifdef CONFIG_DEBUG_LL
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/*
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* Map in IO space for serial debugging.
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* This allows debug messages to be output
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* via a serial console before paging_init.
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*/
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add r0, r4, r7
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rsb r3, r7, #0x4000 @ PTRS_PER_PGD*sizeof(long)
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cmp r3, #0x0800
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addge r2, r0, #0x0800
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addlt r2, r0, r3
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orr r3, r6, r8
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1: str r3, [r0], #4
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add r3, r3, #1 << 20
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teq r0, r2
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bne 1b
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#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
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/*
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* If we're using the NetWinder, we need to map in
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* the 16550-type serial port for the debug messages
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*/
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teq r1, #MACH_TYPE_NETWINDER
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teqne r1, #MACH_TYPE_CATS
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bne 1f
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add r0, r4, #0x3fc0 @ ff000000
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mov r3, #0x7c000000
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orr r3, r3, r8
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str r3, [r0], #4
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add r3, r3, #1 << 20
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str r3, [r0], #4
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1:
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#endif
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#endif
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#ifdef CONFIG_ARCH_RPC
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/*
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* Map in screen at 0x02000000 & SCREEN2_BASE
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* Similar reasons here - for debug. This is
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* only for Acorn RiscPC architectures.
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*/
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add r0, r4, #0x80 @ 02000000
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mov r3, #0x02000000
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orr r3, r3, r8
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str r3, [r0]
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add r0, r4, #0x3600 @ d8000000
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str r3, [r0]
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#endif
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mov pc, lr
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.ltorg
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/*
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* Exception handling. Something went wrong and we can't proceed. We
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* ought to tell the user, but since we don't have any guarantee that
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* we're even running on the right architecture, we do virtually nothing.
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*
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* r0 = ascii error character:
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* a = invalid architecture
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* p = invalid processor
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* i = invalid calling convention
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*
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* Generally, only serious errors cause this.
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*/
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__error:
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#ifdef CONFIG_DEBUG_LL
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mov r8, r0 @ preserve r0
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adr r0, err_str
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bl printascii
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mov r0, r8
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bl printch
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#endif
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#ifdef CONFIG_ARCH_RPC
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/*
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* Turn the screen red on a error - RiscPC only.
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*/
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mov r0, #0x02000000
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mov r3, #0x11
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orr r3, r3, r3, lsl #8
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orr r3, r3, r3, lsl #16
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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#endif
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1: mov r0, r0
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b 1b
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#ifdef CONFIG_DEBUG_LL
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err_str:
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.asciz "\nError: "
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.align
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#endif
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/*
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* Read processor ID register (CP#15, CR0), and look up in the linker-built
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* supported processor list. Note that we can't use the absolute addresses
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* for the __proc_info lists since we aren't running with the MMU on
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* (and therefore, we are not in the correct address space). We have to
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* calculate the offset.
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*
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* Returns:
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* r5, r6, r7 corrupted
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* r8 = page table flags
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* r9 = processor ID
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* r10 = pointer to processor structure
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*/
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__lookup_processor_type:
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adr r5, 2f
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ldmia r5, {r7, r9, r10}
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sub r5, r5, r10 @ convert addresses
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add r7, r7, r5 @ to our address space
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add r10, r9, r5
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mrc p15, 0, r9, c0, c0 @ get processor id
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1: ldmia r10, {r5, r6, r8} @ value, mask, mmuflags
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and r6, r6, r9 @ mask wanted bits
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teq r5, r6
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moveq pc, lr
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add r10, r10, #PROC_INFO_SZ @ sizeof(proc_info_list)
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cmp r10, r7
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blt 1b
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mov r10, #0 @ unknown processor
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mov pc, lr
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/*
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* Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
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* more information about the __proc_info and __arch_info structures.
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*/
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2: .long __proc_info_end
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.long __proc_info_begin
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.long 2b
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.long __arch_info_begin
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.long __arch_info_end
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/*
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* Lookup machine architecture in the linker-build list of architectures.
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* Note that we can't use the absolute addresses for the __arch_info
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* lists since we aren't running with the MMU on (and therefore, we are
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* not in the correct address space). We have to calculate the offset.
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*
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* r1 = machine architecture number
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* Returns:
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* r2, r3, r4 corrupted
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* r5 = physical start address of RAM
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* r6 = physical address of IO
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* r7 = byte offset into page tables for IO
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*/
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__lookup_architecture_type:
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adr r4, 2b
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ldmia r4, {r2, r3, r5, r6, r7} @ throw away r2, r3
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sub r5, r4, r5 @ convert addresses
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add r4, r6, r5 @ to our address space
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add r7, r7, r5
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1: ldr r5, [r4] @ get machine type
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teq r5, r1 @ matches loader number?
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beq 2f @ found
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add r4, r4, #SIZEOF_MACHINE_DESC @ next machine_desc
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cmp r4, r7
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blt 1b
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mov r7, #0 @ unknown architecture
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mov pc, lr
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2: ldmib r4, {r5, r6, r7} @ found, get results
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mov pc, lr
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