223 lines
6.7 KiB
C
223 lines
6.7 KiB
C
/*
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* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
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* Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org)
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* Copyright (C) 2000 SiByte, Inc.
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*
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* Written by Justin Carlson of SiByte, Inc.
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* and Kip Walker of Broadcom Corp.
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*
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <asm/io.h>
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#include <asm/sibyte/sb1250.h>
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#include <asm/sibyte/sb1250_regs.h>
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#include <asm/sibyte/sb1250_dma.h>
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#ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
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#define SB1_PREF_LOAD_STREAMED_HINT "0"
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#define SB1_PREF_STORE_STREAMED_HINT "1"
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#else
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#define SB1_PREF_LOAD_STREAMED_HINT "4"
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#define SB1_PREF_STORE_STREAMED_HINT "5"
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#endif
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#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
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static inline void clear_page_cpu(void *page)
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#else
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void clear_page(void *page)
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#endif
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{
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unsigned char *addr = (unsigned char *) page;
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unsigned char *end = addr + PAGE_SIZE;
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/*
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* JDCXXX - This should be bottlenecked by the write buffer, but these
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* things tend to be mildly unpredictable...should check this on the
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* performance model
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*
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* We prefetch 4 lines ahead. We're also "cheating" slightly here...
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* since we know we're on an SB1, we force the assembler to take
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* 64-bit operands to speed things up
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*/
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do {
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__asm__ __volatile__(
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" .set mips4 \n"
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#ifdef CONFIG_CPU_HAS_PREFETCH
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" pref " SB1_PREF_STORE_STREAMED_HINT ", 0(%0) \n" /* Prefetch the first 4 lines */
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" pref " SB1_PREF_STORE_STREAMED_HINT ", 32(%0) \n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", 64(%0) \n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", 96(%0) \n"
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#endif
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"1: sd $0, 0(%0) \n" /* Throw out a cacheline of 0's */
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" sd $0, 8(%0) \n"
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" sd $0, 16(%0) \n"
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" sd $0, 24(%0) \n"
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#ifdef CONFIG_CPU_HAS_PREFETCH
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" pref " SB1_PREF_STORE_STREAMED_HINT ",128(%0) \n" /* Prefetch 4 lines ahead */
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#endif
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" .set mips0 \n"
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:
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: "r" (addr)
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: "memory");
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addr += 32;
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} while (addr != end);
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}
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#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
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static inline void copy_page_cpu(void *to, void *from)
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#else
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void copy_page(void *to, void *from)
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#endif
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{
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unsigned char *src = from;
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unsigned char *dst = to;
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unsigned char *end = src + PAGE_SIZE;
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/*
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* This should be optimized in assembly...can't use ld/sd, though,
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* because the top 32 bits could be nuked if we took an interrupt
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* during the routine. And this is not a good place to be cli()'ing
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*
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* The pref's used here are using "streaming" hints, which cause the
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* copied data to be kicked out of the cache sooner. A page copy often
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* ends up copying a lot more data than is commonly used, so this seems
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* to make sense in terms of reducing cache pollution, but I've no real
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* performance data to back this up
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*/
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do {
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__asm__ __volatile__(
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" .set mips4 \n"
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#ifdef CONFIG_CPU_HAS_PREFETCH
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" pref " SB1_PREF_LOAD_STREAMED_HINT ", 0(%0)\n" /* Prefetch the first 3 lines */
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" pref " SB1_PREF_STORE_STREAMED_HINT ", 0(%1)\n"
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" pref " SB1_PREF_LOAD_STREAMED_HINT ", 32(%0)\n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", 32(%1)\n"
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" pref " SB1_PREF_LOAD_STREAMED_HINT ", 64(%0)\n"
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" pref " SB1_PREF_STORE_STREAMED_HINT ", 64(%1)\n"
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#endif
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"1: lw $2, 0(%0) \n" /* Block copy a cacheline */
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" lw $3, 4(%0) \n"
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" lw $4, 8(%0) \n"
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" lw $5, 12(%0) \n"
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" lw $6, 16(%0) \n"
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" lw $7, 20(%0) \n"
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" lw $8, 24(%0) \n"
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" lw $9, 28(%0) \n"
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#ifdef CONFIG_CPU_HAS_PREFETCH
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" pref " SB1_PREF_LOAD_STREAMED_HINT ", 96(%0) \n" /* Prefetch ahead */
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" pref " SB1_PREF_STORE_STREAMED_HINT ", 96(%1) \n"
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#endif
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" sw $2, 0(%1) \n"
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" sw $3, 4(%1) \n"
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" sw $4, 8(%1) \n"
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" sw $5, 12(%1) \n"
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" sw $6, 16(%1) \n"
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" sw $7, 20(%1) \n"
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" sw $8, 24(%1) \n"
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" sw $9, 28(%1) \n"
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" .set mips0 \n"
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:
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: "r" (src), "r" (dst)
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: "$2","$3","$4","$5","$6","$7","$8","$9","memory");
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src += 32;
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dst += 32;
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} while (src != end);
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}
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#ifdef CONFIG_SIBYTE_DMA_PAGEOPS
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/*
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* Pad descriptors to cacheline, since each is exclusively owned by a
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* particular CPU.
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*/
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typedef struct dmadscr_s {
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uint64_t dscr_a;
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uint64_t dscr_b;
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uint64_t pad_a;
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uint64_t pad_b;
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} dmadscr_t;
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static dmadscr_t page_descr[NR_CPUS] __attribute__((aligned(SMP_CACHE_BYTES)));
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void sb1_dma_init(void)
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{
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int cpu = smp_processor_id();
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uint64_t base_val = PHYSADDR(&page_descr[cpu]) | V_DM_DSCR_BASE_RINGSZ(1);
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__raw_writeq(base_val,
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IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
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__raw_writeq(base_val | M_DM_DSCR_BASE_RESET,
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IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
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__raw_writeq(base_val | M_DM_DSCR_BASE_ENABL,
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IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
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}
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void clear_page(void *page)
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{
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int cpu = smp_processor_id();
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/* if the page is above Kseg0, use old way */
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if (KSEGX(page) != CAC_BASE)
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return clear_page_cpu(page);
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page_descr[cpu].dscr_a = PHYSADDR(page) | M_DM_DSCRA_ZERO_MEM | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
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page_descr[cpu].dscr_b = V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
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__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
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/*
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* Don't really want to do it this way, but there's no
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* reliable way to delay completion detection.
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*/
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while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & M_DM_DSCR_BASE_INTERRUPT)))
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;
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__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
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}
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void copy_page(void *to, void *from)
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{
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unsigned long from_phys = PHYSADDR(from);
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unsigned long to_phys = PHYSADDR(to);
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int cpu = smp_processor_id();
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/* if either page is above Kseg0, use old way */
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if ((KSEGX(to) != CAC_BASE) || (KSEGX(from) != CAC_BASE))
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return copy_page_cpu(to, from);
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page_descr[cpu].dscr_a = PHYSADDR(to_phys) | M_DM_DSCRA_L2C_DEST | M_DM_DSCRA_INTERRUPT;
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page_descr[cpu].dscr_b = PHYSADDR(from_phys) | V_DM_DSCRB_SRC_LENGTH(PAGE_SIZE);
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__raw_writeq(1, IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_COUNT)));
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/*
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* Don't really want to do it this way, but there's no
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* reliable way to delay completion detection.
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*/
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while (!(__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE_DEBUG)) & M_DM_DSCR_BASE_INTERRUPT)))
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;
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__raw_readq(IOADDR(A_DM_REGISTER(cpu, R_DM_DSCR_BASE)));
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}
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#endif
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EXPORT_SYMBOL(clear_page);
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EXPORT_SYMBOL(copy_page);
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