477 lines
11 KiB
C
477 lines
11 KiB
C
/*
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* arch/ppc/platforms/ev64260_setup.c
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*
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* Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
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*
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* Author: Mark A. Greer <mgreer@mvista.com>
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*
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* 2001 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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/*
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* The EV-64260-BP port is the result of hard work from many people from
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* many companies. In particular, employees of Marvell/Galileo, Mission
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* Critical Linux, Xyterra, and MontaVista Software were heavily involved.
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*/
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#include <linux/config.h>
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#include <linux/stddef.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/reboot.h>
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#include <linux/pci.h>
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#include <linux/kdev_t.h>
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#include <linux/major.h>
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#include <linux/initrd.h>
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#include <linux/console.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/ide.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#if !defined(CONFIG_GT64260_CONSOLE)
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#include <linux/serial.h>
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#endif
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#include <asm/system.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/time.h>
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#include <asm/dma.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/smp.h>
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#include <asm/todc.h>
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#include <asm/bootinfo.h>
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#include <asm/gt64260.h>
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#include <platforms/ev64260.h>
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extern char cmd_line[];
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unsigned long ev64260_find_end_of_memory(void);
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TODC_ALLOC();
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/*
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* Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
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*/
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static int __init
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ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
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{
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struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
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if (hose->index == 0) {
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 91, 0, 0, 0 }, /* IDSEL 7 - PCI bus 0 */
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{ 91, 0, 0, 0 }, /* IDSEL 8 - PCI bus 0 */
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};
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const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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else {
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static char pci_irq_table[][4] =
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/*
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* PCI IDSEL/INTPIN->INTLINE
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* A B C D
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*/
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{
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{ 93, 0, 0, 0 }, /* IDSEL 7 - PCI bus 1 */
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{ 93, 0, 0, 0 }, /* IDSEL 8 - PCI bus 1 */
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};
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const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
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return PCI_IRQ_TABLE_LOOKUP;
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}
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}
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static void __init
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ev64260_setup_bridge(void)
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{
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gt64260_bridge_info_t info;
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int window;
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GT64260_BRIDGE_INFO_DEFAULT(&info, ev64260_find_end_of_memory());
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/* Lookup PCI host bridges */
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if (gt64260_find_bridges(EV64260_BRIDGE_REG_BASE,
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&info,
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ev64260_map_irq)) {
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printk("Bridge initialization failed.\n");
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}
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/*
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* Enabling of PCI internal-vs-external arbitration
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* is a platform- and errata-dependent decision.
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*/
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if(gt64260_revision == GT64260) {
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/* FEr#35 */
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gt_clr_bits(GT64260_PCI_0_ARBITER_CNTL, (1<<31));
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gt_clr_bits(GT64260_PCI_1_ARBITER_CNTL, (1<<31));
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} else if( gt64260_revision == GT64260A ) {
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gt_set_bits(GT64260_PCI_0_ARBITER_CNTL, (1<<31));
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gt_set_bits(GT64260_PCI_1_ARBITER_CNTL, (1<<31));
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/* Make external GPP interrupts level sensitive */
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gt_set_bits(GT64260_COMM_ARBITER_CNTL, (1<<10));
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/* Doc Change 9: > 100 MHz so must be set */
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gt_set_bits(GT64260_CPU_CONFIG, (1<<23));
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}
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gt_set_bits(GT64260_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
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/* SCS windows not disabled above, disable all but SCS 0 */
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for (window=1; window<GT64260_CPU_SCS_DECODE_WINDOWS; window++) {
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gt64260_cpu_scs_set_window(window, 0, 0);
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}
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/* Set up windows to RTC/TODC and DUART on device module (CS 1 & 2) */
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gt64260_cpu_cs_set_window(1, EV64260_TODC_BASE, EV64260_TODC_LEN);
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gt64260_cpu_cs_set_window(2, EV64260_UART_BASE, EV64260_UART_LEN);
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/*
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* The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
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* bridge as interrupt inputs (via the General Purpose Ports (GPP)
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* register). Need to route the MPP inputs to the GPP and set the
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* polarity correctly.
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*
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* In MPP Control 2 Register
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* MPP 21 -> GPP 21 (DUART channel A intr)
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* MPP 22 -> GPP 22 (DUART channel B intr)
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*
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* In MPP Control 3 Register
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* MPP 27 -> GPP 27 (PCI 0 INTA)
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* MPP 29 -> GPP 29 (PCI 1 INTA)
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*/
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gt_clr_bits(GT64260_MPP_CNTL_2,
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((1<<20) | (1<<21) | (1<<22) | (1<<23) |
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(1<<24) | (1<<25) | (1<<26) | (1<<27)));
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gt_clr_bits(GT64260_MPP_CNTL_3,
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((1<<12) | (1<<13) | (1<<14) | (1<<15) |
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(1<<20) | (1<<21) | (1<<22) | (1<<23)));
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gt_write(GT64260_GPP_LEVEL_CNTL, 0x000002c6);
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/* DUART & PCI interrupts are active low */
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gt_set_bits(GT64260_GPP_LEVEL_CNTL,
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((1<<21) | (1<<22) | (1<<27) | (1<<29)));
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/* Clear any pending interrupts for these inputs and enable them. */
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gt_write(GT64260_GPP_INTR_CAUSE,
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~((1<<21) | (1<<22) | (1<<27) | (1<<29)));
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gt_set_bits(GT64260_GPP_INTR_MASK,
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((1<<21) | (1<<22)| (1<<27) | (1<<29)));
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gt_set_bits(GT64260_IC_CPU_INTR_MASK_HI, ((1<<26) | (1<<27)));
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/* Set MPSC Multiplex RMII */
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/* NOTE: ethernet driver modifies bit 0 and 1 */
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gt_write(GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
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return;
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}
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static void __init
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ev64260_setup_arch(void)
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{
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#if !defined(CONFIG_GT64260_CONSOLE)
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struct serial_struct serial_req;
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#endif
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if ( ppc_md.progress )
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ppc_md.progress("ev64260_setup_arch: enter", 0);
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loops_per_jiffy = 50000000 / HZ;
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#ifdef CONFIG_BLK_DEV_INITRD
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if (initrd_start)
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ROOT_DEV = Root_RAM0;
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else
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#endif
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#ifdef CONFIG_ROOT_NFS
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ROOT_DEV = Root_NFS;
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#else
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ROOT_DEV = Root_SDA2;
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#endif
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if ( ppc_md.progress )
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ppc_md.progress("ev64260_setup_arch: find_bridges", 0);
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/*
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* Set up the L2CR register.
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* L2 cache was invalidated by bootloader.
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*/
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switch (PVR_VER(mfspr(PVR))) {
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case PVR_VER(PVR_750):
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_set_L2CR(0xfd100000);
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break;
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case PVR_VER(PVR_7400):
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case PVR_VER(PVR_7410):
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_set_L2CR(0xcd100000);
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break;
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/* case PVR_VER(PVR_7450): */
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/* XXXX WHAT VALUE?? FIXME */
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break;
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}
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ev64260_setup_bridge();
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TODC_INIT(TODC_TYPE_DS1501, 0, 0, ioremap(EV64260_TODC_BASE,0x20), 8);
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#if !defined(CONFIG_GT64260_CONSOLE)
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memset(&serial_req, 0, sizeof(serial_req));
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serial_req.line = 0;
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serial_req.baud_base = BASE_BAUD;
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serial_req.port = 0;
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serial_req.irq = 85;
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serial_req.flags = STD_COM_FLAGS;
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serial_req.io_type = SERIAL_IO_MEM;
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serial_req.iomem_base = ioremap(EV64260_SERIAL_0, 0x20);
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serial_req.iomem_reg_shift = 2;
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if (early_serial_setup(&serial_req) != 0) {
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printk("Early serial init of port 0 failed\n");
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}
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/* Assume early_serial_setup() doesn't modify serial_req */
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serial_req.line = 1;
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serial_req.port = 1;
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serial_req.irq = 86;
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serial_req.iomem_base = ioremap(EV64260_SERIAL_1, 0x20);
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if (early_serial_setup(&serial_req) != 0) {
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printk("Early serial init of port 1 failed\n");
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}
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#endif
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printk("Marvell/Galileo EV-64260-BP Evaluation Board\n");
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printk("EV-64260-BP port (C) 2001 MontaVista Software, Inc. (source@mvista.com)\n");
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if ( ppc_md.progress )
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ppc_md.progress("ev64260_setup_arch: exit", 0);
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return;
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}
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static void __init
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ev64260_init_irq(void)
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{
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gt64260_init_irq();
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if(gt64260_revision != GT64260) {
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/* XXXX Kludge--need to fix gt64260_init_irq() interface */
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/* Mark PCI intrs level sensitive */
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irq_desc[91].status |= IRQ_LEVEL;
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irq_desc[93].status |= IRQ_LEVEL;
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}
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}
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unsigned long __init
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ev64260_find_end_of_memory(void)
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{
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return 32*1024*1024; /* XXXX FIXME */
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}
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static void
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ev64260_reset_board(void)
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{
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local_irq_disable();
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/* Set exception prefix high - to the firmware */
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_nmask_and_or_msr(0, MSR_IP);
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/* XXX FIXME */
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printk("XXXX **** trying to reset board ****\n");
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return;
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}
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static void
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ev64260_restart(char *cmd)
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{
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volatile ulong i = 10000000;
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ev64260_reset_board();
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while (i-- > 0);
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panic("restart failed\n");
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}
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static void
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ev64260_halt(void)
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{
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local_irq_disable();
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while (1);
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/* NOTREACHED */
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}
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static void
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ev64260_power_off(void)
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{
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ev64260_halt();
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/* NOTREACHED */
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}
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static int
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ev64260_show_cpuinfo(struct seq_file *m)
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{
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uint pvid;
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pvid = mfspr(PVR);
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seq_printf(m, "vendor\t\t: Marvell/Galileo\n");
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seq_printf(m, "machine\t\t: EV-64260-BP\n");
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seq_printf(m, "PVID\t\t: 0x%x, vendor: %s\n",
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pvid, (pvid & (1<<15) ? "IBM" : "Motorola"));
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return 0;
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}
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/* DS1501 RTC has too much variation to use RTC for calibration */
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static void __init
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ev64260_calibrate_decr(void)
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{
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ulong freq;
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freq = 100000000 / 4;
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printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
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freq/1000000, freq%1000000);
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tb_ticks_per_jiffy = freq / HZ;
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tb_to_us = mulhwu_scale_factor(freq, 1000000);
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return;
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}
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#if defined(CONFIG_SERIAL_TEXT_DEBUG)
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/*
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* Set BAT 3 to map 0xf0000000 to end of physical memory space.
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*/
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static __inline__ void
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ev64260_set_bat(void)
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{
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unsigned long bat3u, bat3l;
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static int mapping_set = 0;
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if (!mapping_set) {
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__asm__ __volatile__(
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" lis %0,0xf000\n \
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ori %1,%0,0x002a\n \
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ori %0,%0,0x1ffe\n \
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mtspr 0x21e,%0\n \
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mtspr 0x21f,%1\n \
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isync\n \
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sync "
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: "=r" (bat3u), "=r" (bat3l));
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mapping_set = 1;
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}
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return;
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}
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#if !defined(CONFIG_GT64260_CONSOLE)
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#include <linux/serialP.h>
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#include <linux/serial_reg.h>
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#include <asm/serial.h>
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static struct serial_state rs_table[RS_TABLE_SIZE] = {
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SERIAL_PORT_DFNS /* Defined in <asm/serial.h> */
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};
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static void
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ev64260_16550_progress(char *s, unsigned short hex)
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{
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volatile char c;
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volatile unsigned long com_port;
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u16 shift;
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com_port = rs_table[0].port;
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shift = rs_table[0].iomem_reg_shift;
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while ((c = *s++) != 0) {
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while ((*((volatile unsigned char *)com_port +
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(UART_LSR << shift)) & UART_LSR_THRE) == 0)
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;
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*(volatile unsigned char *)com_port = c;
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if (c == '\n') {
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while ((*((volatile unsigned char *)com_port +
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(UART_LSR << shift)) & UART_LSR_THRE) == 0)
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;
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*(volatile unsigned char *)com_port = '\r';
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}
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}
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/* Move to next line on */
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while ((*((volatile unsigned char *)com_port +
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(UART_LSR << shift)) & UART_LSR_THRE) == 0)
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;
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*(volatile unsigned char *)com_port = '\n';
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while ((*((volatile unsigned char *)com_port +
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(UART_LSR << shift)) & UART_LSR_THRE) == 0)
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;
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*(volatile unsigned char *)com_port = '\r';
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return;
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}
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#endif /* !CONFIG_GT64260_CONSOLE */
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#endif /* CONFIG_SERIAL_TEXT_DEBUG */
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void __init
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platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
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unsigned long r6, unsigned long r7)
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{
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parse_bootinfo(find_bootinfo());
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isa_mem_base = 0;
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ppc_md.setup_arch = ev64260_setup_arch;
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ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
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ppc_md.irq_canonicalize = NULL;
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ppc_md.init_IRQ = ev64260_init_irq;
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ppc_md.get_irq = gt64260_get_irq;
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ppc_md.init = NULL;
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ppc_md.restart = ev64260_restart;
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ppc_md.power_off = ev64260_power_off;
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ppc_md.halt = ev64260_halt;
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ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
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ppc_md.time_init = todc_time_init;
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ppc_md.set_rtc_time = todc_set_rtc_time;
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ppc_md.get_rtc_time = todc_get_rtc_time;
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ppc_md.calibrate_decr = ev64260_calibrate_decr;
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ppc_md.nvram_read_val = todc_direct_read_val;
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ppc_md.nvram_write_val = todc_direct_write_val;
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ppc_md.heartbeat = NULL;
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ppc_md.heartbeat_reset = 0;
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ppc_md.heartbeat_count = 0;
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#ifdef CONFIG_SERIAL_TEXT_DEBUG
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ev64260_set_bat();
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#ifdef CONFIG_GT64260_CONSOLE
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gt64260_base = EV64260_BRIDGE_REG_BASE;
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ppc_md.progress = gt64260_mpsc_progress; /* embedded UART */
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#else
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ppc_md.progress = ev64260_16550_progress; /* Dev module DUART */
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#endif
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#else /* !CONFIG_SERIAL_TEXT_DEBUG */
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ppc_md.progress = NULL;
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#endif /* CONFIG_SERIAL_TEXT_DEBUG */
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return;
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}
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