602 lines
24 KiB
C
602 lines
24 KiB
C
#ifndef __MV64340_ETH_H__
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#define __MV64340_ETH_H__
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#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/mv643xx.h>
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#define BIT0 0x00000001
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#define BIT1 0x00000002
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#define BIT2 0x00000004
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#define BIT3 0x00000008
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#define BIT4 0x00000010
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#define BIT5 0x00000020
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#define BIT6 0x00000040
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#define BIT7 0x00000080
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#define BIT8 0x00000100
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#define BIT9 0x00000200
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#define BIT10 0x00000400
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#define BIT11 0x00000800
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#define BIT12 0x00001000
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#define BIT13 0x00002000
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#define BIT14 0x00004000
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#define BIT15 0x00008000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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#define BIT23 0x00800000
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#define BIT24 0x01000000
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#define BIT25 0x02000000
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#define BIT26 0x04000000
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#define BIT27 0x08000000
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#define BIT28 0x10000000
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#define BIT29 0x20000000
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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/*
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* The first part is the high level driver of the gigE ethernet ports.
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*/
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#define ETH_PORT0_IRQ_NUM 48 /* main high register, bit0 */
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#define ETH_PORT1_IRQ_NUM ETH_PORT0_IRQ_NUM+1 /* main high register, bit1 */
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#define ETH_PORT2_IRQ_NUM ETH_PORT0_IRQ_NUM+2 /* main high register, bit1 */
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/* Checksum offload for Tx works */
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#define MV64340_CHECKSUM_OFFLOAD_TX
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#define MV64340_NAPI
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#define MV64340_TX_FAST_REFILL
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#undef MV64340_COAL
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/*
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* Number of RX / TX descriptors on RX / TX rings.
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* Note that allocating RX descriptors is done by allocating the RX
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* ring AND a preallocated RX buffers (skb's) for each descriptor.
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* The TX descriptors only allocates the TX descriptors ring,
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* with no pre allocated TX buffers (skb's are allocated by higher layers.
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*/
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/* Default TX ring size is 1000 descriptors */
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#define MV64340_TX_QUEUE_SIZE 1000
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/* Default RX ring size is 400 descriptors */
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#define MV64340_RX_QUEUE_SIZE 400
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#define MV64340_TX_COAL 100
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#ifdef MV64340_COAL
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#define MV64340_RX_COAL 100
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#endif
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/*
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* The second part is the low level driver of the gigE ethernet ports. *
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*/
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/*
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* Header File for : MV-643xx network interface header
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*
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* DESCRIPTION:
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* This header file contains macros typedefs and function declaration for
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* the Marvell Gig Bit Ethernet Controller.
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*
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* DEPENDENCIES:
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* None.
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*
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*/
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/* Default port configuration value */
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#define PORT_CONFIG_VALUE \
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ETH_UNICAST_NORMAL_MODE | \
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ETH_DEFAULT_RX_QUEUE_0 | \
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ETH_DEFAULT_RX_ARP_QUEUE_0 | \
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ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
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ETH_RECEIVE_BC_IF_IP | \
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ETH_RECEIVE_BC_IF_ARP | \
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ETH_CAPTURE_TCP_FRAMES_DIS | \
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ETH_CAPTURE_UDP_FRAMES_DIS | \
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ETH_DEFAULT_RX_TCP_QUEUE_0 | \
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ETH_DEFAULT_RX_UDP_QUEUE_0 | \
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ETH_DEFAULT_RX_BPDU_QUEUE_0
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/* Default port extend configuration value */
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#define PORT_CONFIG_EXTEND_VALUE \
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ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
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ETH_PARTITION_DISABLE
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/* Default sdma control value */
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#define PORT_SDMA_CONFIG_VALUE \
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ETH_RX_BURST_SIZE_16_64BIT | \
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GT_ETH_IPG_INT_RX(0) | \
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ETH_TX_BURST_SIZE_16_64BIT;
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#define GT_ETH_IPG_INT_RX(value) \
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((value & 0x3fff) << 8)
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/* Default port serial control value */
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#define PORT_SERIAL_CONTROL_VALUE \
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ETH_FORCE_LINK_PASS | \
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ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
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ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
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ETH_ADV_SYMMETRIC_FLOW_CTRL | \
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ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
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ETH_FORCE_BP_MODE_NO_JAM | \
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BIT9 | \
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ETH_DO_NOT_FORCE_LINK_FAIL | \
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ETH_RETRANSMIT_16_ATTEMPTS | \
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ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
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ETH_DTE_ADV_0 | \
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ETH_DISABLE_AUTO_NEG_BYPASS | \
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ETH_AUTO_NEG_NO_CHANGE | \
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ETH_MAX_RX_PACKET_9700BYTE | \
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ETH_CLR_EXT_LOOPBACK | \
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ETH_SET_FULL_DUPLEX_MODE | \
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ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
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#define RX_BUFFER_MAX_SIZE 0x4000000
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#define TX_BUFFER_MAX_SIZE 0x4000000
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/* MAC accepet/reject macros */
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#define ACCEPT_MAC_ADDR 0
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#define REJECT_MAC_ADDR 1
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/* Buffer offset from buffer pointer */
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#define RX_BUF_OFFSET 0x2
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/* Gigabit Ethernet Unit Global Registers */
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/* MIB Counters register definitions */
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#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
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#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
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#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
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#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
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#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
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#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
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#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
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#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
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#define ETH_MIB_FRAMES_64_OCTETS 0x20
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#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
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#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
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#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
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#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
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#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
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#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
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#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
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#define ETH_MIB_GOOD_FRAMES_SENT 0x40
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#define ETH_MIB_EXCESSIVE_COLLISION 0x44
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#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
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#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
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#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
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#define ETH_MIB_FC_SENT 0x54
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#define ETH_MIB_GOOD_FC_RECEIVED 0x58
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#define ETH_MIB_BAD_FC_RECEIVED 0x5c
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#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
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#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
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#define ETH_MIB_OVERSIZE_RECEIVED 0x68
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#define ETH_MIB_JABBER_RECEIVED 0x6c
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#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
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#define ETH_MIB_BAD_CRC_EVENT 0x74
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#define ETH_MIB_COLLISION 0x78
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#define ETH_MIB_LATE_COLLISION 0x7c
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/* Port serial status reg (PSR) */
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#define ETH_INTERFACE_GMII_MII 0
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#define ETH_INTERFACE_PCM BIT0
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#define ETH_LINK_IS_DOWN 0
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#define ETH_LINK_IS_UP BIT1
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#define ETH_PORT_AT_HALF_DUPLEX 0
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#define ETH_PORT_AT_FULL_DUPLEX BIT2
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#define ETH_RX_FLOW_CTRL_DISABLED 0
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#define ETH_RX_FLOW_CTRL_ENBALED BIT3
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#define ETH_GMII_SPEED_100_10 0
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#define ETH_GMII_SPEED_1000 BIT4
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#define ETH_MII_SPEED_10 0
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#define ETH_MII_SPEED_100 BIT5
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#define ETH_NO_TX 0
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#define ETH_TX_IN_PROGRESS BIT7
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#define ETH_BYPASS_NO_ACTIVE 0
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#define ETH_BYPASS_ACTIVE BIT8
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#define ETH_PORT_NOT_AT_PARTITION_STATE 0
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#define ETH_PORT_AT_PARTITION_STATE BIT9
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#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
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#define ETH_PORT_TX_FIFO_EMPTY BIT10
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/* These macros describes the Port configuration reg (Px_cR) bits */
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#define ETH_UNICAST_NORMAL_MODE 0
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#define ETH_UNICAST_PROMISCUOUS_MODE BIT0
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#define ETH_DEFAULT_RX_QUEUE_0 0
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#define ETH_DEFAULT_RX_QUEUE_1 BIT1
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#define ETH_DEFAULT_RX_QUEUE_2 BIT2
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#define ETH_DEFAULT_RX_QUEUE_3 (BIT2 | BIT1)
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#define ETH_DEFAULT_RX_QUEUE_4 BIT3
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#define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
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#define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
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#define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
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#define ETH_DEFAULT_RX_ARP_QUEUE_0 0
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#define ETH_DEFAULT_RX_ARP_QUEUE_1 BIT4
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#define ETH_DEFAULT_RX_ARP_QUEUE_2 BIT5
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#define ETH_DEFAULT_RX_ARP_QUEUE_3 (BIT5 | BIT4)
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#define ETH_DEFAULT_RX_ARP_QUEUE_4 BIT6
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#define ETH_DEFAULT_RX_ARP_QUEUE_5 (BIT6 | BIT4)
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#define ETH_DEFAULT_RX_ARP_QUEUE_6 (BIT6 | BIT5)
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#define ETH_DEFAULT_RX_ARP_QUEUE_7 (BIT6 | BIT5 | BIT4)
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#define ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
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#define ETH_REJECT_BC_IF_NOT_IP_OR_ARP BIT7
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#define ETH_RECEIVE_BC_IF_IP 0
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#define ETH_REJECT_BC_IF_IP BIT8
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#define ETH_RECEIVE_BC_IF_ARP 0
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#define ETH_REJECT_BC_IF_ARP BIT9
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#define ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY BIT12
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#define ETH_CAPTURE_TCP_FRAMES_DIS 0
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#define ETH_CAPTURE_TCP_FRAMES_EN BIT14
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#define ETH_CAPTURE_UDP_FRAMES_DIS 0
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#define ETH_CAPTURE_UDP_FRAMES_EN BIT15
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#define ETH_DEFAULT_RX_TCP_QUEUE_0 0
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#define ETH_DEFAULT_RX_TCP_QUEUE_1 BIT16
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#define ETH_DEFAULT_RX_TCP_QUEUE_2 BIT17
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#define ETH_DEFAULT_RX_TCP_QUEUE_3 (BIT17 | BIT16)
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#define ETH_DEFAULT_RX_TCP_QUEUE_4 BIT18
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#define ETH_DEFAULT_RX_TCP_QUEUE_5 (BIT18 | BIT16)
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#define ETH_DEFAULT_RX_TCP_QUEUE_6 (BIT18 | BIT17)
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#define ETH_DEFAULT_RX_TCP_QUEUE_7 (BIT18 | BIT17 | BIT16)
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#define ETH_DEFAULT_RX_UDP_QUEUE_0 0
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#define ETH_DEFAULT_RX_UDP_QUEUE_1 BIT19
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#define ETH_DEFAULT_RX_UDP_QUEUE_2 BIT20
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#define ETH_DEFAULT_RX_UDP_QUEUE_3 (BIT20 | BIT19)
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#define ETH_DEFAULT_RX_UDP_QUEUE_4 (BIT21
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#define ETH_DEFAULT_RX_UDP_QUEUE_5 (BIT21 | BIT19)
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#define ETH_DEFAULT_RX_UDP_QUEUE_6 (BIT21 | BIT20)
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#define ETH_DEFAULT_RX_UDP_QUEUE_7 (BIT21 | BIT20 | BIT19)
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#define ETH_DEFAULT_RX_BPDU_QUEUE_0 0
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#define ETH_DEFAULT_RX_BPDU_QUEUE_1 BIT22
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#define ETH_DEFAULT_RX_BPDU_QUEUE_2 BIT23
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#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
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#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
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#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
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#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
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#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
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/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
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#define ETH_CLASSIFY_EN BIT0
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#define ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
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#define ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 BIT1
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#define ETH_PARTITION_DISABLE 0
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#define ETH_PARTITION_ENABLE BIT2
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/* Tx/Rx queue command reg (RQCR/TQCR)*/
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#define ETH_QUEUE_0_ENABLE BIT0
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#define ETH_QUEUE_1_ENABLE BIT1
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#define ETH_QUEUE_2_ENABLE BIT2
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#define ETH_QUEUE_3_ENABLE BIT3
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#define ETH_QUEUE_4_ENABLE BIT4
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#define ETH_QUEUE_5_ENABLE BIT5
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#define ETH_QUEUE_6_ENABLE BIT6
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#define ETH_QUEUE_7_ENABLE BIT7
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#define ETH_QUEUE_0_DISABLE BIT8
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#define ETH_QUEUE_1_DISABLE BIT9
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#define ETH_QUEUE_2_DISABLE BIT10
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#define ETH_QUEUE_3_DISABLE BIT11
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#define ETH_QUEUE_4_DISABLE BIT12
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#define ETH_QUEUE_5_DISABLE BIT13
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#define ETH_QUEUE_6_DISABLE BIT14
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#define ETH_QUEUE_7_DISABLE BIT15
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/* These macros describes the Port Sdma configuration reg (SDCR) bits */
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#define ETH_RIFB BIT0
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#define ETH_RX_BURST_SIZE_1_64BIT 0
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#define ETH_RX_BURST_SIZE_2_64BIT BIT1
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#define ETH_RX_BURST_SIZE_4_64BIT BIT2
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#define ETH_RX_BURST_SIZE_8_64BIT (BIT2 | BIT1)
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#define ETH_RX_BURST_SIZE_16_64BIT BIT3
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#define ETH_BLM_RX_NO_SWAP BIT4
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#define ETH_BLM_RX_BYTE_SWAP 0
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#define ETH_BLM_TX_NO_SWAP BIT5
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#define ETH_BLM_TX_BYTE_SWAP 0
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#define ETH_DESCRIPTORS_BYTE_SWAP BIT6
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#define ETH_DESCRIPTORS_NO_SWAP 0
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#define ETH_TX_BURST_SIZE_1_64BIT 0
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#define ETH_TX_BURST_SIZE_2_64BIT BIT22
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#define ETH_TX_BURST_SIZE_4_64BIT BIT23
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#define ETH_TX_BURST_SIZE_8_64BIT (BIT23 | BIT22)
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#define ETH_TX_BURST_SIZE_16_64BIT BIT24
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/* These macros describes the Port serial control reg (PSCR) bits */
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#define ETH_SERIAL_PORT_DISABLE 0
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#define ETH_SERIAL_PORT_ENABLE BIT0
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#define ETH_FORCE_LINK_PASS BIT1
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#define ETH_DO_NOT_FORCE_LINK_PASS 0
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#define ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
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#define ETH_DISABLE_AUTO_NEG_FOR_DUPLX BIT2
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#define ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
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#define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
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#define ETH_ADV_NO_FLOW_CTRL 0
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#define ETH_ADV_SYMMETRIC_FLOW_CTRL BIT4
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#define ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
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#define ETH_FORCE_FC_MODE_TX_PAUSE_DIS BIT5
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#define ETH_FORCE_BP_MODE_NO_JAM 0
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#define ETH_FORCE_BP_MODE_JAM_TX BIT7
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#define ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR BIT8
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#define ETH_FORCE_LINK_FAIL 0
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#define ETH_DO_NOT_FORCE_LINK_FAIL BIT10
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#define ETH_RETRANSMIT_16_ATTEMPTS 0
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#define ETH_RETRANSMIT_FOREVER BIT11
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#define ETH_DISABLE_AUTO_NEG_SPEED_GMII BIT13
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#define ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
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#define ETH_DTE_ADV_0 0
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#define ETH_DTE_ADV_1 BIT14
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#define ETH_DISABLE_AUTO_NEG_BYPASS 0
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#define ETH_ENABLE_AUTO_NEG_BYPASS BIT15
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#define ETH_AUTO_NEG_NO_CHANGE 0
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#define ETH_RESTART_AUTO_NEG BIT16
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#define ETH_MAX_RX_PACKET_1518BYTE 0
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#define ETH_MAX_RX_PACKET_1522BYTE BIT17
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#define ETH_MAX_RX_PACKET_1552BYTE BIT18
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#define ETH_MAX_RX_PACKET_9022BYTE (BIT18 | BIT17)
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#define ETH_MAX_RX_PACKET_9192BYTE BIT19
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#define ETH_MAX_RX_PACKET_9700BYTE (BIT19 | BIT17)
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#define ETH_SET_EXT_LOOPBACK BIT20
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#define ETH_CLR_EXT_LOOPBACK 0
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#define ETH_SET_FULL_DUPLEX_MODE BIT21
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#define ETH_SET_HALF_DUPLEX_MODE 0
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#define ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX BIT22
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#define ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
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#define ETH_SET_GMII_SPEED_TO_10_100 0
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#define ETH_SET_GMII_SPEED_TO_1000 BIT23
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#define ETH_SET_MII_SPEED_TO_10 0
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#define ETH_SET_MII_SPEED_TO_100 BIT24
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/* SMI reg */
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#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
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#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
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#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
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#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
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/* SDMA command status fields macros */
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/* Tx & Rx descriptors status */
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#define ETH_ERROR_SUMMARY (BIT0)
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/* Tx & Rx descriptors command */
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#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
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/* Tx descriptors status */
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#define ETH_LC_ERROR (0 )
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#define ETH_UR_ERROR (BIT1 )
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#define ETH_RL_ERROR (BIT2 )
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#define ETH_LLC_SNAP_FORMAT (BIT9 )
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/* Rx descriptors status */
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#define ETH_CRC_ERROR (0 )
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#define ETH_OVERRUN_ERROR (BIT1 )
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#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
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#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
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#define ETH_VLAN_TAGGED (BIT19)
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#define ETH_BPDU_FRAME (BIT20)
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#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
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#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
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#define ETH_OTHER_FRAME_TYPE (BIT22)
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#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
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#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
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#define ETH_FRAME_HEADER_OK (BIT25)
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#define ETH_RX_LAST_DESC (BIT26)
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#define ETH_RX_FIRST_DESC (BIT27)
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#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
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#define ETH_RX_ENABLE_INTERRUPT (BIT29)
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#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
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/* Rx descriptors byte count */
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#define ETH_FRAME_FRAGMENTED (BIT2)
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/* Tx descriptors command */
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#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
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#define ETH_FRAME_SET_TO_VLAN (BIT15)
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#define ETH_TCP_FRAME (0 )
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#define ETH_UDP_FRAME (BIT16)
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|
#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
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|
#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
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|
#define ETH_ZERO_PADDING (BIT19)
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|
#define ETH_TX_LAST_DESC (BIT20)
|
|
#define ETH_TX_FIRST_DESC (BIT21)
|
|
#define ETH_GEN_CRC (BIT22)
|
|
#define ETH_TX_ENABLE_INTERRUPT (BIT23)
|
|
#define ETH_AUTO_MODE (BIT30)
|
|
|
|
/* typedefs */
|
|
|
|
typedef enum _eth_func_ret_status {
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|
ETH_OK, /* Returned as expected. */
|
|
ETH_ERROR, /* Fundamental error. */
|
|
ETH_RETRY, /* Could not process request. Try later. */
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|
ETH_END_OF_JOB, /* Ring has nothing to process. */
|
|
ETH_QUEUE_FULL, /* Ring resource error. */
|
|
ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
|
|
} ETH_FUNC_RET_STATUS;
|
|
|
|
typedef enum _eth_target {
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|
ETH_TARGET_DRAM,
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|
ETH_TARGET_DEVICE,
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|
ETH_TARGET_CBS,
|
|
ETH_TARGET_PCI0,
|
|
ETH_TARGET_PCI1
|
|
} ETH_TARGET;
|
|
|
|
/* These are for big-endian machines. Little endian needs different
|
|
* definitions.
|
|
*/
|
|
#if defined(__BIG_ENDIAN)
|
|
struct eth_rx_desc {
|
|
u16 byte_cnt; /* Descriptor buffer byte count */
|
|
u16 buf_size; /* Buffer size */
|
|
u32 cmd_sts; /* Descriptor command status */
|
|
u32 next_desc_ptr; /* Next descriptor pointer */
|
|
u32 buf_ptr; /* Descriptor buffer pointer */
|
|
};
|
|
|
|
struct eth_tx_desc {
|
|
u16 byte_cnt; /* buffer byte count */
|
|
u16 l4i_chk; /* CPU provided TCP checksum */
|
|
u32 cmd_sts; /* Command/status field */
|
|
u32 next_desc_ptr; /* Pointer to next descriptor */
|
|
u32 buf_ptr; /* pointer to buffer for this descriptor */
|
|
};
|
|
|
|
#elif defined(__LITTLE_ENDIAN)
|
|
struct eth_rx_desc {
|
|
u32 cmd_sts; /* Descriptor command status */
|
|
u16 buf_size; /* Buffer size */
|
|
u16 byte_cnt; /* Descriptor buffer byte count */
|
|
u32 buf_ptr; /* Descriptor buffer pointer */
|
|
u32 next_desc_ptr; /* Next descriptor pointer */
|
|
};
|
|
|
|
struct eth_tx_desc {
|
|
u32 cmd_sts; /* Command/status field */
|
|
u16 l4i_chk; /* CPU provided TCP checksum */
|
|
u16 byte_cnt; /* buffer byte count */
|
|
u32 buf_ptr; /* pointer to buffer for this descriptor */
|
|
u32 next_desc_ptr; /* Pointer to next descriptor */
|
|
};
|
|
#else
|
|
#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
|
|
#endif
|
|
|
|
/* Unified struct for Rx and Tx operations. The user is not required to */
|
|
/* be familier with neither Tx nor Rx descriptors. */
|
|
struct pkt_info {
|
|
unsigned short byte_cnt; /* Descriptor buffer byte count */
|
|
unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
|
|
unsigned int cmd_sts; /* Descriptor command status */
|
|
dma_addr_t buf_ptr; /* Descriptor buffer pointer */
|
|
struct sk_buff * return_info; /* User resource return information */
|
|
};
|
|
|
|
|
|
/* Ethernet port specific infomation */
|
|
|
|
struct mv64340_private {
|
|
int port_num; /* User Ethernet port number */
|
|
u8 port_mac_addr[6]; /* User defined port MAC address. */
|
|
u32 port_config; /* User port configuration value */
|
|
u32 port_config_extend; /* User port config extend value */
|
|
u32 port_sdma_config; /* User port SDMA config value */
|
|
u32 port_serial_control; /* User port serial control value */
|
|
u32 port_tx_queue_command; /* Port active Tx queues summary */
|
|
u32 port_rx_queue_command; /* Port active Rx queues summary */
|
|
|
|
int rx_resource_err; /* Rx ring resource error flag */
|
|
int tx_resource_err; /* Tx ring resource error flag */
|
|
|
|
/* Tx/Rx rings managment indexes fields. For driver use */
|
|
|
|
/* Next available and first returning Rx resource */
|
|
int rx_curr_desc_q, rx_used_desc_q;
|
|
|
|
/* Next available and first returning Tx resource */
|
|
int tx_curr_desc_q, tx_used_desc_q;
|
|
#ifdef MV64340_CHECKSUM_OFFLOAD_TX
|
|
int tx_first_desc_q;
|
|
#endif
|
|
|
|
#ifdef MV64340_TX_FAST_REFILL
|
|
u32 tx_clean_threshold;
|
|
#endif
|
|
|
|
volatile struct eth_rx_desc * p_rx_desc_area;
|
|
dma_addr_t rx_desc_dma;
|
|
unsigned int rx_desc_area_size;
|
|
struct sk_buff * rx_skb[MV64340_RX_QUEUE_SIZE];
|
|
|
|
volatile struct eth_tx_desc * p_tx_desc_area;
|
|
dma_addr_t tx_desc_dma;
|
|
unsigned int tx_desc_area_size;
|
|
struct sk_buff * tx_skb[MV64340_TX_QUEUE_SIZE];
|
|
|
|
struct work_struct tx_timeout_task;
|
|
|
|
/*
|
|
* Former struct mv64340_eth_priv members start here
|
|
*/
|
|
struct net_device_stats stats;
|
|
spinlock_t lock;
|
|
/* Size of Tx Ring per queue */
|
|
unsigned int tx_ring_size;
|
|
/* Ammont of SKBs outstanding on Tx queue */
|
|
unsigned int tx_ring_skbs;
|
|
/* Size of Rx Ring per queue */
|
|
unsigned int rx_ring_size;
|
|
/* Ammount of SKBs allocated to Rx Ring per queue */
|
|
unsigned int rx_ring_skbs;
|
|
|
|
/*
|
|
* rx_task used to fill RX ring out of bottom half context
|
|
*/
|
|
struct work_struct rx_task;
|
|
|
|
/*
|
|
* Used in case RX Ring is empty, which can be caused when
|
|
* system does not have resources (skb's)
|
|
*/
|
|
struct timer_list timeout;
|
|
long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
|
|
unsigned rx_timer_flag;
|
|
|
|
u32 rx_int_coal;
|
|
u32 tx_int_coal;
|
|
};
|
|
|
|
/* ethernet.h API list */
|
|
|
|
/* Port operation control routines */
|
|
static void eth_port_init(struct mv64340_private *mp);
|
|
static void eth_port_reset(unsigned int eth_port_num);
|
|
static int eth_port_start(struct mv64340_private *mp);
|
|
|
|
static void ethernet_set_config_reg(unsigned int eth_port_num,
|
|
unsigned int value);
|
|
static unsigned int ethernet_get_config_reg(unsigned int eth_port_num);
|
|
|
|
/* Port MAC address routines */
|
|
static void eth_port_uc_addr_set(unsigned int eth_port_num,
|
|
unsigned char *p_addr);
|
|
|
|
/* PHY and MIB routines */
|
|
static int ethernet_phy_reset(unsigned int eth_port_num);
|
|
|
|
static int eth_port_write_smi_reg(unsigned int eth_port_num,
|
|
unsigned int phy_reg,
|
|
unsigned int value);
|
|
|
|
static int eth_port_read_smi_reg(unsigned int eth_port_num,
|
|
unsigned int phy_reg,
|
|
unsigned int *value);
|
|
|
|
static void eth_clear_mib_counters(unsigned int eth_port_num);
|
|
|
|
/* Port data flow control routines */
|
|
static ETH_FUNC_RET_STATUS eth_port_send(struct mv64340_private *mp,
|
|
struct pkt_info * p_pkt_info);
|
|
static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv64340_private *mp,
|
|
struct pkt_info * p_pkt_info);
|
|
static ETH_FUNC_RET_STATUS eth_port_receive(struct mv64340_private *mp,
|
|
struct pkt_info * p_pkt_info);
|
|
static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv64340_private *mp,
|
|
struct pkt_info * p_pkt_info);
|
|
|
|
#endif /* __MV64340_ETH_H__ */
|