562 lines
15 KiB
C
562 lines
15 KiB
C
/*
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* Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
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* of PCI-SCSI IO processors.
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*
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* Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
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*
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* This driver is derived from the Linux sym53c8xx driver.
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* Copyright (C) 1998-2000 Gerard Roudier
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*
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* The sym53c8xx driver is derived from the ncr53c8xx driver that had been
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* a port of the FreeBSD ncr driver to Linux-1.2.13.
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*
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* The original ncr driver has been written for 386bsd and FreeBSD by
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* Wolfgang Stanglmeier <wolf@cologne.de>
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* Stefan Esser <se@mi.Uni-Koeln.de>
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* Copyright (C) 1994 Wolfgang Stanglmeier
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*
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* Other major contributions:
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*
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* NVRAM detection and reading.
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* Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
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*
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*-----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef SYM_GLUE_H
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#define SYM_GLUE_H
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#include <linux/config.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/timer.h>
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#include <linux/types.h>
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#include <asm/io.h>
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#ifdef __sparc__
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# include <asm/irq.h>
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#endif
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#include <scsi/scsi.h>
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#include <scsi/scsi_cmnd.h>
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#include <scsi/scsi_device.h>
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#include <scsi/scsi_host.h>
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#ifndef bzero
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#define bzero(d, n) memset((d), 0, (n))
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#endif
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/*
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* General driver includes.
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*/
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#include "sym_conf.h"
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#include "sym_defs.h"
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#include "sym_misc.h"
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/*
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* Configuration addendum for Linux.
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*/
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#define SYM_CONF_TIMER_INTERVAL ((HZ+1)/2)
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#define SYM_OPT_HANDLE_DIR_UNKNOWN
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#define SYM_OPT_HANDLE_DEVICE_QUEUEING
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#define SYM_OPT_LIMIT_COMMAND_REORDERING
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#define SYM_OPT_ANNOUNCE_TRANSFER_RATE
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/*
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* Print a message with severity.
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*/
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#define printf_emerg(args...) printk(KERN_EMERG args)
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#define printf_alert(args...) printk(KERN_ALERT args)
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#define printf_crit(args...) printk(KERN_CRIT args)
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#define printf_err(args...) printk(KERN_ERR args)
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#define printf_warning(args...) printk(KERN_WARNING args)
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#define printf_notice(args...) printk(KERN_NOTICE args)
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#define printf_info(args...) printk(KERN_INFO args)
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#define printf_debug(args...) printk(KERN_DEBUG args)
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#define printf(args...) printk(args)
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/*
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* Insert a delay in micro-seconds
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*/
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#define sym_udelay(us) udelay(us)
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/*
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* A 'read barrier' flushes any data that have been prefetched
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* by the processor due to out of order execution. Such a barrier
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* must notably be inserted prior to looking at data that have
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* been DMAed, assuming that program does memory READs in proper
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* order and that the device ensured proper ordering of WRITEs.
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*
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* A 'write barrier' prevents any previous WRITEs to pass further
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* WRITEs. Such barriers must be inserted each time another agent
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* relies on ordering of WRITEs.
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*
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* Note that, due to posting of PCI memory writes, we also must
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* insert dummy PCI read transactions when some ordering involving
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* both directions over the PCI does matter. PCI transactions are
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* fully ordered in each direction.
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*/
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#define MEMORY_READ_BARRIER() rmb()
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#define MEMORY_WRITE_BARRIER() wmb()
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/*
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* Let the compiler know about driver data structure names.
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*/
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typedef struct sym_tcb *tcb_p;
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typedef struct sym_lcb *lcb_p;
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typedef struct sym_ccb *ccb_p;
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typedef struct sym_hcb *hcb_p;
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/*
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* Define a reference to the O/S dependent IO request.
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*/
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typedef struct scsi_cmnd *cam_ccb_p; /* Generic */
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typedef struct scsi_cmnd *cam_scsiio_p;/* SCSI I/O */
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/*
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* IO functions definition for big/little endian CPU support.
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* For now, PCI chips are only supported in little endian addressing mode,
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*/
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#ifdef __BIG_ENDIAN
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#define inw_l2b inw
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#define inl_l2b inl
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#define outw_b2l outw
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#define outl_b2l outl
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#define readw_l2b readw
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#define readl_l2b readl
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#define writew_b2l writew
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#define writel_b2l writel
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#else /* little endian */
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#define inw_raw inw
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#define inl_raw inl
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#define outw_raw outw
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#define outl_raw outl
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#define readw_raw readw
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#define readl_raw readl
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#define writew_raw writew
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#define writel_raw writel
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#endif /* endian */
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#ifdef SYM_CONF_CHIP_BIG_ENDIAN
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#error "Chips in BIG ENDIAN addressing mode are not (yet) supported"
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#endif
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/*
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* If the chip uses big endian addressing mode over the
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* PCI, actual io register addresses for byte and word
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* accesses must be changed according to lane routing.
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* Btw, sym_offb() and sym_offw() macros only apply to
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* constants and so donnot generate bloated code.
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*/
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#if defined(SYM_CONF_CHIP_BIG_ENDIAN)
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#define sym_offb(o) (((o)&~3)+((~((o)&3))&3))
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#define sym_offw(o) (((o)&~3)+((~((o)&3))&2))
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#else
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#define sym_offb(o) (o)
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#define sym_offw(o) (o)
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#endif
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/*
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* If the CPU and the chip use same endian-ness addressing,
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* no byte reordering is needed for script patching.
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* Macro cpu_to_scr() is to be used for script patching.
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* Macro scr_to_cpu() is to be used for getting a DWORD
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* from the script.
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*/
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#if defined(__BIG_ENDIAN) && !defined(SYM_CONF_CHIP_BIG_ENDIAN)
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#define cpu_to_scr(dw) cpu_to_le32(dw)
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#define scr_to_cpu(dw) le32_to_cpu(dw)
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#elif defined(__LITTLE_ENDIAN) && defined(SYM_CONF_CHIP_BIG_ENDIAN)
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#define cpu_to_scr(dw) cpu_to_be32(dw)
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#define scr_to_cpu(dw) be32_to_cpu(dw)
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#else
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#define cpu_to_scr(dw) (dw)
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#define scr_to_cpu(dw) (dw)
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#endif
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/*
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* Access to the controller chip.
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*
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* If SYM_CONF_IOMAPPED is defined, the driver will use
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* normal IOs instead of the MEMORY MAPPED IO method
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* recommended by PCI specifications.
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* If all PCI bridges, host brigdes and architectures
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* would have been correctly designed for PCI, this
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* option would be useless.
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*
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* If the CPU and the chip use same endian-ness addressing,
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* no byte reordering is needed for accessing chip io
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* registers. Functions suffixed by '_raw' are assumed
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* to access the chip over the PCI without doing byte
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* reordering. Functions suffixed by '_l2b' are
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* assumed to perform little-endian to big-endian byte
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* reordering, those suffixed by '_b2l' blah, blah,
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* blah, ...
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*/
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#if defined(SYM_CONF_IOMAPPED)
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/*
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* IO mapped only input / ouput
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*/
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#define INB_OFF(o) inb (np->s.io_port + sym_offb(o))
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#define OUTB_OFF(o, val) outb ((val), np->s.io_port + sym_offb(o))
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#if defined(__BIG_ENDIAN) && !defined(SYM_CONF_CHIP_BIG_ENDIAN)
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#define INW_OFF(o) inw_l2b (np->s.io_port + sym_offw(o))
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#define INL_OFF(o) inl_l2b (np->s.io_port + (o))
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#define OUTW_OFF(o, val) outw_b2l ((val), np->s.io_port + sym_offw(o))
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#define OUTL_OFF(o, val) outl_b2l ((val), np->s.io_port + (o))
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#elif defined(__LITTLE_ENDIAN) && defined(SYM_CONF_CHIP_BIG_ENDIAN)
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#define INW_OFF(o) inw_b2l (np->s.io_port + sym_offw(o))
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#define INL_OFF(o) inl_b2l (np->s.io_port + (o))
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#define OUTW_OFF(o, val) outw_l2b ((val), np->s.io_port + sym_offw(o))
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#define OUTL_OFF(o, val) outl_l2b ((val), np->s.io_port + (o))
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#else
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#define INW_OFF(o) inw_raw (np->s.io_port + sym_offw(o))
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#define INL_OFF(o) inl_raw (np->s.io_port + (o))
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#define OUTW_OFF(o, val) outw_raw ((val), np->s.io_port + sym_offw(o))
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#define OUTL_OFF(o, val) outl_raw ((val), np->s.io_port + (o))
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#endif /* ENDIANs */
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#else /* defined SYM_CONF_IOMAPPED */
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/*
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* MEMORY mapped IO input / output
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*/
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#define INB_OFF(o) readb(np->s.mmio_va + sym_offb(o))
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#define OUTB_OFF(o, val) writeb((val), np->s.mmio_va + sym_offb(o))
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#if defined(__BIG_ENDIAN) && !defined(SYM_CONF_CHIP_BIG_ENDIAN)
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#define INW_OFF(o) readw_l2b(np->s.mmio_va + sym_offw(o))
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#define INL_OFF(o) readl_l2b(np->s.mmio_va + (o))
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#define OUTW_OFF(o, val) writew_b2l((val), np->s.mmio_va + sym_offw(o))
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#define OUTL_OFF(o, val) writel_b2l((val), np->s.mmio_va + (o))
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#elif defined(__LITTLE_ENDIAN) && defined(SYM_CONF_CHIP_BIG_ENDIAN)
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#define INW_OFF(o) readw_b2l(np->s.mmio_va + sym_offw(o))
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#define INL_OFF(o) readl_b2l(np->s.mmio_va + (o))
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#define OUTW_OFF(o, val) writew_l2b((val), np->s.mmio_va + sym_offw(o))
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#define OUTL_OFF(o, val) writel_l2b((val), np->s.mmio_va + (o))
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#else
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#define INW_OFF(o) readw_raw(np->s.mmio_va + sym_offw(o))
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#define INL_OFF(o) readl_raw(np->s.mmio_va + (o))
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#define OUTW_OFF(o, val) writew_raw((val), np->s.mmio_va + sym_offw(o))
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#define OUTL_OFF(o, val) writel_raw((val), np->s.mmio_va + (o))
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#endif
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#endif /* defined SYM_CONF_IOMAPPED */
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#define OUTRAM_OFF(o, a, l) memcpy_toio(np->s.ram_va + (o), (a), (l))
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/*
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* Remap some status field values.
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*/
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#define CAM_REQ_CMP DID_OK
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#define CAM_SEL_TIMEOUT DID_NO_CONNECT
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#define CAM_CMD_TIMEOUT DID_TIME_OUT
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#define CAM_REQ_ABORTED DID_ABORT
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#define CAM_UNCOR_PARITY DID_PARITY
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#define CAM_SCSI_BUS_RESET DID_RESET
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#define CAM_REQUEUE_REQ DID_SOFT_ERROR
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#define CAM_UNEXP_BUSFREE DID_ERROR
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#define CAM_SCSI_BUSY DID_BUS_BUSY
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#define CAM_DEV_NOT_THERE DID_NO_CONNECT
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#define CAM_REQ_INVALID DID_ERROR
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#define CAM_REQ_TOO_BIG DID_ERROR
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#define CAM_RESRC_UNAVAIL DID_ERROR
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/*
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* Remap data direction values.
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*/
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#define CAM_DIR_NONE DMA_NONE
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#define CAM_DIR_IN DMA_FROM_DEVICE
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#define CAM_DIR_OUT DMA_TO_DEVICE
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#define CAM_DIR_UNKNOWN DMA_BIDIRECTIONAL
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/*
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* These ones are used as return code from
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* error recovery handlers under Linux.
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*/
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#define SCSI_SUCCESS SUCCESS
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#define SCSI_FAILED FAILED
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/*
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* System specific target data structure.
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* None for now, under Linux.
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*/
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/* #define SYM_HAVE_STCB */
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/*
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* System specific lun data structure.
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*/
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#define SYM_HAVE_SLCB
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struct sym_slcb {
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u_short reqtags; /* Number of tags requested by user */
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u_short scdev_depth; /* Queue depth set in select_queue_depth() */
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};
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/*
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* System specific command data structure.
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* Not needed under Linux.
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*/
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/* struct sym_sccb */
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/*
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* System specific host data structure.
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*/
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struct sym_shcb {
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/*
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* Chip and controller indentification.
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*/
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int unit;
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char inst_name[16];
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char chip_name[8];
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struct pci_dev *device;
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struct Scsi_Host *host;
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void __iomem * mmio_va; /* MMIO kernel virtual address */
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void __iomem * ram_va; /* RAM kernel virtual address */
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u_long io_port; /* IO port address cookie */
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u_short io_ws; /* IO window size */
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int irq; /* IRQ number */
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struct timer_list timer; /* Timer handler link header */
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u_long lasttime;
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u_long settle_time; /* Resetting the SCSI BUS */
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u_char settle_time_valid;
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};
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/*
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* Return the name of the controller.
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*/
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#define sym_name(np) (np)->s.inst_name
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/*
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* Data structure used as input for the NVRAM reading.
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* Must resolve the IO macros and sym_name(), when
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* used as sub-field 's' of another structure.
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*/
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struct sym_slot {
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u_long base;
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u_long base_2;
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u_long base_c;
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u_long base_2_c;
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int irq;
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/* port and address fields to fit INB, OUTB macros */
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u_long io_port;
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void __iomem * mmio_va;
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char inst_name[16];
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};
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struct sym_nvram;
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struct sym_device {
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struct pci_dev *pdev;
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struct sym_slot s;
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struct sym_pci_chip chip;
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struct sym_nvram *nvram;
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u_short device_id;
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u_char host_id;
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};
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/*
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* Driver host data structure.
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*/
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struct host_data {
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struct sym_hcb *ncb;
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};
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/*
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* The driver definitions (sym_hipd.h) must know about a
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* couple of things related to the memory allocator.
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*/
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typedef u_long m_addr_t; /* Enough bits to represent any address */
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#define SYM_MEM_PAGE_ORDER 0 /* 1 PAGE maximum */
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#define SYM_MEM_CLUSTER_SHIFT (PAGE_SHIFT+SYM_MEM_PAGE_ORDER)
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#ifdef MODULE
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#define SYM_MEM_FREE_UNUSED /* Free unused pages immediately */
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#endif
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typedef struct pci_dev *m_pool_ident_t;
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/*
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* Include driver soft definitions.
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*/
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#include "sym_fw.h"
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#include "sym_hipd.h"
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/*
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* Memory allocator related stuff.
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*/
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#define SYM_MEM_GFP_FLAGS GFP_ATOMIC
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#define SYM_MEM_WARN 1 /* Warn on failed operations */
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#define sym_get_mem_cluster() \
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__get_free_pages(SYM_MEM_GFP_FLAGS, SYM_MEM_PAGE_ORDER)
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#define sym_free_mem_cluster(p) \
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free_pages(p, SYM_MEM_PAGE_ORDER)
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void *sym_calloc(int size, char *name);
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void sym_mfree(void *m, int size, char *name);
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/*
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* We have to provide the driver memory allocator with methods for
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* it to maintain virtual to bus physical address translations.
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*/
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#define sym_m_pool_match(mp_id1, mp_id2) (mp_id1 == mp_id2)
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static __inline m_addr_t sym_m_get_dma_mem_cluster(m_pool_p mp, m_vtob_p vbp)
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{
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void *vaddr = NULL;
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dma_addr_t baddr = 0;
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vaddr = pci_alloc_consistent(mp->dev_dmat,SYM_MEM_CLUSTER_SIZE, &baddr);
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if (vaddr) {
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vbp->vaddr = (m_addr_t) vaddr;
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vbp->baddr = (m_addr_t) baddr;
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}
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return (m_addr_t) vaddr;
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}
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static __inline void sym_m_free_dma_mem_cluster(m_pool_p mp, m_vtob_p vbp)
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{
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pci_free_consistent(mp->dev_dmat, SYM_MEM_CLUSTER_SIZE,
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(void *)vbp->vaddr, (dma_addr_t)vbp->baddr);
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}
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#define sym_m_create_dma_mem_tag(mp) (0)
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#define sym_m_delete_dma_mem_tag(mp) do { ; } while (0)
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void *__sym_calloc_dma(m_pool_ident_t dev_dmat, int size, char *name);
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void __sym_mfree_dma(m_pool_ident_t dev_dmat, void *m, int size, char *name);
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m_addr_t __vtobus(m_pool_ident_t dev_dmat, void *m);
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/*
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* Set the status field of a CAM CCB.
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*/
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static __inline void
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sym_set_cam_status(struct scsi_cmnd *ccb, int status)
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{
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ccb->result &= ~(0xff << 16);
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ccb->result |= (status << 16);
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}
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/*
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* Get the status field of a CAM CCB.
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*/
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static __inline int
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sym_get_cam_status(struct scsi_cmnd *ccb)
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{
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return ((ccb->result >> 16) & 0xff);
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}
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/*
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* The dma mapping is mostly handled by the
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* SCSI layer and the driver glue under Linux.
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*/
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#define sym_data_dmamap_create(np, cp) (0)
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#define sym_data_dmamap_destroy(np, cp) do { ; } while (0)
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#define sym_data_dmamap_unload(np, cp) do { ; } while (0)
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#define sym_data_dmamap_presync(np, cp) do { ; } while (0)
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#define sym_data_dmamap_postsync(np, cp) do { ; } while (0)
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/*
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* Async handler for negotiations.
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*/
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void sym_xpt_async_nego_wide(hcb_p np, int target);
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#define sym_xpt_async_nego_sync(np, target) \
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sym_announce_transfer_rate(np, target)
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#define sym_xpt_async_nego_ppr(np, target) \
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sym_announce_transfer_rate(np, target)
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/*
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* Build CAM result for a successful IO and for a failed IO.
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*/
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static __inline void sym_set_cam_result_ok(hcb_p np, ccb_p cp, int resid)
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{
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struct scsi_cmnd *cmd = cp->cam_ccb;
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cmd->resid = resid;
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cmd->result = (((DID_OK) << 16) + ((cp->ssss_status) & 0x7f));
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}
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void sym_set_cam_result_error(hcb_p np, ccb_p cp, int resid);
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/*
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* Other O/S specific methods.
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*/
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#define sym_cam_target_id(ccb) (ccb)->target
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#define sym_cam_target_lun(ccb) (ccb)->lun
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#define sym_freeze_cam_ccb(ccb) do { ; } while (0)
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void sym_xpt_done(hcb_p np, cam_ccb_p ccb);
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void sym_xpt_done2(hcb_p np, cam_ccb_p ccb, int cam_status);
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void sym_print_addr (ccb_p cp);
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void sym_xpt_async_bus_reset(hcb_p np);
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void sym_xpt_async_sent_bdr(hcb_p np, int target);
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int sym_setup_data_and_start (hcb_p np, cam_scsiio_p csio, ccb_p cp);
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void sym_log_bus_error(hcb_p np);
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void sym_sniff_inquiry(hcb_p np, struct scsi_cmnd *cmd, int resid);
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#endif /* SYM_GLUE_H */
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