313 lines
12 KiB
C
313 lines
12 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (c) 1992-1999,2001-2004 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_IA64_SN_ADDRS_H
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#define _ASM_IA64_SN_ADDRS_H
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/* McKinley Address Format:
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*
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* 4 4 3 3 3 3
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* 9 8 8 7 6 5 0
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* +-+---------+----+--------------+
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* |0| Node ID | AS | Node Offset |
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* +-+---------+----+--------------+
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*
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* Node ID: If bit 38 = 1, is ICE, else is SHUB
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* AS: Address Space Identifier. Used only if bit 38 = 0.
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* b'00: Local Resources and MMR space
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* bit 35
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* 0: Local resources space
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* node id:
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* 0: IA64/NT compatibility space
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* 2: Local MMR Space
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* 4: Local memory, regardless of local node id
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* 1: Global MMR space
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* b'01: GET space.
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* b'10: AMO space.
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* b'11: Cacheable memory space.
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*
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* NodeOffset: byte offset
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*/
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/* TIO address format:
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* 4 4 3 3 3 3 3 0
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* 9 8 8 7 6 5 4
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* +-+----------+-+---+--------------+
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* |0| Node ID |0|CID| Node offset |
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* +-+----------+-+---+--------------+
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*
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* Node ID: if bit 38 == 1, is ICE.
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* Bit 37: Must be zero.
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* CID: Chiplet ID:
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* b'01: TIO LB (Indicates TIO MMR access.)
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* b'11: TIO ICE (indicates coretalk space access.)
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* Node offset: byte offest.
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*/
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/*
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* Note that in both of the above address formats, bit
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* 35 set indicates that the reference is to the
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* shub or tio MMRs.
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*/
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#ifndef __ASSEMBLY__
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typedef union ia64_sn2_pa {
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struct {
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unsigned long off : 36;
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unsigned long as : 2;
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unsigned long nasid: 11;
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unsigned long fill : 15;
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} f;
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unsigned long l;
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void *p;
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} ia64_sn2_pa_t;
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#endif
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#define TO_PHYS_MASK 0x0001ffcfffffffffUL /* Note - clear AS bits */
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/* Regions determined by AS */
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#define LOCAL_MMR_SPACE 0xc000008000000000UL /* Local MMR space */
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#define LOCAL_PHYS_MMR_SPACE 0x8000008000000000UL /* Local PhysicalMMR space */
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#define LOCAL_MEM_SPACE 0xc000010000000000UL /* Local Memory space */
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/* It so happens that setting bit 35 indicates a reference to the SHUB or TIO
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* MMR space.
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*/
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#define GLOBAL_MMR_SPACE 0xc000000800000000UL /* Global MMR space */
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#define TIO_MMR_SPACE 0xc000000800000000UL /* TIO MMR space */
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#define ICE_MMR_SPACE 0xc000000000000000UL /* ICE MMR space */
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#define GLOBAL_PHYS_MMR_SPACE 0x0000000800000000UL /* Global Physical MMR space */
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#define GET_SPACE 0xe000001000000000UL /* GET space */
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#define AMO_SPACE 0xc000002000000000UL /* AMO space */
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#define CACHEABLE_MEM_SPACE 0xe000003000000000UL /* Cacheable memory space */
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#define UNCACHED 0xc000000000000000UL /* UnCacheable memory space */
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#define UNCACHED_PHYS 0x8000000000000000UL /* UnCacheable physical memory space */
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#define PHYS_MEM_SPACE 0x0000003000000000UL /* physical memory space */
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/* SN2 address macros */
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/* NID_SHFT has the right value for both SHUB and TIO addresses.*/
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#define NID_SHFT 38
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#define LOCAL_MMR_ADDR(a) (UNCACHED | LOCAL_MMR_SPACE | (a))
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#define LOCAL_MMR_PHYS_ADDR(a) (UNCACHED_PHYS | LOCAL_PHYS_MMR_SPACE | (a))
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#define LOCAL_MEM_ADDR(a) (LOCAL_MEM_SPACE | (a))
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#define REMOTE_ADDR(n,a) ((((unsigned long)(n))<<NID_SHFT) | (a))
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#define GLOBAL_MMR_ADDR(n,a) (UNCACHED | GLOBAL_MMR_SPACE | REMOTE_ADDR(n,a))
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#define GLOBAL_MMR_PHYS_ADDR(n,a) (UNCACHED_PHYS | GLOBAL_PHYS_MMR_SPACE | REMOTE_ADDR(n,a))
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#define GET_ADDR(n,a) (GET_SPACE | REMOTE_ADDR(n,a))
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#define AMO_ADDR(n,a) (UNCACHED | AMO_SPACE | REMOTE_ADDR(n,a))
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#define GLOBAL_MEM_ADDR(n,a) (CACHEABLE_MEM_SPACE | REMOTE_ADDR(n,a))
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/* non-II mmr's start at top of big window space (4G) */
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#define BWIN_TOP 0x0000000100000000UL
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/*
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* general address defines - for code common to SN0/SN1/SN2
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*/
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#define CAC_BASE CACHEABLE_MEM_SPACE /* cacheable memory space */
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#define IO_BASE (UNCACHED | GLOBAL_MMR_SPACE) /* lower 4G maps II's XIO space */
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#define TIO_BASE (UNCACHED | ICE_MMR_SPACE) /* lower 4G maps TIO space */
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#define AMO_BASE (UNCACHED | AMO_SPACE) /* fetch & op space */
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#define MSPEC_BASE AMO_BASE /* fetch & op space */
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#define UNCAC_BASE (UNCACHED | CACHEABLE_MEM_SPACE) /* uncached global memory */
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#define GET_BASE GET_SPACE /* momentarily coherent remote mem. */
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#define CALIAS_BASE LOCAL_CACHEABLE_BASE /* cached node-local memory */
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#define UALIAS_BASE (UNCACHED | LOCAL_CACHEABLE_BASE) /* uncached node-local memory */
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#define TO_PHYS(x) ( ((x) & TO_PHYS_MASK))
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#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK))
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#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK))
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#define TO_MSPEC(x) (MSPEC_BASE | ((x) & TO_PHYS_MASK))
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#define TO_GET(x) (GET_BASE | ((x) & TO_PHYS_MASK))
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#define TO_CALIAS(x) (CALIAS_BASE | TO_NODE_ADDRSPACE(x))
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#define TO_UALIAS(x) (UALIAS_BASE | TO_NODE_ADDRSPACE(x))
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#define NODE_SIZE_BITS 36 /* node offset : bits <35:0> */
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#define BWIN_SIZE_BITS 29 /* big window size: 512M */
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#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
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#define NASID_BITS 11 /* bits <48:38> */
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#define NASID_BITMASK (0x7ffULL)
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#define NASID_SHFT NID_SHFT
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#define NASID_META_BITS 0 /* ???? */
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#define NASID_LOCAL_BITS 7 /* same router as SN1 */
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#define NODE_ADDRSPACE_SIZE (1UL << NODE_SIZE_BITS)
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#define NASID_MASK ((uint64_t) NASID_BITMASK << NASID_SHFT)
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#define NASID_GET(_pa) (int) (((uint64_t) (_pa) >> \
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NASID_SHFT) & NASID_BITMASK)
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#define PHYS_TO_DMA(x) ( ((x & NASID_MASK) >> 2) | \
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(x & (NODE_ADDRSPACE_SIZE - 1)) )
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/*
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* This address requires a chiplet id in bits 38-39. For DMA to memory,
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* the chiplet id is zero. If we implement TIO-TIO dma, we might need
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* to insert a chiplet id into this macro. However, it is our belief
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* right now that this chiplet id will be ICE, which is also zero.
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*/
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#define PHYS_TO_TIODMA(x) ( ((x & NASID_MASK) << 2) | \
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(x & (NODE_ADDRSPACE_SIZE - 1)) )
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#define CHANGE_NASID(n,x) ({ia64_sn2_pa_t _v; _v.l = (long) (x); _v.f.nasid = n; _v.p;})
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#ifndef __ASSEMBLY__
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#define NODE_SWIN_BASE(nasid, widget) \
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((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
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: RAW_NODE_SWIN_BASE(nasid, widget))
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#else
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#define NODE_SWIN_BASE(nasid, widget) \
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(NODE_IO_BASE(nasid) + ((uint64_t) (widget) << SWIN_SIZE_BITS))
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#define LOCAL_SWIN_BASE(widget) \
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(UNCACHED | LOCAL_MMR_SPACE | (((uint64_t) (widget) << SWIN_SIZE_BITS)))
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#endif /* __ASSEMBLY__ */
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/*
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* The following definitions pertain to the IO special address
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* space. They define the location of the big and little windows
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* of any given node.
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*/
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#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
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#define BWIN_SIZEMASK (BWIN_SIZE - 1)
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#define BWIN_WIDGET_MASK 0x7
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#define NODE_BWIN_BASE0(nasid) (NODE_IO_BASE(nasid) + BWIN_SIZE)
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#define NODE_BWIN_BASE(nasid, bigwin) (NODE_BWIN_BASE0(nasid) + \
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((uint64_t) (bigwin) << BWIN_SIZE_BITS))
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#define BWIN_WIDGETADDR(addr) ((addr) & BWIN_SIZEMASK)
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#define BWIN_WINDOWNUM(addr) (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
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#define TIO_BWIN_WINDOW_SELECT_MASK 0x7
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#define TIO_BWIN_WINDOWNUM(addr) (((addr) >> TIO_BWIN_SIZE_BITS) & TIO_BWIN_WINDOW_SELECT_MASK)
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#ifndef __ASSEMBLY__
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#include <asm/sn/types.h>
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#endif
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/*
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* The following macros are used to index to the beginning of a specific
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* node's address space.
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*/
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#define NODE_OFFSET(_n) ((uint64_t) (_n) << NASID_SHFT)
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#define NODE_CAC_BASE(_n) (CAC_BASE + NODE_OFFSET(_n))
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#define NODE_HSPEC_BASE(_n) (HSPEC_BASE + NODE_OFFSET(_n))
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#define NODE_IO_BASE(_n) (IO_BASE + NODE_OFFSET(_n))
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#define NODE_MSPEC_BASE(_n) (MSPEC_BASE + NODE_OFFSET(_n))
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#define NODE_UNCAC_BASE(_n) (UNCAC_BASE + NODE_OFFSET(_n))
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#define TO_NODE_CAC(_n, _x) (NODE_CAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
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#define RAW_NODE_SWIN_BASE(nasid, widget) \
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(NODE_IO_BASE(nasid) + ((uint64_t) (widget) << SWIN_SIZE_BITS))
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/*
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* The following definitions pertain to the IO special address
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* space. They define the location of the big and little windows
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* of any given node.
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*/
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#define SWIN_SIZE_BITS 24
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#define SWIN_SIZE (1UL << 24)
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#define SWIN_SIZEMASK (SWIN_SIZE - 1)
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#define SWIN_WIDGET_MASK 0xF
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#define TIO_SWIN_SIZE_BITS 28
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#define TIO_SWIN_SIZE (1UL << 28)
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#define TIO_SWIN_SIZEMASK (SWIN_SIZE - 1)
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#define TIO_SWIN_WIDGET_MASK 0x3
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/*
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* Convert smallwindow address to xtalk address.
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*
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* 'addr' can be physical or virtual address, but will be converted
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* to Xtalk address in the range 0 -> SWINZ_SIZEMASK
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*/
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#define SWIN_WIDGETNUM(addr) (((addr) >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
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#define TIO_SWIN_WIDGETNUM(addr) (((addr) >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
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/*
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* The following macros produce the correct base virtual address for
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* the hub registers. The LOCAL_HUB_* macros produce the appropriate
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* address for the local registers. The REMOTE_HUB_* macro produce
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* the address for the specified hub's registers. The intent is
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* that the appropriate PI, MD, NI, or II register would be substituted
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* for _x.
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*/
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/*
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* SN2 has II mmr's located inside small window space.
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* As all other non-II mmr's located at the top of big window
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* space.
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*/
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#define REMOTE_HUB_BASE(_x) \
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(UNCACHED | GLOBAL_MMR_SPACE | \
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(((~(_x)) & BWIN_TOP)>>8) | \
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(((~(_x)) & BWIN_TOP)>>9) | (_x))
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#define REMOTE_HUB(_n, _x) \
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((uint64_t *)(REMOTE_HUB_BASE(_x) | ((((long)(_n))<<NASID_SHFT))))
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/*
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* WARNING:
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* When certain Hub chip workaround are defined, it's not sufficient
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* to dereference the *_HUB_ADDR() macros. You should instead use
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* HUB_L() and HUB_S() if you must deal with pointers to hub registers.
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* Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
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* They're always safe.
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*/
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/*
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* LOCAL_HUB_ADDR doesn't need to be changed for TIO, since, by definition,
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* there are no "local" TIOs.
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*/
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#define LOCAL_HUB_ADDR(_x) \
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(((_x) & BWIN_TOP) ? ((volatile uint64_t *)(LOCAL_MMR_ADDR(_x))) \
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: ((volatile uint64_t *)(IALIAS_BASE + (_x))))
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#define REMOTE_HUB_ADDR(_n, _x) \
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((_n & 1) ? \
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/* TIO: */ \
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((volatile uint64_t *)(GLOBAL_MMR_ADDR(_n, _x))) \
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: /* SHUB: */ \
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(((_x) & BWIN_TOP) ? ((volatile uint64_t *)(GLOBAL_MMR_ADDR(_n, _x))) \
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: ((volatile uint64_t *)(NODE_SWIN_BASE(_n, 1) + 0x800000 + (_x)))))
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#ifndef __ASSEMBLY__
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#define HUB_L(_a) (*((volatile typeof(*_a) *)_a))
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#define HUB_S(_a, _d) (*((volatile typeof(*_a) *)_a) = (_d))
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#define LOCAL_HUB_L(_r) HUB_L(LOCAL_HUB_ADDR(_r))
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#define LOCAL_HUB_S(_r, _d) HUB_S(LOCAL_HUB_ADDR(_r), (_d))
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#define REMOTE_HUB_L(_n, _r) HUB_L(REMOTE_HUB_ADDR((_n), (_r)))
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#define REMOTE_HUB_S(_n, _r, _d) HUB_S(REMOTE_HUB_ADDR((_n), (_r)), (_d))
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#define REMOTE_HUB_PI_L(_n, _sn, _r) HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
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#define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
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#endif /* __ASSEMBLY__ */
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/*
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* The following macros are used to get to a hub/bridge register, given
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* the base of the register space.
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*/
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#define HUB_REG_PTR(_base, _off) \
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(volatile uint64_t *)((unsigned long)(_base) + (__psunsigned_t)(_off)))
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#define HUB_REG_PTR_L(_base, _off) \
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HUB_L(HUB_REG_PTR((_base), (_off)))
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#define HUB_REG_PTR_S(_base, _off, _data) \
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HUB_S(HUB_REG_PTR((_base), (_off)), (_data))
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#endif /* _ASM_IA64_SN_ADDRS_H */
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