145 lines
5.0 KiB
C
145 lines
5.0 KiB
C
/*
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* include/asm-ppc/mpc85xx.h
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*
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* MPC85xx definitions
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*
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* Maintainer: Kumar Gala <kumar.gala@freescale.com>
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*
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* Copyright 2004 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_MPC85xx_H__
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#define __ASM_MPC85xx_H__
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#include <linux/config.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_85xx
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#ifdef CONFIG_MPC8540_ADS
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#include <platforms/85xx/mpc8540_ads.h>
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#endif
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#ifdef CONFIG_MPC8555_CDS
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#include <platforms/85xx/mpc8555_cds.h>
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#endif
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#ifdef CONFIG_MPC8560_ADS
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#include <platforms/85xx/mpc8560_ads.h>
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#endif
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#ifdef CONFIG_SBC8560
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#include <platforms/85xx/sbc8560.h>
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#endif
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#define _IO_BASE isa_io_base
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#define _ISA_MEM_BASE isa_mem_base
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#ifdef CONFIG_PCI
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#define PCI_DRAM_OFFSET pci_dram_offset
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#else
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#define PCI_DRAM_OFFSET 0
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#endif
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/*
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* The "residual" board information structure the boot loader passes
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* into the kernel.
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*/
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extern unsigned char __res[];
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/* Internal IRQs on MPC85xx OpenPIC */
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/* Not all of these exist on all MPC85xx implementations */
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#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
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#define MPC85xx_OPENPIC_IRQ_OFFSET 64
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#endif
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/* The 32 internal sources */
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#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
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/* The 12 external interrupt lines */
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#define MPC85xx_IRQ_EXT0 (32 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT1 (33 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT2 (34 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT3 (35 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT4 (36 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT5 (37 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT6 (38 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT7 (39 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT8 (40 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT9 (41 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT10 (42 + MPC85xx_OPENPIC_IRQ_OFFSET)
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#define MPC85xx_IRQ_EXT11 (43 + MPC85xx_OPENPIC_IRQ_OFFSET)
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/* Offset from CCSRBAR */
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#define MPC85xx_CPM_OFFSET (0x80000)
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#define MPC85xx_CPM_SIZE (0x40000)
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#define MPC85xx_DMA_OFFSET (0x21000)
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#define MPC85xx_DMA_SIZE (0x01000)
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#define MPC85xx_ENET1_OFFSET (0x24000)
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#define MPC85xx_ENET1_SIZE (0x01000)
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#define MPC85xx_ENET2_OFFSET (0x25000)
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#define MPC85xx_ENET2_SIZE (0x01000)
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#define MPC85xx_ENET3_OFFSET (0x26000)
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#define MPC85xx_ENET3_SIZE (0x01000)
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#define MPC85xx_GUTS_OFFSET (0xe0000)
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#define MPC85xx_GUTS_SIZE (0x01000)
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#define MPC85xx_IIC1_OFFSET (0x03000)
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#define MPC85xx_IIC1_SIZE (0x01000)
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#define MPC85xx_OPENPIC_OFFSET (0x40000)
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#define MPC85xx_OPENPIC_SIZE (0x40000)
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#define MPC85xx_PCI1_OFFSET (0x08000)
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#define MPC85xx_PCI1_SIZE (0x01000)
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#define MPC85xx_PCI2_OFFSET (0x09000)
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#define MPC85xx_PCI2_SIZE (0x01000)
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#define MPC85xx_PERFMON_OFFSET (0xe1000)
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#define MPC85xx_PERFMON_SIZE (0x01000)
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#define MPC85xx_SEC2_OFFSET (0x30000)
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#define MPC85xx_SEC2_SIZE (0x10000)
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#define MPC85xx_UART0_OFFSET (0x04500)
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#define MPC85xx_UART0_SIZE (0x00100)
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#define MPC85xx_UART1_OFFSET (0x04600)
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#define MPC85xx_UART1_SIZE (0x00100)
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#define MPC85xx_CCSRBAR_SIZE (1024*1024)
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/* Let modules/drivers get at CCSRBAR */
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extern phys_addr_t get_ccsrbar(void);
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#ifdef MODULE
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#define CCSRBAR get_ccsrbar()
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#else
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#define CCSRBAR BOARD_CCSRBAR
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#endif
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#endif /* CONFIG_85xx */
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#endif /* __ASM_MPC85xx_H__ */
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#endif /* __KERNEL__ */
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