135 lines
6.6 KiB
C
135 lines
6.6 KiB
C
/*
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* ItLpPaca.h
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* Copyright (C) 2001 Mike Corrigan IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ITLPPACA_H
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#define _ITLPPACA_H
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//=============================================================================
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//
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// This control block contains the data that is shared between the
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// hypervisor (PLIC) and the OS.
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//
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//
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//----------------------------------------------------------------------------
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#include <asm/types.h>
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struct ItLpPaca
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{
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//=============================================================================
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// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
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// NOTE: The xDynXyz fields are fields that will be dynamically changed by
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// PLIC when preparing to bring a processor online or when dispatching a
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// virtual processor!
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//=============================================================================
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u32 xDesc; // Eye catcher 0xD397D781 x00-x03
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u16 xSize; // Size of this struct x04-x05
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u16 xRsvd1_0; // Reserved x06-x07
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u16 xRsvd1_1:14; // Reserved x08-x09
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u8 xSharedProc:1; // Shared processor indicator ...
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u8 xSecondaryThread:1; // Secondary thread indicator ...
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volatile u8 xDynProcStatus:8; // Dynamic Status of this proc x0A-x0A
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u8 xSecondaryThreadCnt; // Secondary thread count x0B-x0B
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volatile u16 xDynHvPhysicalProcIndex;// Dynamic HV Physical Proc Index0C-x0D
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volatile u16 xDynHvLogicalProcIndex;// Dynamic HV Logical Proc Indexx0E-x0F
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u32 xDecrVal; // Value for Decr programming x10-x13
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u32 xPMCVal; // Value for PMC regs x14-x17
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volatile u32 xDynHwNodeId; // Dynamic Hardware Node id x18-x1B
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volatile u32 xDynHwProcId; // Dynamic Hardware Proc Id x1C-x1F
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volatile u32 xDynPIR; // Dynamic ProcIdReg value x20-x23
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u32 xDseiData; // DSEI data x24-x27
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u64 xSPRG3; // SPRG3 value x28-x2F
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u8 xRsvd1_3[80]; // Reserved x30-x7F
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//=============================================================================
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// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
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//=============================================================================
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// This Dword contains a byte for each type of interrupt that can occur.
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// The IPI is a count while the others are just a binary 1 or 0.
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union {
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u64 xAnyInt;
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struct {
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u16 xRsvd; // Reserved - cleared by #mpasmbl
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u8 xXirrInt; // Indicates xXirrValue is valid or Immed IO
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u8 xIpiCnt; // IPI Count
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u8 xDecrInt; // DECR interrupt occurred
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u8 xPdcInt; // PDC interrupt occurred
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u8 xQuantumInt; // Interrupt quantum reached
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u8 xOldPlicDeferredExtInt; // Old PLIC has a deferred XIRR pending
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} xFields;
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} xIntDword;
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// Whenever any fields in this Dword are set then PLIC will defer the
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// processing of external interrupts. Note that PLIC will store the
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// XIRR directly into the xXirrValue field so that another XIRR will
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// not be presented until this one clears. The layout of the low
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// 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
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// entire Dword is zero or not. A non-zero value in the low order
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// 2-bytes will result in SLIC being granted the highest thread
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// priority upon return. A 0 will return to SLIC as medium priority.
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u64 xPlicDeferIntsArea; // Entire Dword
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// Used to pass the real SRR0/1 from PLIC to SLIC as well as to
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// pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
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u64 xSavedSrr0; // Saved SRR0 x10-x17
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u64 xSavedSrr1; // Saved SRR1 x18-x1F
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// Used to pass parms from the OS to PLIC for SetAsrAndRfid
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u64 xSavedGpr3; // Saved GPR3 x20-x27
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u64 xSavedGpr4; // Saved GPR4 x28-x2F
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u64 xSavedGpr5; // Saved GPR5 x30-x37
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u8 xRsvd2_1; // Reserved x38-x38
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u8 xCpuCtlsTaskAttributes; // Task attributes for cpuctls x39-x39
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u8 xFPRegsInUse; // FP regs in use x3A-x3A
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u8 xPMCRegsInUse; // PMC regs in use x3B-x3B
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volatile u32 xSavedDecr; // Saved Decr Value x3C-x3F
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volatile u64 xEmulatedTimeBase;// Emulated TB for this thread x40-x47
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volatile u64 xCurPLICLatency; // Unaccounted PLIC latency x48-x4F
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u64 xTotPLICLatency; // Accumulated PLIC latency x50-x57
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u64 xWaitStateCycles; // Wait cycles for this proc x58-x5F
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u64 xEndOfQuantum; // TB at end of quantum x60-x67
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u64 xPDCSavedSPRG1; // Saved SPRG1 for PMC int x68-x6F
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u64 xPDCSavedSRR0; // Saved SRR0 for PMC int x70-x77
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volatile u32 xVirtualDecr; // Virtual DECR for shared procsx78-x7B
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u16 xSLBCount; // # of SLBs to maintain x7C-x7D
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u8 xIdle; // Indicate OS is idle x7E
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u8 xRsvd2_2; // Reserved x7F
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//=============================================================================
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// CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors
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//=============================================================================
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// This is the xYieldCount. An "odd" value (low bit on) means that
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// the processor is yielded (either because of an OS yield or a PLIC
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// preempt). An even value implies that the processor is currently
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// executing.
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// NOTE: This value will ALWAYS be zero for dedicated processors and
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// will NEVER be zero for shared processors (ie, initialized to a 1).
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volatile u32 xYieldCount; // PLIC increments each dispatchx00-x03
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u8 xRsvd3_0[124]; // Reserved x04-x7F
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//=============================================================================
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// CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data
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//=============================================================================
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u8 xPmcSaveArea[256]; // PMC interrupt Area x00-xFF
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};
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#endif /* _ITLPPACA_H */
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