131 lines
2.9 KiB
C
131 lines
2.9 KiB
C
/* The CPM2 internal interrupt controller. It is usually
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* the only interrupt controller.
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* There are two 32-bit registers (high/low) for up to 64
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* possible interrupts.
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*
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* Now, the fun starts.....Interrupt Numbers DO NOT MAP
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* in a simple arithmetic fashion to mask or pending registers.
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* That is, interrupt 4 does not map to bit position 4.
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* We create two tables, indexed by vector number, to indicate
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* which register to use and which bit in the register to use.
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*/
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/irq.h>
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#include <asm/immap_cpm2.h>
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#include <asm/mpc8260.h>
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#include "cpm2_pic.h"
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static u_char irq_to_siureg[] = {
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0
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};
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static u_char irq_to_siubit[] = {
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31, 16, 17, 18, 19, 20, 21, 22,
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23, 24, 25, 26, 27, 28, 29, 30,
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29, 30, 16, 17, 18, 19, 20, 21,
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22, 23, 24, 25, 26, 27, 28, 31,
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0, 1, 2, 3, 4, 5, 6, 7,
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8, 9, 10, 11, 12, 13, 14, 15,
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15, 14, 13, 12, 11, 10, 9, 8,
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7, 6, 5, 4, 3, 2, 1, 0
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};
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static void cpm2_mask_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
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simr[word] = ppc_cached_irq_mask[word];
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}
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static void cpm2_unmask_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] |= (1 << (31 - bit));
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simr[word] = ppc_cached_irq_mask[word];
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}
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static void cpm2_mask_and_ack(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr, *sipnr;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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sipnr = &(cpm2_immr->im_intctl.ic_sipnrh);
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ppc_cached_irq_mask[word] &= ~(1 << (31 - bit));
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simr[word] = ppc_cached_irq_mask[word];
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sipnr[word] = 1 << (31 - bit);
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}
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static void cpm2_end_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
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&& irq_desc[irq_nr].action) {
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_immr->im_intctl.ic_simrh);
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ppc_cached_irq_mask[word] |= (1 << (31 - bit));
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simr[word] = ppc_cached_irq_mask[word];
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}
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}
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struct hw_interrupt_type cpm2_pic = {
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" CPM2 SIU ",
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NULL,
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NULL,
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cpm2_unmask_irq,
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cpm2_mask_irq,
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cpm2_mask_and_ack,
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cpm2_end_irq,
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0
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};
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int
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cpm2_get_irq(struct pt_regs *regs)
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{
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int irq;
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unsigned long bits;
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/* For CPM2, read the SIVEC register and shift the bits down
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* to get the irq number. */
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bits = cpm2_immr->im_intctl.ic_sivec;
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irq = bits >> 26;
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if (irq == 0)
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return(-1);
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return irq;
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}
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