484 lines
14 KiB
C
484 lines
14 KiB
C
#ifndef HPT366_H
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#define HPT366_H
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#include <linux/config.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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/* various tuning parameters */
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#define HPT_RESET_STATE_ENGINE
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#undef HPT_DELAY_INTERRUPT
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#undef HPT_SERIALIZE_IO
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static const char *quirk_drives[] = {
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"QUANTUM FIREBALLlct08 08",
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"QUANTUM FIREBALLP KA6.4",
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"QUANTUM FIREBALLP LM20.4",
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"QUANTUM FIREBALLP LM20.5",
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NULL
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};
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static const char *bad_ata100_5[] = {
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"IBM-DTLA-307075",
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"IBM-DTLA-307060",
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"IBM-DTLA-307045",
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"IBM-DTLA-307030",
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"IBM-DTLA-307020",
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"IBM-DTLA-307015",
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"IBM-DTLA-305040",
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"IBM-DTLA-305030",
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"IBM-DTLA-305020",
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"IC35L010AVER07-0",
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"IC35L020AVER07-0",
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"IC35L030AVER07-0",
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"IC35L040AVER07-0",
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"IC35L060AVER07-0",
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"WDC AC310200R",
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NULL
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};
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static const char *bad_ata66_4[] = {
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"IBM-DTLA-307075",
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"IBM-DTLA-307060",
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"IBM-DTLA-307045",
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"IBM-DTLA-307030",
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"IBM-DTLA-307020",
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"IBM-DTLA-307015",
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"IBM-DTLA-305040",
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"IBM-DTLA-305030",
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"IBM-DTLA-305020",
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"IC35L010AVER07-0",
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"IC35L020AVER07-0",
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"IC35L030AVER07-0",
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"IC35L040AVER07-0",
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"IC35L060AVER07-0",
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"WDC AC310200R",
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NULL
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};
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static const char *bad_ata66_3[] = {
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"WDC AC310200R",
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NULL
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};
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static const char *bad_ata33[] = {
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"Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
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"Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
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"Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
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"Maxtor 90510D4",
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"Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
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"Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
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"Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
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NULL
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};
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struct chipset_bus_clock_list_entry {
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byte xfer_speed;
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unsigned int chipset_settings;
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};
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/* key for bus clock timings
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* bit
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* 0:3 data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
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* DMA. cycles = value + 1
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* 4:8 data_low_time. active time of DIOW_/DIOR_ for PIO and MW
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* DMA. cycles = value + 1
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* 9:12 cmd_high_time. inactive time of DIOW_/DIOR_ during task file
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* register access.
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* 13:17 cmd_low_time. active time of DIOW_/DIOR_ during task file
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* register access.
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* 18:21 udma_cycle_time. clock freq and clock cycles for UDMA xfer.
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* during task file register access.
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* 22:24 pre_high_time. time to initialize 1st cycle for PIO and MW DMA
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* xfer.
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* 25:27 cmd_pre_high_time. time to initialize 1st PIO cycle for task
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* register access.
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* 28 UDMA enable
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* 29 DMA enable
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* 30 PIO_MST enable. if set, the chip is in bus master mode during
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* PIO.
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* 31 FIFO enable.
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*/
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static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
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{ XFER_UDMA_4, 0x900fd943 },
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{ XFER_UDMA_3, 0x900ad943 },
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{ XFER_UDMA_2, 0x900bd943 },
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{ XFER_UDMA_1, 0x9008d943 },
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{ XFER_UDMA_0, 0x9008d943 },
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{ XFER_MW_DMA_2, 0xa008d943 },
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{ XFER_MW_DMA_1, 0xa010d955 },
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{ XFER_MW_DMA_0, 0xa010d9fc },
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{ XFER_PIO_4, 0xc008d963 },
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{ XFER_PIO_3, 0xc010d974 },
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{ XFER_PIO_2, 0xc010d997 },
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{ XFER_PIO_1, 0xc010d9c7 },
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{ XFER_PIO_0, 0xc018d9d9 },
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{ 0, 0x0120d9d9 }
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};
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static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
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{ XFER_UDMA_4, 0x90c9a731 },
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{ XFER_UDMA_3, 0x90cfa731 },
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{ XFER_UDMA_2, 0x90caa731 },
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{ XFER_UDMA_1, 0x90cba731 },
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{ XFER_UDMA_0, 0x90c8a731 },
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{ XFER_MW_DMA_2, 0xa0c8a731 },
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{ XFER_MW_DMA_1, 0xa0c8a732 }, /* 0xa0c8a733 */
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{ XFER_MW_DMA_0, 0xa0c8a797 },
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{ XFER_PIO_4, 0xc0c8a731 },
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{ XFER_PIO_3, 0xc0c8a742 },
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{ XFER_PIO_2, 0xc0d0a753 },
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{ XFER_PIO_1, 0xc0d0a7a3 }, /* 0xc0d0a793 */
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{ XFER_PIO_0, 0xc0d0a7aa }, /* 0xc0d0a7a7 */
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{ 0, 0x0120a7a7 }
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};
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static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
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{ XFER_UDMA_4, 0x90c98521 },
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{ XFER_UDMA_3, 0x90cf8521 },
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{ XFER_UDMA_2, 0x90cf8521 },
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{ XFER_UDMA_1, 0x90cb8521 },
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{ XFER_UDMA_0, 0x90cb8521 },
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{ XFER_MW_DMA_2, 0xa0ca8521 },
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{ XFER_MW_DMA_1, 0xa0ca8532 },
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{ XFER_MW_DMA_0, 0xa0ca8575 },
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{ XFER_PIO_4, 0xc0ca8521 },
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{ XFER_PIO_3, 0xc0ca8532 },
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{ XFER_PIO_2, 0xc0ca8542 },
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{ XFER_PIO_1, 0xc0d08572 },
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{ XFER_PIO_0, 0xc0d08585 },
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{ 0, 0x01208585 }
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};
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/* from highpoint documentation. these are old values */
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static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
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/* { XFER_UDMA_5, 0x1A85F442, 0x16454e31 }, */
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{ XFER_UDMA_5, 0x16454e31 },
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{ XFER_UDMA_4, 0x16454e31 },
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{ XFER_UDMA_3, 0x166d4e31 },
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{ XFER_UDMA_2, 0x16494e31 },
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{ XFER_UDMA_1, 0x164d4e31 },
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{ XFER_UDMA_0, 0x16514e31 },
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{ XFER_MW_DMA_2, 0x26514e21 },
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{ XFER_MW_DMA_1, 0x26514e33 },
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{ XFER_MW_DMA_0, 0x26514e97 },
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{ XFER_PIO_4, 0x06514e21 },
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{ XFER_PIO_3, 0x06514e22 },
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{ XFER_PIO_2, 0x06514e33 },
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{ XFER_PIO_1, 0x06914e43 },
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{ XFER_PIO_0, 0x06914e57 },
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{ 0, 0x06514e57 }
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};
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static struct chipset_bus_clock_list_entry sixty_six_base_hpt370[] = {
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{ XFER_UDMA_5, 0x14846231 },
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{ XFER_UDMA_4, 0x14886231 },
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{ XFER_UDMA_3, 0x148c6231 },
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{ XFER_UDMA_2, 0x148c6231 },
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{ XFER_UDMA_1, 0x14906231 },
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{ XFER_UDMA_0, 0x14986231 },
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{ XFER_MW_DMA_2, 0x26514e21 },
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{ XFER_MW_DMA_1, 0x26514e33 },
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{ XFER_MW_DMA_0, 0x26514e97 },
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{ XFER_PIO_4, 0x06514e21 },
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{ XFER_PIO_3, 0x06514e22 },
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{ XFER_PIO_2, 0x06514e33 },
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{ XFER_PIO_1, 0x06914e43 },
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{ XFER_PIO_0, 0x06914e57 },
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{ 0, 0x06514e57 }
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};
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/* these are the current (4 sep 2001) timings from highpoint */
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static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
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{ XFER_UDMA_5, 0x12446231 },
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{ XFER_UDMA_4, 0x12446231 },
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{ XFER_UDMA_3, 0x126c6231 },
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{ XFER_UDMA_2, 0x12486231 },
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{ XFER_UDMA_1, 0x124c6233 },
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{ XFER_UDMA_0, 0x12506297 },
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{ XFER_MW_DMA_2, 0x22406c31 },
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{ XFER_MW_DMA_1, 0x22406c33 },
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{ XFER_MW_DMA_0, 0x22406c97 },
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{ XFER_PIO_4, 0x06414e31 },
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{ XFER_PIO_3, 0x06414e42 },
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{ XFER_PIO_2, 0x06414e53 },
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{ XFER_PIO_1, 0x06814e93 },
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{ XFER_PIO_0, 0x06814ea7 },
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{ 0, 0x06814ea7 }
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};
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/* 2x 33MHz timings */
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static struct chipset_bus_clock_list_entry sixty_six_base_hpt370a[] = {
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{ XFER_UDMA_5, 0x1488e673 },
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{ XFER_UDMA_4, 0x1488e673 },
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{ XFER_UDMA_3, 0x1498e673 },
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{ XFER_UDMA_2, 0x1490e673 },
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{ XFER_UDMA_1, 0x1498e677 },
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{ XFER_UDMA_0, 0x14a0e73f },
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{ XFER_MW_DMA_2, 0x2480fa73 },
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{ XFER_MW_DMA_1, 0x2480fa77 },
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{ XFER_MW_DMA_0, 0x2480fb3f },
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{ XFER_PIO_4, 0x0c82be73 },
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{ XFER_PIO_3, 0x0c82be95 },
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{ XFER_PIO_2, 0x0c82beb7 },
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{ XFER_PIO_1, 0x0d02bf37 },
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{ XFER_PIO_0, 0x0d02bf5f },
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{ 0, 0x0d02bf5f }
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};
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static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
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{ XFER_UDMA_5, 0x12848242 },
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{ XFER_UDMA_4, 0x12ac8242 },
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{ XFER_UDMA_3, 0x128c8242 },
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{ XFER_UDMA_2, 0x120c8242 },
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{ XFER_UDMA_1, 0x12148254 },
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{ XFER_UDMA_0, 0x121882ea },
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{ XFER_MW_DMA_2, 0x22808242 },
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{ XFER_MW_DMA_1, 0x22808254 },
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{ XFER_MW_DMA_0, 0x228082ea },
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{ XFER_PIO_4, 0x0a81f442 },
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{ XFER_PIO_3, 0x0a81f443 },
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{ XFER_PIO_2, 0x0a81f454 },
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{ XFER_PIO_1, 0x0ac1f465 },
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{ XFER_PIO_0, 0x0ac1f48a },
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{ 0, 0x0ac1f48a }
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};
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static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
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{ XFER_UDMA_6, 0x1c81dc62 },
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{ XFER_UDMA_5, 0x1c6ddc62 },
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{ XFER_UDMA_4, 0x1c8ddc62 },
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{ XFER_UDMA_3, 0x1c8edc62 }, /* checkme */
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{ XFER_UDMA_2, 0x1c91dc62 },
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{ XFER_UDMA_1, 0x1c9adc62 }, /* checkme */
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{ XFER_UDMA_0, 0x1c82dc62 }, /* checkme */
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{ XFER_MW_DMA_2, 0x2c829262 },
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{ XFER_MW_DMA_1, 0x2c829266 }, /* checkme */
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{ XFER_MW_DMA_0, 0x2c82922e }, /* checkme */
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{ XFER_PIO_4, 0x0c829c62 },
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{ XFER_PIO_3, 0x0c829c84 },
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{ XFER_PIO_2, 0x0c829ca6 },
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{ XFER_PIO_1, 0x0d029d26 },
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{ XFER_PIO_0, 0x0d029d5e },
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{ 0, 0x0d029d5e }
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};
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static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
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{ XFER_UDMA_5, 0x12848242 },
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{ XFER_UDMA_4, 0x12ac8242 },
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{ XFER_UDMA_3, 0x128c8242 },
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{ XFER_UDMA_2, 0x120c8242 },
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{ XFER_UDMA_1, 0x12148254 },
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{ XFER_UDMA_0, 0x121882ea },
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{ XFER_MW_DMA_2, 0x22808242 },
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{ XFER_MW_DMA_1, 0x22808254 },
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{ XFER_MW_DMA_0, 0x228082ea },
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{ XFER_PIO_4, 0x0a81f442 },
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{ XFER_PIO_3, 0x0a81f443 },
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{ XFER_PIO_2, 0x0a81f454 },
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{ XFER_PIO_1, 0x0ac1f465 },
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{ XFER_PIO_0, 0x0ac1f48a },
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{ 0, 0x0a81f443 }
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};
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static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
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{ XFER_UDMA_6, 0x1c869c62 },
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{ XFER_UDMA_5, 0x1cae9c62 },
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{ XFER_UDMA_4, 0x1c8a9c62 },
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{ XFER_UDMA_3, 0x1c8e9c62 },
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{ XFER_UDMA_2, 0x1c929c62 },
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{ XFER_UDMA_1, 0x1c9a9c62 },
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{ XFER_UDMA_0, 0x1c829c62 },
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{ XFER_MW_DMA_2, 0x2c829c62 },
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{ XFER_MW_DMA_1, 0x2c829c66 },
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{ XFER_MW_DMA_0, 0x2c829d2e },
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{ XFER_PIO_4, 0x0c829c62 },
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{ XFER_PIO_3, 0x0c829c84 },
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{ XFER_PIO_2, 0x0c829ca6 },
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{ XFER_PIO_1, 0x0d029d26 },
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{ XFER_PIO_0, 0x0d029d5e },
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{ 0, 0x0d029d26 }
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};
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static struct chipset_bus_clock_list_entry thirty_three_base_hpt374[] = {
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{ XFER_UDMA_6, 0x12808242 },
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{ XFER_UDMA_5, 0x12848242 },
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{ XFER_UDMA_4, 0x12ac8242 },
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{ XFER_UDMA_3, 0x128c8242 },
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{ XFER_UDMA_2, 0x120c8242 },
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{ XFER_UDMA_1, 0x12148254 },
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{ XFER_UDMA_0, 0x121882ea },
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{ XFER_MW_DMA_2, 0x22808242 },
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{ XFER_MW_DMA_1, 0x22808254 },
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{ XFER_MW_DMA_0, 0x228082ea },
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{ XFER_PIO_4, 0x0a81f442 },
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{ XFER_PIO_3, 0x0a81f443 },
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{ XFER_PIO_2, 0x0a81f454 },
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{ XFER_PIO_1, 0x0ac1f465 },
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{ XFER_PIO_0, 0x0ac1f48a },
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{ 0, 0x06814e93 }
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};
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#if 0
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static struct chipset_bus_clock_list_entry fifty_base_hpt374[] = {
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{ XFER_UDMA_6, },
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{ XFER_UDMA_5, },
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{ XFER_UDMA_4, },
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{ XFER_UDMA_3, },
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{ XFER_UDMA_2, },
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{ XFER_UDMA_1, },
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{ XFER_UDMA_0, },
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{ XFER_MW_DMA_2, },
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{ XFER_MW_DMA_1, },
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{ XFER_MW_DMA_0, },
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{ XFER_PIO_4, },
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{ XFER_PIO_3, },
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{ XFER_PIO_2, },
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{ XFER_PIO_1, },
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{ XFER_PIO_0, },
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{ 0, }
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};
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#endif
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#if 0
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static struct chipset_bus_clock_list_entry sixty_six_base_hpt374[] = {
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{ XFER_UDMA_6, 0x12406231 }, /* checkme */
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{ XFER_UDMA_5, 0x12446231 },
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0x14846231
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{ XFER_UDMA_4, 0x16814ea7 },
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0x14886231
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{ XFER_UDMA_3, 0x16814ea7 },
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0x148c6231
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{ XFER_UDMA_2, 0x16814ea7 },
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0x148c6231
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{ XFER_UDMA_1, 0x16814ea7 },
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0x14906231
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{ XFER_UDMA_0, 0x16814ea7 },
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0x14986231
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{ XFER_MW_DMA_2, 0x16814ea7 },
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0x26514e21
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{ XFER_MW_DMA_1, 0x16814ea7 },
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0x26514e97
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{ XFER_MW_DMA_0, 0x16814ea7 },
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0x26514e97
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{ XFER_PIO_4, 0x06814ea7 },
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0x06514e21
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{ XFER_PIO_3, 0x06814ea7 },
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0x06514e22
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{ XFER_PIO_2, 0x06814ea7 },
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0x06514e33
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{ XFER_PIO_1, 0x06814ea7 },
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0x06914e43
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{ XFER_PIO_0, 0x06814ea7 },
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0x06914e57
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{ 0, 0x06814ea7 }
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};
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#endif
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#define HPT366_DEBUG_DRIVE_INFO 0
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#define HPT374_ALLOW_ATA133_6 0
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#define HPT371_ALLOW_ATA133_6 0
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#define HPT302_ALLOW_ATA133_6 0
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#define HPT372_ALLOW_ATA133_6 1
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#define HPT370_ALLOW_ATA100_5 1
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#define HPT366_ALLOW_ATA66_4 1
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#define HPT366_ALLOW_ATA66_3 1
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#define HPT366_MAX_DEVS 8
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#define F_LOW_PCI_33 0x23
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#define F_LOW_PCI_40 0x29
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#define F_LOW_PCI_50 0x2d
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#define F_LOW_PCI_66 0x42
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static void init_setup_hpt366(struct pci_dev *, ide_pci_device_t *);
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static void init_setup_hpt37x(struct pci_dev *, ide_pci_device_t *);
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static void init_setup_hpt374(struct pci_dev *, ide_pci_device_t *);
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static unsigned int init_chipset_hpt366(struct pci_dev *, const char *);
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static void init_hwif_hpt366(ide_hwif_t *);
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static void init_dma_hpt366(ide_hwif_t *, unsigned long);
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static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
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{ /* 0 */
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.name = "HPT366",
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.init_setup = init_setup_hpt366,
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.init_chipset = init_chipset_hpt366,
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.init_hwif = init_hwif_hpt366,
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.init_dma = init_dma_hpt366,
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.channels = 2,
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.autodma = AUTODMA,
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.bootable = OFF_BOARD,
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.extra = 240
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},{ /* 1 */
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.name = "HPT372A",
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.init_setup = init_setup_hpt37x,
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.init_chipset = init_chipset_hpt366,
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.init_hwif = init_hwif_hpt366,
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.init_dma = init_dma_hpt366,
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.channels = 2,
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.autodma = AUTODMA,
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.bootable = OFF_BOARD,
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},{ /* 2 */
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.name = "HPT302",
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.init_setup = init_setup_hpt37x,
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.init_chipset = init_chipset_hpt366,
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.init_hwif = init_hwif_hpt366,
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.init_dma = init_dma_hpt366,
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.channels = 2,
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.autodma = AUTODMA,
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.bootable = OFF_BOARD,
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},{ /* 3 */
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.name = "HPT371",
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|
.init_setup = init_setup_hpt37x,
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.init_chipset = init_chipset_hpt366,
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.init_hwif = init_hwif_hpt366,
|
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.init_dma = init_dma_hpt366,
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.channels = 2,
|
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.autodma = AUTODMA,
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|
.bootable = OFF_BOARD,
|
|
},{ /* 4 */
|
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.name = "HPT374",
|
|
.init_setup = init_setup_hpt374,
|
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.init_chipset = init_chipset_hpt366,
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.init_hwif = init_hwif_hpt366,
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.init_dma = init_dma_hpt366,
|
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.channels = 2, /* 4 */
|
|
.autodma = AUTODMA,
|
|
.bootable = OFF_BOARD,
|
|
},{ /* 5 */
|
|
.name = "HPT372N",
|
|
.init_setup = init_setup_hpt37x,
|
|
.init_chipset = init_chipset_hpt366,
|
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.init_hwif = init_hwif_hpt366,
|
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.init_dma = init_dma_hpt366,
|
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.channels = 2, /* 4 */
|
|
.autodma = AUTODMA,
|
|
.bootable = OFF_BOARD,
|
|
}
|
|
};
|
|
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#endif /* HPT366_H */
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