383 lines
8.7 KiB
C
383 lines
8.7 KiB
C
#ifndef _ASM_M32R_SPINLOCK_H
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#define _ASM_M32R_SPINLOCK_H
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/*
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* linux/include/asm-m32r/spinlock.h
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*
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* M32R version:
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* Copyright (C) 2001, 2002 Hitoshi Yamamoto
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* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
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*/
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#include <linux/config.h> /* CONFIG_DEBUG_SPINLOCK, CONFIG_SMP */
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#include <linux/compiler.h>
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#include <asm/atomic.h>
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#include <asm/page.h>
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extern int printk(const char * fmt, ...)
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__attribute__ ((format (printf, 1, 2)));
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#define RW_LOCK_BIAS 0x01000000
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#define RW_LOCK_BIAS_STR "0x01000000"
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/* It seems that people are forgetting to
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* initialize their spinlocks properly, tsk tsk.
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* Remember to turn this off in 2.4. -ben
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*/
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#if defined(CONFIG_DEBUG_SPINLOCK)
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#define SPINLOCK_DEBUG 1
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#else
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#define SPINLOCK_DEBUG 0
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#endif
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*/
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typedef struct {
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volatile int lock;
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#if SPINLOCK_DEBUG
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unsigned magic;
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#endif
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#ifdef CONFIG_PREEMPT
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unsigned int break_lock;
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#endif
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} spinlock_t;
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#define SPINLOCK_MAGIC 0xdead4ead
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#if SPINLOCK_DEBUG
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#define SPINLOCK_MAGIC_INIT , SPINLOCK_MAGIC
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#else
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#define SPINLOCK_MAGIC_INIT /* */
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#endif
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#define SPIN_LOCK_UNLOCKED (spinlock_t) { 1 SPINLOCK_MAGIC_INIT }
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#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0)
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*/
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#define spin_is_locked(x) (*(volatile int *)(&(x)->lock) <= 0)
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#define spin_unlock_wait(x) do { barrier(); } while(spin_is_locked(x))
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#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock)
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/**
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* _raw_spin_trylock - Try spin lock and return a result
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* @lock: Pointer to the lock variable
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*
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* _raw_spin_trylock() tries to get the lock and returns a result.
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* On the m32r, the result value is 1 (= Success) or 0 (= Failure).
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*/
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static inline int _raw_spin_trylock(spinlock_t *lock)
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{
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int oldval;
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unsigned long tmp1, tmp2;
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/*
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* lock->lock : =1 : unlock
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* : <=0 : lock
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* {
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* oldval = lock->lock; <--+ need atomic operation
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* lock->lock = 0; <--+
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* }
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*/
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__asm__ __volatile__ (
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"# spin_trylock \n\t"
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"ldi %1, #0; \n\t"
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"mvfc %2, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r6", "%3")
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"lock %0, @%3; \n\t"
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"unlock %1, @%3; \n\t"
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"mvtc %2, psw; \n\t"
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: "=&r" (oldval), "=&r" (tmp1), "=&r" (tmp2)
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: "r" (&lock->lock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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return (oldval > 0);
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}
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static inline void _raw_spin_lock(spinlock_t *lock)
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{
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unsigned long tmp0, tmp1;
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#if SPINLOCK_DEBUG
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__label__ here;
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here:
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if (lock->magic != SPINLOCK_MAGIC) {
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printk("eip: %p\n", &&here);
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BUG();
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}
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#endif
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/*
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* lock->lock : =1 : unlock
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* : <=0 : lock
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*
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* for ( ; ; ) {
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* lock->lock -= 1; <-- need atomic operation
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* if (lock->lock == 0) break;
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* for ( ; lock->lock <= 0 ; );
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* }
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*/
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__asm__ __volatile__ (
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"# spin_lock \n\t"
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".fillinsn \n"
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"1: \n\t"
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"mvfc %1, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r6", "%2")
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"lock %0, @%2; \n\t"
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"addi %0, #-1; \n\t"
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"unlock %0, @%2; \n\t"
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"mvtc %1, psw; \n\t"
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"bltz %0, 2f; \n\t"
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LOCK_SECTION_START(".balign 4 \n\t")
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".fillinsn \n"
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"2: \n\t"
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"ld %0, @%2; \n\t"
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"bgtz %0, 1b; \n\t"
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"bra 2b; \n\t"
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LOCK_SECTION_END
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: "=&r" (tmp0), "=&r" (tmp1)
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: "r" (&lock->lock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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}
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static inline void _raw_spin_unlock(spinlock_t *lock)
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{
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#if SPINLOCK_DEBUG
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BUG_ON(lock->magic != SPINLOCK_MAGIC);
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BUG_ON(!spin_is_locked(lock));
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#endif
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mb();
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lock->lock = 1;
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}
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/*
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* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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typedef struct {
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volatile int lock;
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#if SPINLOCK_DEBUG
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unsigned magic;
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#endif
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#ifdef CONFIG_PREEMPT
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unsigned int break_lock;
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#endif
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} rwlock_t;
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#define RWLOCK_MAGIC 0xdeaf1eed
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#if SPINLOCK_DEBUG
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#define RWLOCK_MAGIC_INIT , RWLOCK_MAGIC
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#else
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#define RWLOCK_MAGIC_INIT /* */
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#endif
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#define RW_LOCK_UNLOCKED (rwlock_t) { RW_LOCK_BIAS RWLOCK_MAGIC_INIT }
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#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while(0)
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#define rwlock_is_locked(x) ((x)->lock != RW_LOCK_BIAS)
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/*
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* On x86, we implement read-write locks as a 32-bit counter
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* with the high bit (sign) being the "contended" bit.
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*
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* The inline assembly is non-obvious. Think about it.
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*
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* Changed to use the same technique as rw semaphores. See
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* semaphore.h for details. -ben
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*/
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/* the spinlock helpers are in arch/i386/kernel/semaphore.c */
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static inline void _raw_read_lock(rwlock_t *rw)
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{
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unsigned long tmp0, tmp1;
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#if SPINLOCK_DEBUG
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BUG_ON(rw->magic != RWLOCK_MAGIC);
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#endif
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/*
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* rw->lock : >0 : unlock
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* : <=0 : lock
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*
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* for ( ; ; ) {
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* rw->lock -= 1; <-- need atomic operation
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* if (rw->lock >= 0) break;
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* rw->lock += 1; <-- need atomic operation
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* for ( ; rw->lock <= 0 ; );
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* }
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*/
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__asm__ __volatile__ (
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"# read_lock \n\t"
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".fillinsn \n"
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"1: \n\t"
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"mvfc %1, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r6", "%2")
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"lock %0, @%2; \n\t"
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"addi %0, #-1; \n\t"
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"unlock %0, @%2; \n\t"
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"mvtc %1, psw; \n\t"
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"bltz %0, 2f; \n\t"
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LOCK_SECTION_START(".balign 4 \n\t")
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".fillinsn \n"
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"2: \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r6", "%2")
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"lock %0, @%2; \n\t"
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"addi %0, #1; \n\t"
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"unlock %0, @%2; \n\t"
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"mvtc %1, psw; \n\t"
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".fillinsn \n"
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"3: \n\t"
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"ld %0, @%2; \n\t"
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"bgtz %0, 1b; \n\t"
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"bra 3b; \n\t"
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LOCK_SECTION_END
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: "=&r" (tmp0), "=&r" (tmp1)
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: "r" (&rw->lock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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}
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static inline void _raw_write_lock(rwlock_t *rw)
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{
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unsigned long tmp0, tmp1, tmp2;
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#if SPINLOCK_DEBUG
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BUG_ON(rw->magic != RWLOCK_MAGIC);
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#endif
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/*
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* rw->lock : =RW_LOCK_BIAS_STR : unlock
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* : !=RW_LOCK_BIAS_STR : lock
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*
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* for ( ; ; ) {
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* rw->lock -= RW_LOCK_BIAS_STR; <-- need atomic operation
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* if (rw->lock == 0) break;
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* rw->lock += RW_LOCK_BIAS_STR; <-- need atomic operation
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* for ( ; rw->lock != RW_LOCK_BIAS_STR ; ) ;
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* }
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*/
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__asm__ __volatile__ (
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"# write_lock \n\t"
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"seth %1, #high(" RW_LOCK_BIAS_STR "); \n\t"
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"or3 %1, %1, #low(" RW_LOCK_BIAS_STR "); \n\t"
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".fillinsn \n"
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"1: \n\t"
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"mvfc %2, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r7", "%3")
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"lock %0, @%3; \n\t"
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"sub %0, %1; \n\t"
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"unlock %0, @%3; \n\t"
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"mvtc %2, psw; \n\t"
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"bnez %0, 2f; \n\t"
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LOCK_SECTION_START(".balign 4 \n\t")
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".fillinsn \n"
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"2: \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r7", "%3")
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"lock %0, @%3; \n\t"
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"add %0, %1; \n\t"
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"unlock %0, @%3; \n\t"
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"mvtc %2, psw; \n\t"
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".fillinsn \n"
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"3: \n\t"
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"ld %0, @%3; \n\t"
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"beq %0, %1, 1b; \n\t"
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"bra 3b; \n\t"
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LOCK_SECTION_END
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: "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r7"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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}
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static inline void _raw_read_unlock(rwlock_t *rw)
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{
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unsigned long tmp0, tmp1;
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__asm__ __volatile__ (
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"# read_unlock \n\t"
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"mvfc %1, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r6", "%2")
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"lock %0, @%2; \n\t"
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"addi %0, #1; \n\t"
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"unlock %0, @%2; \n\t"
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"mvtc %1, psw; \n\t"
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: "=&r" (tmp0), "=&r" (tmp1)
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: "r" (&rw->lock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r6"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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}
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static inline void _raw_write_unlock(rwlock_t *rw)
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{
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unsigned long tmp0, tmp1, tmp2;
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__asm__ __volatile__ (
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"# write_unlock \n\t"
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"seth %1, #high(" RW_LOCK_BIAS_STR "); \n\t"
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"or3 %1, %1, #low(" RW_LOCK_BIAS_STR "); \n\t"
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"mvfc %2, psw; \n\t"
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"clrpsw #0x40 -> nop; \n\t"
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DCACHE_CLEAR("%0", "r7", "%3")
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"lock %0, @%3; \n\t"
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"add %0, %1; \n\t"
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"unlock %0, @%3; \n\t"
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"mvtc %2, psw; \n\t"
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: "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "memory"
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#ifdef CONFIG_CHIP_M32700_TS1
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, "r7"
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#endif /* CONFIG_CHIP_M32700_TS1 */
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);
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}
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#define _raw_read_trylock(lock) generic_raw_read_trylock(lock)
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static inline int _raw_write_trylock(rwlock_t *lock)
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{
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atomic_t *count = (atomic_t *)lock;
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if (atomic_sub_and_test(RW_LOCK_BIAS, count))
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return 1;
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atomic_add(RW_LOCK_BIAS, count);
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return 0;
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}
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#endif /* _ASM_M32R_SPINLOCK_H */
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